Showing papers in "IEEE Transactions on Circuits and Systems in 2011"
TL;DR: Based on the estimation, an observer-based fault-tolerant control scheme is developed to stabilize the resulting closed-loop system and a numerical example is presented to illustrate the effectiveness and applicability of the proposed technique.
Abstract: This paper investigates the problem of sensor fault estimation and fault-tolerant control for Markovian jump systems with time delay and Lipschitz nonlinearities. The issues involved here are: i) sensor faults; ii) model Lipchitz nonlinearities; iii) system structure changes governed by Markovian jumping parameters; and iv) time delay in system states. Such type of mathematical models can represent a large number of practical systems in the actual engineering. A new estimation technique (named proportional and derivative sliding mode observer) is developed to deal with this design problem. The proposed observer is mode-dependent type in which a derivative gain and a proportional gain are introduced to provide more design freedom, and a discontinuous input term is introduced to eliminate the effects of sensor faults. By employing the developed estimation technique, the asymptotic estimations of system states and sensor faults can be obtained simultaneously. Based on the estimation, an observer-based fault-tolerant control scheme is developed to stabilize the resulting closed-loop system. Finally, a numerical example is presented to illustrate the effectiveness and applicability of the proposed technique.
274 citations
TL;DR: This paper presents a highly efficient, ultra-low-voltage active full wave rectifier using a bulk-input comparator working in the subthreshold region to drive the switch of the active diode.
Abstract: This paper presents a highly efficient, ultra-low-voltage active full wave rectifier. A two-stage concept is used including a first passive stage and only one active diode as second stage. A bulk-input comparator working in the subthreshold region is used to drive the switch of the active diode. The voltage drop over the rectifier is some tens of millivolt, which results in voltage and power efficiencies of over 90%. The design was successfully implemented in an 0.35 μm CMOS technology. The measured power consumption of the comparator is 266 nW@500 mV and the minimum operating voltage is 380 mV. Input voltages with frequencies up to 10 kHz can be rectified.
114 citations
TL;DR: A CMOS single-chip gas recognition circuit, which encodes sensor array outputs into a unique sequence of spikes with the firing delay mapping the strength of the stimulation across the array, and relies on a novel sensor calibration technique that does not require control or prior knowledge of the gas concentration.
Abstract: This paper presents a CMOS single-chip gas recognition circuit, which encodes sensor array outputs into a unique sequence of spikes with the firing delay mapping the strength of the stimulation across the array. The proposed gas recognition circuit examines the generated spike pattern of relative excitations across the population of sensors and looks for a match within a library of 2-D spatio-temporal spike signatures. Each signature is drift insensitive, concentration invariant and is also a unique characteristic of the target gas. This VLSI friendly approach relies on a simple spatio-temporal code matching instead of existing computationally expensive pattern matching statistical techniques. In addition, it relies on a novel sensor calibration technique that does not require control or prior knowledge of the gas concentration. The proposed gas recognition circuit was implemented in a 0.35 μm CMOS process and characterized using an in-house fabricated 4 × 4 tin oxide gas sensor array. Experimental results show a correct detection rate of 94.9% when the gas sensor array is exposed to propane, ethanol and carbon monoxide.
80 citations
TL;DR: This paper revisits the digitization journey of the traditional charge-pump PLL that has resulted in an all-digital frequency synthesizer with the best-in-class RF performance while occupying only a fraction of the silicon area and consuming only a fractions of the power.
Abstract: The past several years have successfully brought all-digital techniques to the RF frequency synthesis, which could arguably be considered one of the last strong bastions of the traditionally-analog design approaches. With their high sensitivity and high dynamic range requirements, the RF circuits have long had a good excuse to avoid any possible source of digital switching activity. With the constant scaling of CMOS feature size and the merciless push for integration, the existence of almost free and powerful digital logic could not go unnoticed. Hence, the environment was ripe to transform the RF functions into digital realizations, as well as to apply digital assistance to help with the performance of RF circuits. This paper revisits the digitization journey of the traditional charge-pump PLL that has resulted in an all-digital frequency synthesizer with the best-in-class RF performance while occupying only a fraction of the silicon area and consuming a fraction of the power. The paper also offers a few novel techniques to further improve area, current consumption, testability, and reliability of frequency synthesizers.
79 citations
TL;DR: Results show that the proposed ABB compensates effectively for NBTI aging and process variations and enhances the soft errors immunity of the SRAM cell by reducing the critical charge degradation and the SNM degradation.
Abstract: Reliability and variability have become big design challenges facing submicrometer SRAM designers. A low area overhead adaptive body bias (ABB) circuit is proposed in this paper to compensate for NBTI aging and process variations to improve the SRAM reliability and yield. The proposed ABB circuit consists of a threshold voltage sensing circuit and an on-chip analog controller. Postlayout simulation results, referring to an industrial hardware-calibrated STMicroelectronics 65 nm CMOS technology transistor model, are presented. The transistor model contains process variations and NBTI aging model cards, which are declared by STMicroelectronics to be silicon verified. Cadence RelXpert, Virtuoso Spectre, and Virtuoso UltraSim tools are used to estimate the NBTI aging and process variations impacts on the SRAM array. These results show that the proposed ABB compensates effectively for NBTI aging and process variations. For example, the proposed ABB reduces the read failure probability from 0.32% to 0.05% and the SNM degradation from 10.9% to 2.6% at 10 years aging time. In addition, the proposed ABB enhances the soft errors immunity of the SRAM cell by reducing the critical charge degradation from 12.7% to 3.4% at 10 years aging time.
69 citations
TL;DR: This paper illustrates how floating-gate and quasi-floating gate MOS transistors can be efficiently employed by employing them in the design of two transconductors, which have been fabricated in a 0.5 μm CMOS process.
Abstract: Floating-gate and quasi-floating gate MOS transistors can be efficiently employed to design CMOS transconductors. These transistors allow achievement of relevant features in a compact and simple way, such as rail-to-rail input range, continuous transconductance tuning, and class AB operation. This paper illustrates how these techniques can be applied by employing them in the design of two transconductors, which have been fabricated in a 0.5 μm CMOS process. Measurement results confirm the advantages of the proposed approach.
67 citations
TL;DR: A cyclic Vernier time-to-digital converter (TDC) with digitally controlled oscillators (DCOs) targeted for a synthesizable all-digital phase locked loop (ADPLL).
Abstract: This paper presents a cyclic Vernier time-to-digital converter (TDC) with digitally controlled oscillators (DCOs), targeted for a synthesizable all-digital phase locked loop (ADPLL). All functional blocks in the TDC are implemented with digital standard cells and placed-and-routed (PR thus, the TDC is portable and scalable to other process technologies. The effect of P&R mismatch is characterized in calibration mode, and utilized to achieve a minimum TDC resolution of 5.5 ps. The TDC was fabricated in a 65 nm CMOS process, and occupies 0.006 mm2.
59 citations
TL;DR: A low power content addressable memory (CAM) using low swing search lines that saves 83.9% and 97.3% of the power in the search lines and the match lines, respectively.
Abstract: This paper proposes a low power content addressable memory (CAM) using low swing search lines. The CAM reduces the swing voltage and the power consumption of the search lines by using CAM cells as amplifiers. The CAM cells compare the stored data with the low swing search data on the search lines. The CAM also reduces the power consumption of match lines by using low swing NAND-NOR match lines. The 128 × 144 bit CAM chip was fabricated using a 0.18 μm CMOS process with VDD = 1.8 V. The CAM chip dissipates 2.82 fj/bit/search and consumes 8.7% of the power used by a conventional dynamic NOR-type CAM. It saves 83.9% and 97.3% of the power in the search lines and the match lines, respectively. Its area is 1.14 mm2. Its maximum operating frequency is 210 MHz.
50 citations
TL;DR: The yield model is found to be very accurate and can be easily applied to the analysis and yield optimization of novel array structures, DRAM cell leakage analysis, sense amplifier offset voltage requirements, and core supply voltage optimization.
Abstract: In this paper the electric yield of DRAM core circuits is investigated by means of a statistical approach that incorporates a hierarchical linear Gaussian model for the DRAM core sensing process and a lognormal distribution model for the DRAM cell leakage. Analytical yield expressions are obtained and found to be dominated by two independent sources-either the lognormal distribution of the cell leakage components or the Gaussian distribution depending on the array structural parameters, parasitic, and the sense amplifier offset voltage. Analytical yield analysis is conducted for several different DRAM architectures and compared to measurements from signal margin analysis and data retention tests. The yield model is found to be very accurate. Thanks to the short computation time, it can be easily applied to the analysis and yield optimization of novel array structures, DRAM cell leakage analysis, sense amplifier offset voltage requirements, and core supply voltage optimization. It also paves the way for the design for yield of other memory circuits.
49 citations
TL;DR: The experimental results show that the proposed RNS scaler is smaller and faster than the most area-efficient adder- based design and the fastest ROM-based design besides being the most power efficient among all scalers evaluated for the same three-moduli set.
Abstract: Scaling in RNS has always been conceived as a performance bottleneck similar to the residue-to-binary conversion problem due to the inefficient intermodulo operation. In this paper, a simple and fast scaling algorithm for the three-moduli set {2n - 1, 2n, 2n + 1} RNS is proposed. The complexity of intermodulo operation has been resolved by a new formulation of scaling an integer in RNS domain by one of its moduli. By elegant exploitation of the Chinese Remainder Theorem and the number theoretic properties for this moduli set, the design can be readily implemented by a standard cell based design methodology. The low cost VLSI architecture without any read-only memory (ROM) makes it easier to fuse into and pipeline with other residue arithmetic operations of a RNS-based processor to increase the throughput rate. The proposed RNS scaler possesses zero scaling error and has a critical path delay of only 2[log2n]+ 9 units in unit-gate model. Besides the scaled residue numbers, the scaled integer in normal binary representation is also produced as a byproduct of this process, which saves the residue-to-binary converter when the binary representation of scaled integer is also required. Our experimental results show that the proposed RNS scaler is smaller and faster than the most area-efficient adder-based design and the fastest ROM-based design besides being the most power efficient among all scalers evaluated for the same three-moduli set.
35 citations
TL;DR: How to design low-power switched-inductor converters capable of producing net energy gains when supplied from piezoelectric and electrostatic transducers is described, and experimental results from prototype embodiments are presented.
Abstract: The potential application space for miniaturized systems like wireless microsensors is expansive, from reconnaissance mission work and remote sensors to biomedical implants and disposable consumer products. Conforming to microscale dimensions, however, constrains energy and power to such an extent that sustaining critical power-hungry functions like wireless communication is problematical. Harvesting ambient kinetic energy offers an appealing alternative, except the act of transferring energy requires power that could easily exceed what the harvester generates in the first place. This paper reviews piezoelectric and electrostatic harvester circuits, describes how to design low-power switched-inductor converters capable of producing net energy gains when supplied from piezoelectric and electrostatic transducers, and presents experimental results from prototype embodiments. In the electrostatic case shown, the controller dissipated 0.91 nJ per cycle and the switched-inductor precharger achieved 90.3% efficiency to allow the harvester to net a gain of 2.47 nJ per cycle from a capacitor that oscillated between 157 and 991 pF. The piezoelectric counterpart harnessed 1.6 to 29.6 μW from weak periodic vibrations with 0.05-0.16- m/s2 accelerations and 65.3 μJ from (impact-produced) nonperiodic motion.
TL;DR: It is shown how linear complementarity systems can be used to model the behavior of a wide class of power converters and it is proved that the backward zero-order-hold technique preserves passivity through the discretization and allows to determine the unique solution of the complementarity problem.
Abstract: Computation of periodic steady state in nonlinear circuits is a key issue. Power electronics converters represent an interesting class of switched nonlinear circuits. The behavior of the converter is obtained by the commutations of the electronic devices which determine the switchings among the different converter modes. Switchings can be classified as external, if forced by directly manipulable control variables, and internal if determined by state dependent conditions. The presence of internal switchings makes it difficult to know a priori the sequence of modes and also open loop steady-state behaviors are difficult to be obtained. In this paper the complementarity modeling framework is proposed as a possible approach for computing periodic steady-state oscillations in power converters with internal switchings. It is shown how linear complementarity systems can be used to model the behavior of a wide class of power converters. The discretization of such model allows to formulate a static complementarity problem whose solution provides the steady-state oscillation of the converter. It is proved that the backward zero-order-hold technique preserves passivity through the discretization and allows to determine the unique solution of the complementarity problem. A resonant converter and a dc/dc voltage-mode controlled buck converter are used as examples.
TL;DR: The proposed circuit combines negative feedback and the compressive I-V characteristic of a class-AB weak inversion transconductor to achieve low switching error, high signal-to-noise ratio and high dynamic range from a low supply voltage and very low current consumption.
Abstract: This paper proposes the design of a current-mode sample and hold circuit using subthreshold MOSFETs. The proposed circuit combines negative feedback and the compressive I-V characteristic of a class-AB weak inversion transconductor to achieve low switching error, high signal-to-noise ratio and high dynamic range from a low supply voltage and very low current consumption. The paper also provides a feedback analysis of current mode sample and hold circuits. Several design issues including circuit stability, mismatch, linearity, noise, and power consumption are discussed and a comparison of class-A and class-AB versions of subthreshold sample and hold circuits is made. The design verification of the proposed class-AB current mode sample and hold circuit is done by circuit simulations using 0.13 μm CMOS model parameters. The results show that, from a 0.6 V supply and with a power consumption of 27.5 nW, the proposed circuit provides 73 dB signal-to-noise ratio, 77 dB dynamic range, and a figure of merit of 1.9 nW/MHz.
TL;DR: The experimental results show that the spur-free dynamic range (SFDR) of the blind identification digital receiver achieves about 20-dB higher than that of the traditional receiver under multitone or 16-QAM bandpass signal excitation.
Abstract: As the commonly used wideband software radio receiver does not possess the performance of a high linear dynamic range under multiple signal excitation, a new type of adaptive wideband digital receiver architecture is proposed and designed based on blind nonlinear system identification. The traditional narrowband linear receiving and channelizing technologies should not be applied to deal with the complicated multiple-signal excitation with unknown or time-varying characteristics of time domain or frequency domain. Here, the harmonic and the intermodulation components brought about by the wideband digital receiver are firstly identified and extracted in the frequency domain, then a blind identification criterion for minimizing the short-time energy of the nonlinear components is designed, and the steepest descent method (SDM) or the recursive least square (RLS) algorithm is applied to extract and update iteratively the parameters of the nonlinear behavior model of the wideband digital receiver. Finally, the updated model is utilized to compensate the nonlinear distortion of the receiver in real time. The experimental results show that the spur-free dynamic range (SFDR) of the blind identification digital receiver achieves about 20-dB higher than that of the traditional receiver under multitone or 16-QAM bandpass signal excitation. As regards the large bandwidth and the high power efficiency of the RF front end and ADC circuits, the blind identification receiver architecture is helpful for detecting weak signal in concomitance with in-band or out-of-band strong jammers.
TL;DR: An inherently linear current division network (CDN) preserving the high linearity property of the active RC technique while providing wide tuning characteristics is adopted and a reconfigurable filter exhibiting complex bandpass and normal lowpass responses is realized.
Abstract: A new approach providing the active-RC integrator with programmable time constant is proposed. An inherently linear current division network (CDN) preserving the high linearity property of the active RC technique while providing wide tuning characteristics is adopted. The proposed integrator provides wider tuning range, and higher tuning resolution accompanied with better linearity and/or reduced area than what could be obtained from capacitor and resistor banks. The proposed integrator uses two opamps per integrator just like its MOSFET-C counterpart but it inherently exhibits better linearity and wider tuning range particularly for low voltage supply. A reconfigurable filter exhibiting complex bandpass and normal lowpass responses is realized. Experimental results obtained from a 4th-order filter fabricated in a standard 0.18 μm CMOS process are given. The complex and lowpass filters achieve in-band spurious-free dynamic ranges (SFDRs) of about 70 dB and 71 dB for bandwidths of 1 MHz and 5.5 MHz, respectively.
TL;DR: This work performed electrical simulations of learning for an array of 24 nanotube memory devices corresponding to a 3 input × 3 output neural layer that revealed successful learning of separable logic functions within very few epochs, even when a realistic variability of nanotubes diameter was taken into account.
Abstract: We present an original method to implement neuro-inspired supervised learning for a synaptic array based on carbon nanotube devices. The device characteristics required to implement on chip learning within a crossbar of carbon nanotube field effect transistors (CNTFETs) as synaptic arrays were experimentally demonstrated and accurately modeled through a specific electrical compact model. We performed electrical simulations of learning for an array of 24 nanotube memory devices corresponding to a 3 input × 3 output neural layer that revealed successful learning of separable logic functions within very few epochs, even when a realistic variability of nanotube diameter was taken into account. Such a learning approach opens the way to the use of high-density synaptic arrays as generic logic blocks in configurable circuits.
TL;DR: This paper presents a serializer/deserializer scheme for asynchronous address event representation (AER) bit-serial interchip communications that allows to stop physical communication between data events, so that no “comma” characters need to be transmitted during these pauses.
Abstract: This paper presents a serializer/deserializer scheme for asynchronous address event representation (AER) bit-serial interchip communications. Each serial AER (sAER) link uses four wires: a micro strip pair for low voltage differential signaling (LVDS) and two handshaking lines. Each event is represented by a 32-bit word. Two extra preamble bits are used for alignment. Transmission clock is embedded in the data using Manchester encoding. As opposed to conventional LVDS links, the presented approach allows to stop physical communication between data events, so that no “comma” characters need to be transmitted during these pauses. As soon as a new event needs to be transmitted, the link recovers immediately thanks to a built-in control voltage memorization circuit. As a result, power consumption of the serializer and deserializer circuits is proportional to data event rate. The approach is also highly tolerant to clock jitter, due to the asynchronous nature and the Manchester encoding. A chip test prototype has been fabricated in standard 0.35 μm CMOS including a pair of Serializer and Deserializer circuits. Maximum measured event transmission rate is 15 Meps (mega events per second) for 32-bit events, with a maximum bit transmission speed of 670 Mbps (mega bits per second).
TL;DR: A novel channel estimator/predictor for OFDM systems over time-varying channels using a recursive formulation of a basis expansion model (BEM) based on an approximated discrete cosine transform (DCT) using a steady-state Kalman filter.
Abstract: We present a novel channel estimator/predictor for OFDM systems over time-varying channels using a recursive formulation of a basis expansion model (BEM) based on an approximated discrete cosine transform (DCT). We derive a recursive implementation of the approximated DCT-BEM for tracking time-varying channels based on a filter bank. The recursive approximated DCT-BEM structure is then used for long range channel prediction by proper scaling and time extrapolation of the filter bank. As the implicit BEM is time invariant we further simplify the implementation by employing a steady-state Kalman filter whose overall complexity is comparable to an LMS algorithm. The derived predictor outperforms, in terms of predictor range, previously proposed long range predictors that are based on autoregressive (AR) modeling of the time-varying channel. For a similar performance, in terms of MSE, the computational complexity of the proposed predictor is significantly lower than conventional sum-of-sinusoids (SOS) channel predictors as no channel delays nor Doppler frequencies need to be estimated.
TL;DR: This controller is developed with the aim to deal with the unknown resistive component of the load as well as to minimize the dissipated energy and current peaks, what is very important in the field of microelectronics.
Abstract: Dynamic voltage scaling (DVS) is an important method in managing dynamically the system supply voltage for efficient power reduction. This approach is applied in very large scale integration (VLSI). A dc-dc converter is an electronic device which allows to vary the voltage and, thus, to implement DVS technique. In this paper, a high-performance controller is presented for a novel discrete DVS converter. This controller is developed with the aim to deal with the unknown resistive component of the load as well as to minimize the dissipated energy and current peaks, what is very important in the field of microelectronics. Current peaks and power consumption are minimized by computing an optimal evolution for the voltage reference. Likewise, an adaptive controller is proposed to deal with the unknown load resistive parameter. Consequently, the obtained advanced controller can acquires a high consideration on electronic devices.
TL;DR: Algorithms to solve the reachability problem for power electronics converters operating under both open- and closed-loop control are provided along with simulations illustrating the proposed method.
Abstract: A method for large-signal behavior verification of power electronics dc-dc converters subject to uncertain variations in operating conditions is proposed. This method relies on the computation of the reach set, i.e., the set of all possible trajectories that arise from different initial conditions, unknown-but-bounded inputs, and inherent switching. Large-signal behavior verification is accomplished by checking that the reach set remains within the region of state space defined by performance requirements, e.g., output voltage tolerance specifications, component voltage and current limits. Algorithms to solve the reachability problem for power electronics converters operating under both open- and closed-loop control are provided along with simulations illustrating the proposed method.
TL;DR: A hardware based backtracking scheme to break the trapping sets at runtime for lowering the error floor of quasi-cyclic LDPC codes and it is shown that the increase in latency due to backtracking is modest in the average case.
Abstract: Emerging applications such as flash-based storage systems and 10 gigabit Ethernet require that there is no error floor even at bit error rates as low as 10-12 or so. It has been found that trapping sets are responsible for the error floors of many LDPC codes with AWGN channels. This paper presents a hardware based backtracking scheme to break the trapping sets at runtime for lowering the error floor of quasi-cyclic LDPC codes. Backtracking is implemented as a self-contained module that can be interfaced to any generic reconfigurable iterative decoder for QC-LDPC codes. The backtracking module and a reconfigurable decoder are implemented with a FPGA and an 180 nm standard cell library. The results indicate that the overhead of backtracking is modest - about 5% in terms of logic and 13% in terms of memory for the first level backtracking and 14% in terms of logic and 46% in terms of memory for a two-level backtracking scheme. Furthermore, it is shown that the increase in latency due to backtracking is modest in the average case and can be controlled by the system designer by choosing the appropriate values for the number of trials and the number of iterations of the backtracking module.
TL;DR: Higher order shaping and reduction of redistributed noise at intermediate offset frequencies are possible using PPM with a high-pass shaped modulating sequence and pulse repetition and their nonidealities are discussed.
Abstract: Randomizing the positions of charge pump current pulses in a PLL breaks their periodicity and redistributes the reference spurs into broadband noise. Closed form expressions for the power spectral density (PSD) of pulse position modulated (PPM) signals are derived and intuitive explanations for the results are given. The redistributed noise has a high-pass shape and does not affect the close in phase noise of the PLL. PPM using a uniformly distributed i.i.d. sequence completely removes the spurs and provides a first-order shaping of redistributed noise. Higher order shaping and reduction of redistributed noise at intermediate offset frequencies are possible using PPM with a high-pass shaped modulating sequence and pulse repetition. Circuit implementations of these techniques are given and their nonidealities are discussed. Simulation results from a 1 GHz PLL operating from a reference frequency of 20 MHz and a bandwidth of 1 MHz confirm the results of the analysis and viability of the proposed techniques. In the presence of nonidealities spurs can be reduced by at least 13 dB without any trimming of the delays in the PPM circuits and by 25 dB after trimming the delays to within 5% of the nominal value.
TL;DR: It is shown that common peaking methods, although providing significant signal bandwidth enhancement ratios (BWER), are limited to 30%-50% of their speed potential by output matching requirements.
Abstract: This paper presents a general analysis of peaking methods in output stages of amplifiers for broadband communication systems It is shown that common peaking methods, although providing significant signal bandwidth enhancement ratios (BWER), are limited to 30%-50% of their speed potential by output matching requirements A modified T-coil peaking is analyzed which enhances both signal bandwidth and output matching frequency range by up to 200% compared to common peaking methods A broadband amplifier using this inductive output matching with 69-GHz bandwidth implemented in a 025 μm SiGe BiCMOS technology is presented to prove the validity of the analysis
TL;DR: An unified signal flow graph (USFG) model is developed, tailored for integrated reconfigurable switched-capacitor (SC) power converters, and system transfer function and I/O impedance can be evaluated based on it.
Abstract: A systematic design approach using signal flow graph (SFG) is presented in this paper, tailored for integrated reconfigurable switched-capacitor (SC) power converters. To achieve an optimal power stage, an unified signal flow graph (USFG) model is developed. System transfer function and I/O impedance can be evaluated based on it. To verify the design approach, the paper demonstrates a step-up/down reconfigurable SC power converter with five optional gain ratios. A dual-loop control scheme is employed to reconfigure the converter according to the instantaneous line/load conditions. A low-power, digital controller is designed in the subthreshold region for the feedback control loop. The converter was fabricated with a 130-nm CMOS process. Experimental results show that its output can be continuously regulated from 0.4 to 2.2 V, while allowing the input voltage to randomly vary between 0.9 and 1.5 V. The line regulation is maintained below 1.4%, with a lowest value of 0.07%. The maximum efficiency of 90.22% is measured at 0.55-V output voltage and 20-mW load.
TL;DR: A framework for robust design of continuous-time ΣΔ modulators is presented and is able to find modulators that are robust to excess loop delay, clock jitter and coefficient variations.
Abstract: In this paper we present a framework for robust design of continuous-time ΣΔ modulators. The approach allows to find a modulator which maintains its performance (stability, guar anteed peak SNR, . . .) over all the foreseen parasitic effects, provided it exists. For this purpose, we have introduced the S-figure as a criterion for the robustness of a continuous-time ΣΔ modulator. This figure, inspired by the worst-case-distance methodology, indicates how close a design is to violating one of its performance requirements. Optimal robustness is obtained by optimizing this S-figure. The approach is illustrated through various design examples and is able to find modulators that are robust to excess loop delay, clock jitter and coefficient variations. As an application of the approach, we have quantified the effect of coefficient trimming. Even with poor trim resolution, good performance can be achieved provided beneficial initial system parameters are chosen. Another example illustrates the fact that also the out-of-band peaking behavior of the signal transfer function can be controlled with our design framework.
TL;DR: A novel transistor-level synthesis procedure for pipeline ADCs is presented, able to directly map high-level converter specifications onto transistor sizes and biasing conditions, based on the combination of behavioral models for performance evaluation, optimization routines to minimize the power and area consumption, and an algorithm to efficiently constraint the converter design space.
Abstract: A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the combination of behavioral models for performance evaluation, optimization routines to minimize the power and area consumption of the circuit solution, and an algorithm to efficiently constraint the converter design space. This algorithm precludes the cost of lengthy bottom-up verifications and speeds up the synthesis task. The approach is herein demonstrated via the design of a 0.13 μm CMOS 10 bits@60 MS/s pipeline ADC with energy consumption per conversion of only 0.54 pJ@1 MHz, making it one of the most energy-efficient 10-bit video-rate pipeline ADCs reported to date. The computational cost of this design is of only 25 min of CPU time, and includes the evaluation of 13 different pipeline architectures potentially feasible for the targeted specifications. The optimum design derived from the synthesis procedure has been fine tuned to support PVT variations, laid out together with other auxiliary blocks, and fabricated. The experimental results show a power consumption of 23 mW@1.2 V and an effective resolution of 9.47-bit@1 MHz. Bearing in mind that no specific power reduction strategy has been applied; the mentioned results confirm the reliability of the proposed approach.
TL;DR: A pulse digitizing approach for time-of-arrival pulse radio based ranging that is superior in terms of performance versus power to classic A/D conversion and a new SNDR metric are introduced, easing performance comparison of pulse digitizers.
Abstract: A pulse digitizing approach for time-of-arrival pulse radio based ranging is introduced. It is based on a bank of time-to-digital converter (TDC) cores. A comparator bank triggers these multiple TDCs. This multiple event approach has advantages over classic single TDC solutions when facing unknown channel gains, noise corruption, and strong fading channel behavior. Pulses are digitized in a way that is superior in terms of performance versus power to classic A/D conversion. A power effort figure ξ and a new SNDR metric are introduced, easing performance comparison of pulse digitizers. A low power 8 channel digitizing system with a resolution of δtring=62.5 ps is presented for a cm accurate ranging application. The asynchronous, event-based nature of the architecture requires nonstrobed comparators to fire value crossing events. A dynamic range of 800:1 is realized. The digitization device is designed for 130 nm standard CMOS. An analog-baseband front-end I-Q energy detection and comparator threshold level configuration D/As are added to the design. The complete system is designed to consume 4 mW.
TL;DR: This paper presents a low-cost production test strategy for digitally-calibrated analog-to-digital converters (ADCs) that incorporate an equalization-based background calibration scheme that significantly reduces calibration time without compromising test coverage.
Abstract: This paper presents a low-cost production test strategy for digitally-calibrated analog-to-digital converters (ADCs) that incorporate an equalization-based background calibration scheme. The test time of these designs is dominated by the long calibration time required prior to conducting the final testing. To reduce overall test time, we present a two-step calibration approach that significantly reduces calibration time without compromising test coverage. In addition, by analyzing the data obtained in calibration, devices that fail certain static or dynamic specifications can be identified without incurring any additional test time beyond calibration, thereby enabling early rejection. To minimize calibration time and maximize failing symptoms for fault detection, we propose using specific calibration stimuli. Simulation results for a pipelined ADC shows that the proposed strategy reduces the total test time by 80%. This is achieved by reducing the calibration time, as well as by prescreening a good fraction of defective devices that fail static and dynamic specifications including the gain/offset errors and the effective number of bits (ENOB).
TL;DR: This paper presents a low-power and fully integrated frontend channel for long-wave infrared spectroscopic gas recognition that makes extensive use of transistor subthreshold operation and digital programmability.
Abstract: This paper presents a low-power and fully integrated frontend channel for long-wave infrared spectroscopic gas recognition. The proposed channel circuitry includes: input sensor biasing, sub-Hz high-pass filtering and pre-amplification, differential blind cancellation, and lock-in A/D conversion. The proposed CMOS circuits make extensive use of transistor subthreshold operation and digital programmability. Experimental results are presented for a 0.3 mm2 400 μW channel prototype integrated in 0.35 μm CMOS technology.
TL;DR: An analytical framework to express the energy-delay trade-off of CMOS buffers is presented, based on the Logical Effort methodology, and tapered-Vth buffers are shown to offer an up to 3× energy reduction under a given performance constraint.
Abstract: In this paper, “tapered-Vth” buffers are explored as an approach to significantly improve the energy efficiency of traditional CMOS buffers. In this approach, the transistor threshold voltage is progressively increased throughout the buffer stages, in addition to the traditional transistor tapered sizing. Analysis shows that tapered-Vth buffers are able to significantly widen the range of energy-delay trade-offs achievable in real designs, thereby showing improved design flexibility compared to single-Vth buffers. In addition, tapered-Vth buffers are shown to offer an up to 3t energy reduction under a given performance constraint. A circuit-level optimization procedure including the leakage energy contribution is adopted to explore the entire energy-delay space, in contrast to previous analyses that targeted only a specific point. To this aim, an analytical framework to express the energy-delay trade-off of CMOS buffers is presented, based on the Logical Effort methodology. Simulations in a 45-nm CMOS technology are extensively performed to validate the approach in a case study (Word Lines buffers for memory arrays) and in a number of other design cases. Extensive simulations are performed to understand the limits of the proposed approach, as well as the impact of the activity rate, the supply voltage, and process variations.