Showing papers in "IEEE Transactions on Circuits and Systems in 2012"

Consensus Analysis Based on Impulsive Systems in Multiagent Networks

Abstract: This paper discusses consensus problems for multiagent networks under directed communication graphs. The motions of agents are described by impulsive differential equations, and thus, consensus algorithms can be designed in terms of impulsive systems. Different from the standard consensus algorithms which rely on continuous-time or discrete-time models, the proposed algorithms based on impulsive systems take advantages of instantaneous information. It is shown that the proposed algorithms have a faster convergence speed than the standard consensus algorithms. Moreover, conditions under which all agents reach consensus with the desired performance are presented for the multiagent networks with external disturbances. Simulation results demonstrate the effectiveness of the proposed algorithms.

Hybrid Partitioned SRAM-Based Ternary Content Addressable Memory

Abstract: Although content addressable memory (CAM) provides fast search operation; however, CAM has disadvantages like low bit density and high cost per bit. This paper presents a novel memory architecture called hybrid partitioned static random access memory-based ternary content addressable memory (HP SRAM-based TCAM), which emulates TCAM functionality with conventional SRAM, thereby eliminating the inherited disadvantages of conventional TCAMs. HP SRAM-based TCAM logically dissects conventional TCAM table in a hybrid way (column-wise and row-wise) into TCAM sub-tables, which are then processed to be mapped to their corresponding SRAM memory units. Search operation in HP SRAM-based TCAM involves two SRAM accesses followed by a logical ANDing operation. To validate and justify our approach, 512 × 36 HP SRAM-based TCAM has been implemented in Xilinx Virtex-5 field programmable gate array (FPGA) and designed using 65-nm CMOS technology. Implementation in FPGA is advantageous and a beauty of our proposed TCAM because classical TCAMs cannot be implemented in FPGA. After a thorough analysis, we have concluded that energy/bit/search of the proposed TCAM is 85.72 fJ.

Implementing Wavelets in Continuous-Time Analog Circuits With Dynamic Range Optimization

Abstract: Signal processing by means of analog circuits offers advantages from a power consumption viewpoint. A method is described to implement wavelets in analog circuits by fitting the impulse response of a linear system to the time-reversed wavelet function. The fitting is performed using local search involving an L2 criterion, starting from a deterministic starting point. This approach offers a large performance increase over previous Pade-based approaches and allows for the circuit implementation of a larger range of wavelet functions. Subsequently, using state-space optimization the dynamic range of the circuit is optimized. Finally, to illustrate the design procedure, a sixth-order L2-approximated orthonormal Gaussian wavelet filter using Gm-C integrators is presented.

Direct All-Digital Frequency Synthesis Techniques, Spurs Suppression, and Deterministic Jitter Correction

Abstract: Direct all-digital frequency synthesizers are favored by modern nanoscale CMOS technologies but suffer from strong frequency spurs and timing irregularities. To counter these drawbacks various jitter-correction and spurs-suppression techniques have been proposed. This paper presents a comprehensive literature review and a comparative study of such techniques, applied to popular direct all-digital frequency synthesis cores, identifying their strengths and weaknesses.

An Empirical Phase-Noise Model for MEMS Oscillators Operating in Nonlinear Regime

Abstract: Nonlinearity of a silicon resonator can lead to improved phase-noise performance in an oscillator when the phase shift of the sustaining amplifier forces the operating point to a steeper phase-frequency slope. As a result, phase modulation on the oscillator frequency is minimized because the resonator behaves as a high-order phase filter. The effect of the increased filtering translates into phase-noise shaping that reflects superior overall performance. Nonlinear effects in MEMS oscillators can be induced via sufficient driving power, generating low-frequency nonwhite noise processes that need to be considered in a phase-noise description. Since the phase-frequency response is not symmetric for a nonlinear detuned resonator, an empirical model based on power series is proposed to describe its effect in the noise sources and to account for the observed higher effective quality factor of the oscillator, the reduction in the corner frequency, and elevated levels of flicker noise very close-to-carrier. The applicability of the presented phase-noise model is shown for three piezoelectric MEMS oscillators, producing a relative fitting error below 1% in all cases.

A 1-V 15-Bit Audio ΔΣ-ADC in 0.18 µm CMOS.

Abstract: In this paper a 1-V supply, 15-bit ΔΣ ADC design for audio applications is presented. The second order CIFB ΔΣ modulator with a 3-bit internal quantizer is adopted. The design of noise transfer function (NTF) is discussed from the viewpoint of mitigating the quantization noise mixture effect. A single-capacitor summing circuit is proposed which eliminates additional amplification or deliberate reference scaling. Nonideal effect due to parasitic capacitance is discussed. With proper modulator architecture, the design of building blocks is relaxed. Low gain amplifier with high power efficiency can be adopted which saves power. The decimator is implemented with cascade subfilters. Time multiplexing of arithmetic resources is employed for low hardware cost. Fabricated in 0.18 μm CMOS, the prototype ADC achieves 91.3 dB peak SNDR with 16 kHz. The modulator dissipates 190 μW and the decimator consumes 170 μW. The core area of the ADC is 0.5 mm2. The modulator occupies 0.3 mm2 and the decimator occupies 0.2 mm2.

An Autonomous Distributed Control Method for Link Failure Based on Tie-Set Graph Theory

Abstract: This study proposes an autonomous distributed control method for single link failure based on loops in a network. This method focuses on the concept of tie-sets defined by graph theory in order to divide a network into a string of logical loops. A tie-set denotes a set of links that constitutes a loop. Based on theoretical rationale of graph theory, a string of tie-sets that cover all the nodes and links can be created by using a tree, even in an intricately-intertwined mesh network. If tie-sets are used as local management units, high-speed and stable fail-over can be realized by taking full advantage of ring-based restoration. This paper first introduces the notion of tie-sets, and then describes the distributed algorithms for link failure. Experiments are conducted against Rapid Spanning Tree Protocol (RSTP), which is generally used for fault recovery in mesh topological networks. Experimental results comparing the proposed method with RSTP suggest that our method alleviates the adverse effects of link failure with a modest increase in state information of a node.