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Showing papers in "IEEE Transactions on Circuits and Systems in 2013"


Journal ArticleDOI
TL;DR: The proposed methodology uses recent advances in the theory of positive polynomials, semidefinite programming, and sum of squares decomposition to use an algebraic reformulation technique to recast the system's dynamics into a set of polynomial differential algebraic equations.
Abstract: We present a methodology for the algorithmic construction of Lyapunov functions for the transient stability analysis of classical power system models. The proposed methodology uses recent advances in the theory of positive polynomials, semidefinite programming, and sum of squares decomposition, which have been powerful tools for the analysis of systems with polynomial vector fields. In order to apply these techniques to power grid systems described by trigonometric nonlinearities we use an algebraic reformulation technique to recast the system's dynamics into a set of polynomial differential algebraic equations. We demonstrate the application of these techniques to the transient stability analysis of power systems by estimating the region of attraction of the stable operating point. An algorithm to compute the local stability Lyapunov function is described together with an optimization algorithm designed to improve this estimate.

141 citations


Journal Article
TL;DR: In this article, a 3 rd order single-loop continuous-time incremental sigma-delta analogue-to-digital con- verter (ADC) for time-multiplexed signals is proposed.
Abstract: This paper proposes a 3 rd order single-loop continuous-time incremental sigma-delta analogue-to-digital con- verter (ADC) for time-multiplexed signals. Incremental sigma- delta modulation is used to address medium to high resolution requirements of multi-channel applications, while a 3 rd order continuous-time implementation is investigated as an alternative for low-power solutions. A prototype of the proposed modulator, running at 320 kHz, has been fabricated in a 0.15-µm CMOS technology, while the synchronization circuitry to allow incre- mental operation was built on-board. Measurement results show that the ADC achieves 65.3 dB peak SNR, 64 dB peak SNDR and 68.2 dB dynamic range over a 2 kHz bandwidth. The modulator's power dissipation is 96 µW from a 1.6 V power supply. This translates into the best figure-of-merit when compared to recently published continuous-time alternatives, while being competitive with respect to state-of-the-art discrete-time counterparts. Index Terms—A/D conversion, incremental ADC, continuous-time.

55 citations



Journal ArticleDOI
TL;DR: Convergence properties of CLMs based on an augmented Lagrangian function in the context of equality constrained minimization, are studied and it is shown that, under some mild conditions, global asymptotical stability of the unique equilibrium point of the network can be guaranteed.
Abstract: Coupled local minimizers (CLMs) turn out to be a potential global optimization strategy to explore a search space, avoid overfitting and produce good generalization. In this paper, convergence properties of CLMs based on an augmented Lagrangian function in the context of equality constrained minimization, are studied. We first consider the augmented Lagrangian by taking the objective of minimizing the average cost of an ensemble of local minimizers subject to pairwise synchronization constraints. Then we study an array of CLMs within the Lagrange programming network framework and analyze the local stability of CLMs using a linearization strategy. We further show that, under some mild conditions, global asymptotical stability of the unique equilibrium point of the network can be guaranteed. Afterwards, some sufficient conditions are presented to ensure the stability of synchronization between any two minimizers via a directed graph method. The results show that the CLMs usually can be synchronized if the penalty factors in the array of CLMs are chosen large enough. It is worth pointing out that CLMs possess the capability of global exploration in the search space and the advantage of faster running time on convex problems in comparison with most of the neural network approaches, which is also illustrated through two test functions and their numerical simulations.

13 citations



Journal Article
TL;DR: A new digital-to-analog converter (DAC) is proposed for multi-bit continuous-time sigma-delta modulators and theoretical analysis supported by simulation results are provided to evaluate the performance, clock jitter immunity and robustness against DAC elements mismatch in the proposed modulators.
Abstract: In this paper, a new digital-to-analog converter (DAC) is proposed for multi-bit continuous-time sigma-delta modulators ( Ms). This -finite-impulse-response-DAC ( -FIR-DAC) digitally converts the multi-bit output of the quantizer to a 1.5-bit signal at a higher rate and then injects it to the modulator loop filter by using a 1.5-bit DAC. An FIR filter is merged into 1.5-bit DAC to improve the clock jitter insensitivity. Furthermore, a new implementation of FIR-DAC is presented to reduce the output rate of -FIR-DAC down to the original rate of the modulator. This reduced rate -FIR-DAC (RR-FIR-DAC) can be used in both continuous-time and discrete-time Ms. Theoretical analysis supported by simulation results are provided to evaluate the performance, clock jitter immunity and robustness against DAC elements mismatch in the proposed modulators.

7 citations


Journal Article
TL;DR: In this paper, a 4th order RF LC-based ΣΔ ADC clocked at 3.6 GHz and centered at 900 MHz is presented, which achieves a 52 dB SFDR and a 50 dB SNR in a 28 MHz BW and consumes only 15 mW.
Abstract: A 4th order RF LC-based ΣΔ ADC clocked at 3.6 GHz and centered at 900 MHz is presented. A simple design methodology is used to derive a robust architecture with a minimum number of feedback coefficients. The simplicity of the ADC architecture results in a significant performance enhancement and power consumption reduction. An efficient algorithm for the tuning and calibration of the ΣΔ LC-based loop filter is also presented. The ADC, suitable for cognitive Software Defined Radio applications, is implemented in a standard 130 nm CMOS technology. It achieves a 52 dB SFDR and a 50 dB SNR in a 28 MHz BW and consumes only 15 mW from a 1.2 V supply. The Figure of Merit of the ADC is 1.0 pJ/bit, which is to date the best reported FoM for an RF ADC. The effect of the clock jitter on the ADC performance is also measured and presented.

2 citations