Showing papers in "IEEE Transactions on Circuits and Systems in 2015"

Impedance-Based Local Stability Criterion for DC Distributed Power Systems

Abstract: This paper addresses the stability issue of dc distributed power systems (DPS). Impedance-based methods are effective for stability assessment of voltage-source systems and current-source systems. However, these methods may not be suitable for applications involving variation of practical parameters, loading conditions, system's structures, and operating modes. Thus, for systems that do not resemble simple voltage-source systems or current-source systems, stability assessment is much less readily performed. This paper proposes an impedance-based criterion for stability assessment of dc DPS. We first classify any converter in a dc DPS as either a bus voltage controlled converter (BVCC) or a bus current controlled converter (BCCC). As a result, a dc DPS can be represented in a general form regardless of its structure and operating mode. Then, the minor loop gain of the standard dc DPS is derived precisely using a two-port small signal model. Application of the Nyquist criterion on the derived minor loop gain gives the stability requirement for the dc DPS. This proposed criterion is applicable to dc DPSs, regardless of the control method and the connection configuration. Finally, a 480 W photovoltaic (PV) system with battery energy storage and a 200 W dc DPS, in which the source converter employs a droop control, are fabricated to validate the effectiveness of the proposed criterion.

A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection

Abstract: A fully-integrated low-dropout regulator (LDO) with fast transient response and full spectrum power supply rejection (PSR) is proposed to provide a clean supply for noise-sensitive building blocks in wideband communication systems. With the proposed point-of-load LDO, chip-level high-frequency glitches are well attenuated, consequently the system performance is improved. A tri-loop LDO architecture is proposed and verified in a 65 nm CMOS process. In comparison to other fully-integrated designs, the output pole is set to be the dominant pole, and the internal poles are pushed to higher frequencies with only 50 μA of total quiescent current. For a 1.2 V input voltage and 1 V output voltage, the measured undershoot and overshoot is only 43 mV and 82 mV, respectively, for load transient of 0 μA to 10 mA within edge times of 200 ps. It achieves a transient response time of 1.15 ns and the figure-of-merit (FOM) of 5.74 ps. PSR is measured to be better than -12 dB over the whole spectrum (DC to 20 GHz tested). The prototype chip measures 260×90 μm 2 , including 140 pF of stacked on-chip capacitors.

Nonlinear Dynamics of a Locally-Active Memristor

Abstract: This work elucidates some aspects of the nonlinear dynamics of a thermally-activated locally-active memristor based on a micro-structure consisting of a bi-layer of ${\rm Nb}_{2}{\rm O}_{5}$ and ${\rm Nb}_{2}{\rm O}_{x}$ materials. Through application of techniques from the theory of nonlinear dynamics to an accurate and simple mathematical model for the device, we gained a deep insight into the mechanisms at the origin of the emergence of local activity in the memristor. This theoretical study sets a general constraint on the biasing arrangement for the stabilization of the negative differential resistance effect in locally active memristors and provides a theoretical justification for an unexplained phenomenon observed at HP labs. As proof-of-principle, the constraint was used to enable a memristor to induce sustained oscillations in a one port cell. The capability of the oscillatory cell to amplify infinitesimal fluctuations of energy was theoretically and experimentally proved.

Consensus Control of a Class of Lipschitz Nonlinear Systems With Input Delay

Abstract: This paper deals with the consensus control design for Lipschitz nonlinear multi-agent systems with input delay. The Artstein-Kwon-Pearson reduction method is employed to deal with the input delay and the integral term that remains in the transformed system is analyzed by using Krasovskii functional. Upon exploring certain features of the Laplacian matrix, sufficient conditions for global stability of the consensus control are identified using Lyapunov method in the time domain. The proposed control only uses relative state information of the agents. The effectiveness of the proposed control design is demonstrated through a simulation study.

Analog Circuit Design Using Tunnel-FETs

Abstract: Tunnel-FET (TFET) is a major candidate for beyond-CMOS technologies. In this paper, the properties of the TFETs that affect analog circuit design are studied. To demonstrate how TFETs can enhance the performance or change the topology of the analog circuits, several building blocks such as operational transconductance amplifiers (OTAs), current mirrors, and track-and-hold circuits are examined. It is shown that TFETs are promising for low-power and low-voltage designs, wherein transistors are biased at low-to-moderate current densities. Comparing 14-nm III–V TFET-based OTAs with Si-MOSFET-based designs demonstrates up to 5 times reduction in the power dissipation of the amplifiers and more than an order of magnitude increase in their DC voltage gain. The challenges and opportunities that come with the special characteristics of TFETs, namely asymmetry, ambipolar behavior, negative differential resistance, and superlinear operation are discussed in detail.

Optimized Design of N-Phase Passive Mixer-First Receivers in Wideband Operation

Abstract: Recent developments in CMOS passive mixers have demonstrated a number of new and useful capabilities, including dynamic RF port impedance control and filter up-conversion, while also allowing low noise figure and high out-of-band linearity, all of which track wide-ranging LO frequencies and tunable baseband bandwidth. However, these circuits also bring a unique set of challenges and requirements. Here we extend a previously derived LTI model for such mixers to the general N-phase case, and discuss basic limits in performance specifications including impedance matching, noise figure and linearity. We then extend this analysis to include high-frequency effects, especially as they relate to transistor properties. We show that essentially all of the key specification of such mixers can be described in terms of an impedance ratio, a characteristic cut-off frequency, the number of phases of the mixer and some process-related parameters. Finally, we discuss how these properties relate to power consumption of LO circuitry.

Single/multi-band Wilkinson-type power dividers with embedded transversal filtering sections and application to channelized filters

Abstract: This paper addresses the exploitation of signal-interference concepts for the realization of single/multi-frequency Wilkinson-type filtering power dividers in planar/lumped-element technologies. By embedding transversal signal-interference filtering sections into the arms of conventional Wilkinson-type power-divider topologies, RF/microwave power-distribution actions with intrinsic mono/multi-band bandpass filtering capabilities can be obtained. Analytical equations and rules for the theoretical synthesis of this dual-function device are derived. The generalization of the approach to multi-stage schemes for enhanced-performance designs or for the shaping of frequency-asymmetrical responses is also discussed. Furthermore, for practical demonstration, three prototypes are developed and characterized. They are a microstrip quad-band circuit for the 1–5 GHz range, a dual-band lumped-element device for the band of 0.2–0.6 GHz, and a new type of two-branch channelized active bandpass filter at 3 GHz that makes use of single-band versions of this dual-behavior component as signal-division/combination blocks.

Balanced filters with wideband common mode suppression using dual-mode ring resonators

Abstract: Two novel balanced filters with wideband common mode suppression using dual-mode ring resonators are proposed in this paper. Two and four transmission zeros close to the passband are realized to improve the selectivity for the differential mode. In addition, over 20-dB common mode suppression can be realized from 0 GHz to $5f_{0}$ ( $f_{0}$ is the center frequency of the passband), due to the all-stop transmission characteristic of the open/shorted coupled lines. To verify the presented concepts, two prototypes ( $\varepsilon_{r}=2.65$ , $h=1.0\ {\rm mm}$ ) with 3-dB fractional bandwidths of 22.9% and 21.9% for the differential mode are designed and fabricated. The theoretical and measured results agree well and show good in-band filtering performance and high selectivity.

An Ultra-Low-Voltage CMOS Process-Insensitive Self-Biased OTA With Rail-to-Rail Input Range

Abstract: An operational-transconductance-amplifier (OTA) design for ultra-low voltage ultra-low power applications is proposed. The input stage of the proposed OTA utilizes a bulk-driven pseudo-differential pair to allow minimum supply voltage while achieving a rail-to-rail input range. All the transistors in the proposed OTA operate in the subthreshold region. Using a novel self-biasing technique to bias the OTA obviates the need for extra biasing circuitry and enhances the performance of the OTA. The proposed technique ensures the OTA robustness to process variations and increases design feasibility under ultra-low-voltage conditions. Moreover, the proposed biasing technique significantly improves the common-mode and power-supply rejection of the OTA. To further enhance the bandwidth and allow the use of smaller compensation capacitors, a compensation network based on a damping-factor control circuit is exploited. The OTA is fabricated in a 65 nm CMOS technology. Measurement results show that the OTA provides a low-frequency gain of 46 dB and rail-to-rail input common-mode range with a supply voltage as low as 0.5 V. The dc gain of the OTA is greater than 42 dB for supply voltage as low as 0.35 V. The power dissipation is 182 $\mu{\rm W}$ at $V_{DD}=0.5\ {\rm V}$ and 17 $\mu{\rm W}$ at $V_{DD}=0.35\ {\rm V}$ .

A 0.3 V 10-bit 1.17 f SAR ADC With Merge and Split Switching in 90 nm CMOS

Abstract: This paper presents a 10-bit ultra-low voltage energy-efficient SAR ADC. The proposed merge-and-split (MS) switching effectively reduces DAC switching energy by 83% compared with conventional one without the need of extra reference voltage $({\rm V}_{\rm cm})$ and the issue of common-mode voltage variation. To maintain good input linearity, a new double-bootstrapped sample-and-hold (S/H) circuit is proposed under an ultra-low voltage of 0.3 V. In addition, by employing asymmetric logic in SAR control, the leakage power is reduced with the penalty of slight conversion speed degradation. The test chip fabricated in 90 nm CMOS occupied a core area of 0.03 ${\rm mm}^{2}$ . With a single 0.3 V supply and a Nyquist rate input, the prototype consumes 35 nW at 90 kS/s and achieves an ENOB of 8.38 bit and a SFDR of 78.2 dB, respectively. The operation frequency is scalable up to 2 MS/s and power supply range from 0.3 V to 0.5 V. The resultant FOMs are 1.17-to-1.78 fJ/conv.-step.

An RF Energy Harvester With 44.1% PCE at Input Available Power of -12 dBm

Abstract: A 900-MHz radio-frequency energy harvester is designed and implemented for remotely powered devices. An efficient power path structure with adaptive control is proposed to maintain close-to-optimal power conversion efficiency. The control circuit consumes low power by adopting a novel open-loop asynchronous implementation and duty-cycled operation. A startup circuit is also presented. Measurement results show minimum input available power for startup of -17 dBm. With input available power of -12 dBm and load resistance of 144 kΩ, the measured output power is 27.8 μW, giving an output voltage of 2 V. This corresponds to an end-to-end power conversion efficiency of 44.1%. The harvester consumes quiescent current of 1.56 μA at output voltage of 2 V.

An Ultra-Low Voltage Level Shifter Using Revised Wilson Current Mirror for Fast and Energy-Efficient Wide-Range Voltage Conversion from Sub-Threshold to I/O Voltage

Abstract: This paper presents a novel ultra-low voltage level shifter for fast and energy-efficient wide-range voltage conversion from sub-threshold to I/O voltage. By addressing the voltage drop and non-optimal feedback control in a state-of-the-art level shifter based on Wilson current mirror, the proposed level shifter with revised Wilson current mirror significantly improves the delay and power consumption while achieving a wide voltage conversion range. It also employs mixed-Vt device and device sizing aware of inverse narrow width effect to further improve the delay and power consumption. Measurement results at 0.18 μm show that compared with the Wilson current mirror based level shifter, the proposed level shifter improves the delay, switching energy and leakage power by up to 3×, 19×, 29× respectively, when converting 0.3 V to a voltage between 0.6 V and 3.3 V. More specifically, it achieves 1.03 (or 1.15) FO4 delay, 39 (or 954) fJ/transition and 160 (or 970) pW leakage power, when converting 0.3 V to 1.8 V (or 3.3 V), which is better than several state-of-the-art level shifters for similar range voltage conversion. The measurement results also show that the proposed level shifter has good delay scalability with supply voltage scaling and low sensitivity to process and temperature variations.

A CMOS Current-Mode Magnetic Hall Sensor With Integrated Front-End

Abstract: A Hall magnetic sensor working in the current domain and its electronic interface are presented. The paper describes the physical sensor design and implementation in a standard CMOS technology, the transistor level design of its high sensitive front-end together with the sensor experimental characterization. The current-mode Hall sensor and the analog readout circuit have been fabricated using a 0.18- $\mu{\rm m}$ CMOS technology. The sensor uses the current spinning technique to compensate for the offset and provides a differential current as an output signal. The measured sensor power consumption and residual offset are 120 $\mu{\rm W}$ and 50 $\mu{\rm T}$ , respectively.

A 6-to-10-Bit 0.5 V-to-0.9 V Reconfigurable 2 MS/s Power Scalable SAR ADC in 0.18 CMOS

Abstract: An asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for sensor applications is presented. High linear and power efficient switching scheme is proposed. The proposed low leakage latched dynamic cell in SAR logic and wide range configurable delay element extend the flexibility of speed and resolution tradeoff. The ADC fabricated in 0.18 μm CMOS process covers 6-10 bit resolution and 0.5 V-0.9 V power supply range. At 10 bit mode and 0.5 V operation, the proposed SAR ADC achieves 56.36 dB SNDR and 67.96 dB SFDR with sampling rate up to 2 MS/s, corresponding to a figure-of-merit of 20.6 fJ/conversion-step. The proposed ADC core occupies an active area of about 300×700 μm 2 .

Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement

Abstract: This paper presents a 9T multi-threshold (MTCMOS) SRAM macro with equalized bitline leakage and a content-addressable-memory-assisted (CAM-assisted) write performance boosting technique for energy efficiency improvement. A 3T-based read port is proposed to equalize read bitline (RBL) leakage and to improve RBL sensing margin by eliminating data-dependence on bitline leakage current. A miniature CAM-assisted circuit is integrated to conceal the slow data development with HVT devices after data flipping in write operation and therefore enhance the write performance for energy efficiency. A 16 kb SRAM test chip is fabricated in 65 nm CMOS technology. The operating voltage of the test chip is scalable from 1.2 V down to 0.26 V with the read access time from 6 ns to 0.85 $\mu {\rm s}$ . Minimum energy of 2.07 pJ is achieved at 0.4 V with 40.3% improvement compared to the SRAM without the aid of the CAM. Energy efficiency is enhanced by 29.4% between 0.38 V $\sim$ 0.6 V by the proposed CAM-assisted circuit.

A Power-Efficient Continuous-Time Incremental Sigma-Delta ADC for Neural Recording Systems

Abstract: This paper presents an analog-to-digital converter (ADC) dedicated to neural recording systems. By using two continuous-time incremental sigma-delta ADCs in a pipeline configuration, the proposed ADC can achieve high-resolution without sacrificing the conversion rate. This two-step architecture is also power-efficient, as the resolution requirement for the incremental sigma-delta ADC in each step is significantly relaxed. To further enhance the power efficiency, a class-AB output stage and a dynamic summing comparator are used to implement the sigma-delta modulators. A prototype chip, designed and fabricated in a standard 0.18 $\mu{\rm m}$ CMOS process, validates the proposed ADC architecture. Measurement results show that the ADC achieves a peak signal-to-noise-plus-distortion ratio of 75.9 dB over a 4 kHz bandwidth; the power consumption is 34.8 $\mu{\rm W}$ , which corresponds to a figure-of-merit of 0.85 pJ/conv.

Synchronization in On-Off Stochastic Networks: Windows of Opportunity

Abstract: We study dynamical networks whose topology and intrinsic parameters stochastically change, on a time scale that ranges from fast to slow. When switching is fast, the stochastic network synchronizes as long as synchronization in the averaged network, obtained by replacing the random variables by their mean, becomes stable. We apply a recently developed general theory of blinking systems to prove global stability of synchronization in the fast switching limit. We use a network of Lorenz systems to derive explicit probabilistic bounds on the switching frequency sufficient for the network to synchronize almost surely and globally. Going beyond fast switching, we consider networks of Rossler and Duffing oscillators and reveal unexpected windows of intermediate switching frequencies in which synchronization in the switching network becomes stable even though it is unstable in the averaged/fast-switching network.

CMOS Image Sensor Based Physical Unclonable Function for Coherent Sensor-Level Authentication

Abstract: In the applications of biometric authentication and video surveillance, the image sensor is expected to provide certain degree of trust and resiliency. This paper presents a new low-cost CMOS image sensor based physical unclonable function (PUF) targeting a variety of security, privacy and trusted protocols that involves image sensor as a trusted entity. The proposed PUF exploits the intrinsic imperfection during the image sensor manufacturing process to generate unique and reliable digital signatures. The proposed differential readout stabilizes the response bits extracted from the random fixed pattern noises of selected pixel pairs determined by the applied challenge against supply voltage and temperature variations. The threshold of difference can be tightened to winnow out more unstable response bits from the challenge-response space offered by modern image sensors to enhance the reliability under harsher operating conditions and loosened to improve its resiliency against masquerade attacks in routine operating environment. The proposed design can be classified as a weak PUF which is resilient to modeling attacks, with direct access to its challenge-response pair restricted by the linear feedback shift register. Our experiments on the reset voltages extracted from a 64 $\times$ 64 image sensor fabricated in 180 nm 3.3 V CMOS technology demonstrated that robust and reliable challenge-response pairs can be generated with a uniqueness of 49.37% and a reliability of 99.80% under temperature variations of $15\sim 115~^{\circ}{\rm C}$ and supply voltage variations of $3\sim 3.6\ {\rm V}$ .

Theory and Design of a Quadrature Analog-to-Information Converter for Energy-Efficient Wideband Spectrum Sensing

Abstract: A flexible bandwidth, blind sub-Nyquist sampling approach referred to as the quadrature analog-to-information converter (QAIC) is proposed. The QAIC relaxes the analog frontend bandwidth requirements at the cost of some added complexity compared to the modulated wideband converter (MWC) for an overall improvement in sensitivity and energy consumption. An approach for detailed frequency domain analysis of the proposed system with linear impairments is developed. A process for selecting QAIC parameter values is illustrated through examples. The benefits of the QAIC are highlighted with cognitive radio use cases where a wide range of spectrum is observed at various resolution bandwidth settings. We demonstrate that the energy consumption of the QAIC is potentially two orders of magnitude lower than the swept-tuned spectrum analyzer (STSA) and an order of magnitude lower than the MWC. We also demonstrate that the QAIC significantly improves upon the sensitivity performance delivered by the MWC.

Design Methodology of Subthreshold Three-Stage CMOS OTAs Suitable for Ultra-Low-Power Low-Area and High Driving Capability

Abstract: A design methodology for three-stage CMOS OTAs operating in the subthreshold region is presented The procedure is focused on the development of ultra-low-power amplifiers requiring low silicon area but being able to drive high capacitive loads Indeed, by following the presented methodology we designed a CMOS OTA in a 035- $\mu{\rm m}$ technology that occupies only $44\cdot 10^{-3}\ {\rm mm}^{2}$ , is powered with a 1-V supply, exhibits 120-dB DC gain and is able to drive a capacitive load up to 200 pF Thanks to proposed methodology, the OTA is able to provide a 20-kHz unity gain bandwidth while consuming 195 nW, even under the high load considered Moreover, the slew rate enhancer circuit in addition to the class AB output stage allows an average slew rate higher than 5 ${\rm mV}/\mu{\rm s}$ with the 200 pF load Comparison with prior art shows an improvement factor in the figures of merit higher than 5

A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT

Abstract: Approximation of discrete cosine transform (DCT) is useful for reducing its computational complexity without significant impact on its coding performance. Most of the existing algorithms for approximation of the DCT target only the DCT of small transform lengths, and some of them are non-orthogonal. This paper presents a generalized recursive algorithm to obtain orthogonal approximation of DCT where an approximate DCT of length $N$ could be derived from a pair of DCTs of length $(N/2)$ at the cost of $N$ additions for input preprocessing. We perform recursive sparse matrix decomposition and make use of the symmetries of DCT basis vectors for deriving the proposed approximation algorithm. Proposed algorithm is highly scalable for hardware as well as software implementation of DCT of higher lengths, and it can make use of the existing approximation of 8-point DCT to obtain approximate DCT of any power of two length, $N>8$ . We demonstrate that the proposed approximation of DCT provides comparable or better image and video compression performance than the existing approximation methods. It is shown that proposed algorithm involves lower arithmetic complexity compared with the other existing approximation algorithms. We have presented a fully scalable reconfigurable parallel architecture for the computation of approximate DCT based on the proposed algorithm. One uniquely interesting feature of the proposed design is that it could be configured for the computation of a 32-point DCT or for parallel computation of two 16-point DCTs or four 8-point DCTs with a marginal control overhead. The proposed architecture is found to offer many advantages in terms of hardware complexity, regularity and modularity. Experimental results obtained from FPGA implementation show the advantage of the proposed method.

High-Performance Four-Stage CMOS OTA Suitable for Large Capacitive Loads

Abstract: Designing four-stage operational transconductance amplifiers (OTAs) is often considered a challenging task mainly because of the required non trivial frequency compensation procedure In this study, starting from the simplest architecture (a differential stage cascaded by three common source stages) a high-performance OTA is demonstrated, outperforming all the (few) previous implementations Thanks to the frequency compensation scheme and to the adoption of a slew-rate enhancer section, the solution is able to drive large capacitive loads as high as 1 nF, rivaling in terms of bandwidth and speed even with three-stage counterparts, traditionally credited to be better because of the less number of high-impedance nodes The solution, fabricated in a 035- $\mu{\rm m}$ technology, occupies 0014- ${\rm mm}^{2}$ with DC consumption of 170 $\mu{\rm W}$ It also achieves nearly 3-MHz gain bandwidth product while driving the 1-nF load with less than 05- $\mu{\rm s}$ 1% settling time

Digital Multiplierless Realization of Two Coupled Biological Morris-Lecar Neuron Model

Abstract: Modeling and implementation of biological neural networks are significant objectives of the neuromorphic research field In this field, neuronal synchronization plays a significant role in the processing of biological information This paper presents a set of piecewise linear (MLPWL1) and multiplierless piecewise linear (MLPWL2) neuron models, which mimic behaviors of different types of neurons, similar to the biological behavior of conductance-based neurons Both simulations and a low-cost digital implementation are carried out to compare the proposed models to a single ML neuron and two coupled ML neurons, demonstrating the required range of dynamics with a more efficient implementation Hardware implementations on a field-programmable gate array (FPGA) show that the modified models mimic the biological behavior of different types of neurons with higher performance and significantly lower implementation costs compared to the previous realizations of the ML model The mean normalized root mean square errors (NRMSEs) of the MLPWL1 and MLPWL2 models are 370% and 489%, respectively, as compared to the original ML model

DPA-Secured Quasi-Adiabatic Logic (SQAL) for Low-Power Passive RFID Tags Employing S-Boxes

Abstract: Low-power mobile devices such as RFID tags and WSNs that employ AES cryptographic modules are susceptible to differential power analysis (DPA) attacks. This paper presents a novel secured quasi-adiabatic logic (SQAL) technology that is both low-power and DPA immune. The efficiency of the SQAL technology was evaluated on an 8-bit AES-128 SBOX block and proved to be robust against DPA attacks. Compared to other adiabatic and non-adiabatic logic styles, the SQAL technology achieves better results in terms of power consumption and area overhead.

Modeling and Simulation of Vanadium Dioxide Relaxation Oscillators

Abstract: This paper deals with modeling and simulation of a new family of two-terminal devices fabricated with vanadium dioxide material. Such devices allow realization of very compact relaxation nano-oscillators that can be connected electronically to form arrays of coupled oscillators. Challenging applications of oscillator arrays include the realization of multiphase signal generators and massively parallel brain-inspired neurocomputing. In the paper, a circuit-level model of the vanadium dioxide device is provided which enables extensive electrical simulations of oscillator systems built on the device. The proposed model is exploited to explain the dynamics of vanadium dioxide relaxation oscillators as well as to accomplish a robust parameter design. Applications to the realization of voltage-controlled oscillators and of multiphase oscillator arrays are illustrated.

A Closed-Loop Reconfigurable Switched-Capacitor DC-DC Converter for Sub-mW Energy Harvesting Applications

Abstract: Energy harvesting is an emerging technology for powering wireless sensor nodes, enabling battery-free operation of these devices. In an energy harvesting sensor, a power management circuit is required to regulate the variable harvested voltage to provide a constant supply rail for the sensor circuits. The power management circuit needs to be compact, efficient, and robust to the variations of the input voltage and load current. A closed-form power expression and custom control algorithm for regulation of a switched-capacitor DC-DC converter with optimal conversion efficiency are proposed in this paper. The proposed regulation algorithm automatically adjusts both the voltage gain and switching frequency of a switched-capacitor DC-DC converter based on its input voltage and load current, increasing the power efficiency across a wide input voltage range. The design and simulation of a fully integrated circuit based on the proposed power managing approach is presented. This power management circuit has been simulated in a 0.25 $\mu{\rm m}$ standard CMOS process and simulation results confirm that with an input voltage ranging from 0.5 V to 2.5 V, the converter can generate a regulated 1.2 V output rail and deliver a maximum load current of 100 $\mu{\rm A}$ . The power conversion efficiency is higher than 74% across a wide range of the input voltage with a maximum efficiency of 83%.

On the Phase Noise Performance of Transformer-Based CMOS Differential-Pair Harmonic Oscillators

Abstract: The white noise to phase noise conversion of one- and two-port CMOS differential-pair harmonic oscillators with transformer-based resonators is addressed in this paper. First, the operation of double-tuned transformer resonators is reviewed and design guidelines are proposed to maximize the quality factor. A rigorous approach is then employed to approximate the transformer network with a second order RLC model near the resonances, greatly simplifying the problem of handling the complex equations of a higher order resonator. The results are applied to phase noise calculations, leading to simple, yet accurate, closed-form $1/f^{2}$ phase noise expressions in excellent agreement with the simulation results. It is formally proved, in a general case, that high-order resonators do not provide any fundamental advantage in comparison with simple LC-tanks. The two-port transformer based oscillator may be exploited to limit the phase noise contribution of the core transistors through optimization of the bias point and by leveraging the transformer voltage gain.

An 18.7-Gb/s 60-GHz OOK Demodulator in 65-nm CMOS for Wireless Network-on-Chip

Abstract: This paper presents a high-efficiency 60-GHz on-off keying (OOK) demodulator for high-speed short-range wireless communications such as wireless network-on-chip (WiNoC) applications Targeting at data rates of beyond 16 Gb/s, the OOK demodulator consists of a wideband envelope detector (ED) and a single-stage baseband (BB) peaking amplifier Novel dual gain-boosting techniques improve the gain, bandwidth, and out-of-band rejection of the ED In addition, an actively-enhanced tunable inductor (AETI) load in the BB amplifier not only significantly reduces its area overhead, but also provides a tunable peaking level Fabricated in a 65-nm bulk CMOS process, the OOK demodulator consumes only 46 mW from a 1-V supply, and occupies an active area of 0043 mm 2 A maximum data rate of 187 Gb/s with a bit-error rate less than 10 -12 is demonstrated through measurements, which translates to a bit-energy efficiency of 025 pJ/bit