Showing papers in "IEEE Transactions on Circuits and Systems in 2016"
TL;DR: The manuscript introduces a comprehensive analysis method of memristor circuits in the flux-charge (φ, q)-domain that relies on Kirchhoff Flux and Charge Laws and constitutive relations of circuit elements in terms of incremental flux and charge.
Abstract: Memristor-based circuits are widely exploited to realize analog and/or digital systems for a broad scope of applications (e.g., amplifiers, filters, oscillators, logic gates, and memristor as synapses). A systematic methodology is necessary to understand complex nonlinear phenomena emerging in memristor circuits. The manuscript introduces a comprehensive analysis method of memristor circuits in the flux-charge $(\varphi,q)$ -domain. The proposed method relies on Kirchhoff Flux and Charge Laws and constitutive relations of circuit elements in terms of incremental flux and charge. The main advantages (over the approaches in the voltage-current $(v,i)$ -domain) of the formulation of circuit equations in the $(\varphi,q)$ -domain are: a) a simplified analysis of nonlinear dynamics and bifurcations by means of a smaller set of ODEs; b) a clear understanding of the influence of initial conditions. The straightforward application of the proposed method provides a full portrait of the nonlinear dynamics of the simplest memristor circuit made of one memristor connected to a capacitor. In addition, the concept of invariant manifolds permits to clarify how initial conditions give rise to bifurcations without parameters.
112 citations
TL;DR: A speed-up technique for successive-cancellation list decoding of polar codes that is exact for list size of 2, while its approximations bring negligible error-correction performance degradation (<;0.05 dB) for other list sizes.
Abstract: Polar codes are a recently discovered family of capacity-achieving error-correcting codes. Among the proposed decoding algorithms, successive-cancellation list decoding guarantees the best error-correction performance with codes of moderate lengths, but it yields low throughput. Speed-up techniques have been proposed in the past: most of them rely on approximations that degrade the error-correction capability of the algorithm. We propose a speed-up technique for successive-cancellation list decoding of polar codes that is exact for list size of 2, while its approximations bring negligible error-correction performance degradation ( $3.16\times $ , at the cost of 14.2% in area occupation.
110 citations
TL;DR: Broadband capability of a Class-E mode with shunt filter using reactance compensation technique has been demonstrated by two examples, one with lumped elements and the other with transmission-line elements.
Abstract: An analysis of a novel single-ended Class-E mode with shunt capacitance and shunt filter with explicit derivation of the idealized optimum voltage and current waveforms and load-network parameters with their verification by frequency domain simulations with 50% duty ratio is presented. The ideal collector voltage and current waveforms demonstrate a possibility of 100% efficiency. The circuit design with transmission lines at 2.14 GHz is discussed and analyzed. In order to reduce the voltage peak factor, the load network parameters can be rearranged to correspond to Class-E/F 3 mode by providing a short-circuit condition at the third harmonic when the second-harmonic tank is connected in series to the shunt filter. Broadband capability of a Class-E mode with shunt filter using reactance compensation technique has been demonstrated by two examples, one with lumped elements and the other with transmission-line elements. The test board of a transmission-line broadband Class-E GaN HEMT power amplifier with shunt filter was measured and high-performance results with the output power of around 41 dBm, average drain efficiency of 68%, and power gain of about 9 dB were achieved across the frequency band from 1.4 to 2.7 GHz.
109 citations
TL;DR: A tunable fractional order parallel resonator (FOPR) whose resonating frequency can be tuned by the coefficient of a fractionalOrder (FO) element (fractor) whose Q-factor can be set very high (theoretically infinite) by varying its resistor.
Abstract: This paper introduces a tunable fractional order parallel resonator (FOPR) whose resonating frequency can be tuned by the coefficient of a fractional order (FO) element (fractor). At the same time, its $Q$ - factor can be set very high (theoretically infinite) by varying its resistor. Using this FOPR circuit, two simple FO filters (FO bandpass and FO notch) are also developed. The paper includes detail sensitivity analyses of these circuits for various circuit parameters and describes how different design parameters of proposed FOPR and FO filters are chosen accordingly. Proposed FOPR and FO filters are simulated in MATLAB and realized in hardware. The hardware circuits are tested practically, and detail experimental results are provided. It is found that the experimental data are in good agreement with the simulation data. In hardware, the realized FOPR has achieved a $Q$ -factor up to 360, and the realized FO notch filter has ${Q}>10$ when its attenuation is more than 30 dB. Different practical aspects of filter tuning are also described in detail.
107 citations
TL;DR: The problem of existence and stability of equilibria of linear systems with constant power loads is addressed and it is proved that the latter condition is also sufficient if a set defined by the problem data is convex, which is the case for single and two-port systems.
Abstract: The problem of existence and stability of equilibria of linear systems with constant power loads is addressed in this paper. First, we correct an unfortunate mistake in our recent paper pertaining to the sufficiency of the condition for existence of equilibria in multiport systems given there. Second, we give two necessary conditions for existence of equilibria. The first one is a simple linear matrix inequality hence it can be easily verified with existing software. Third, we prove that the latter condition is also sufficient if a set defined by the problem data is convex, which is the case for single and two-port systems. Finally, sufficient conditions for stability and instability for a given equilibrium point are given. The results are illustrated with two benchmark examples.
101 citations
TL;DR: Overall good large-Signal and small-signal performances are achieved, making the solution extremely competitive in comparison to the state of the art.
Abstract: A simple high-performance architecture for bulk-driven operational transconductance amplifiers (OTAs) is presented. The solution, suitable for operation under sub 1-V single supply, is made up of three gain stages and, as an additional feature, provides inherent class-AB behavior with accurate and robust standby current control. The OTA is fabricated in a 180-nm standard CMOS technology, occupies an area of $19.8\cdot 10^{-3}\ \text{mm}^{2}$ and is powered from 0.7 V with a standby current consumption of around 36 $\mu\text{A}$ . DC gain and unity gain frequency are 57 dB and 3 MHz, respectively, under a capacitive load of 20 pF. Overall good large-signal and small-signal performances are achieved, making the solution extremely competitive in comparison to the state of the art.
100 citations
TL;DR: An improved comparator with push-pull pre-amplifier and output offset storage (OOS) strategy is proposed to diminish non-linearity in the input parasitic capacitance to reduce the power consumption and the matching requirement for capacitors in SAR ADCs.
Abstract: A 12-bit 10 MS/s SAR ADC with enhanced linearity and energy efficiency is presented in this paper. A novel switching scheme (COSS) is proposed to reduce the power consumption and the matching requirement for capacitors in SAR ADCs. The switching energy (including switching energy and reset energy), total capacitance and static performance (INL & DNL) of the proposed scheme are reduced by 98.08%, 75%, and 75%, respectively, compared with the conventional architecture. Based on analysis of the non-linear errors caused by comparator input parasitic capacitance, an improved comparator with push-pull pre-amplifier and output offset storage (OOS) strategy is proposed to diminish non-linearity in the input parasitic capacitance. The offset cancellation signal for the comparator can be generated by asynchronous timing automatically, without any extra clock. Additionally, an SFDR enhancement bootstrap switch is proposed to eliminate the distortion induced by parasitic capacitance and threshold voltage that results in insufficient precision for medium-speed 12-bit ADCs. The proposed ADC was fabricated in a 0.18 $\mu\text{m}$ 1P6M CMOS process, and the measured results show that the ADC achieves an SNDR of 66.9 dB and an SFDR of 75.8 dB with a 10 MS/s sampling rate and consumes 0.82 mW, resulting in a figure of merit (FOM) of 44.2 fJ/conversion-step. The peak DNL error is +0.36/−0.33 LSB, and the peak INL error is +0.55 LSB/−0.6 LSB. The ADC core occupies an active area of only $630\ \mu\text{m}\! \times\! 570\ \mu\text{m}^{2}$ .
94 citations
TL;DR: This paper applies an idea of coupling multiple oscillators to reduce phase noise (PN) to beyond the limit of what has been practically achievable so far in a bulk CMOS technology to demonstrate for the first time an RF oscillator that meets the most stringent PN requirements of cellular basestation receivers while abiding by the process technology reliability rules.
Abstract: In this paper, we exploit an idea of coupling multiple oscillators to reduce phase noise (PN) to beyond the limit of what has been practically achievable so far in a bulk CMOS technology. We then apply it to demonstrate for the first time an RF oscillator that meets the most stringent PN requirements of cellular basestation receivers while abiding by the process technology reliability rules. The oscillator is realized in digital 65-nm CMOS as a dual-core LC-tank oscillator based on a high-swing class-C topology. It is tunable within 4.07–4.91 GHz, while drawing 39–59 mA from a 2.15 V power supply. The measured PN is $-$ 146.7 dBc/Hz and $-$ 163.1 dBc/Hz at 3 MHz and 20 MHz offset, respectively, from a 4.07 GHz carrier, which makes it the lowest reported normalized PN of an integrated CMOS oscillator. Straightforward expressions for PN and interconnect resistance between the cores are derived and verified against circuit simulations and measurements. Analysis and simulations show that the interconnect resistance is not critical even with a 1% mismatch between the cores. This approach can be extended to a higher number of cores and achieve an arbitrary reduction in PN at the cost of the power and area.
90 citations
TL;DR: The Holomorphic Embedding Loadflow Method is shown to extend naturally to DC power transmission systems, preserving all the constructive and deterministic properties that allow it to obtain the white branch solution in an unequivocal way.
Abstract: The Holomorphic Embedding Loadflow Method is extended here from AC to DC-based systems. Through an appropriate embedding technique, the method is shown to extend naturally to DC power transmission systems, preserving all the constructive and deterministic properties that allow it to obtain the white branch solution in an unequivocal way. Its applications extend to nascent meshed HVDC networks and also to power distribution systems in more-electric vehicles, ships, aircraft, and spacecraft. In these latter areas, it is shown how the method can cleanly accommodate the higher-order nonlinearities that characterize the I-V curves of many devices. The case of a photovoltaic array feeding a constant-power load is given as an example. The extension to the general problem of finding DC operating points in electronics is also discussed, and exemplified on the diode model.
87 citations
TL;DR: A high-throughput energy-efficient Successive Cancellation decoder architecture for polar codes based on combinational logic that combines the advantageous aspects of the combinational decoder with the low-complexity nature of sequential-logic decoders is proposed.
Abstract: This paper proposes a high-throughput energy-efficient Successive Cancellation (SC) decoder architecture for polar codes based on combinational logic. The proposed combinational architecture operates at relatively low clock frequencies compared to sequential circuits, but takes advantage of the high degree of parallelism inherent in such architectures to provide a favorable tradeoff between throughput and energy efficiency at short to medium block lengths. At longer block lengths, the paper proposes a hybrid-logic SC decoder that combines the advantageous aspects of the combinational decoder with the low-complexity nature of sequential-logic decoders. Performance characteristics on ASIC and FPGA are presented with a detailed power consumption analysis for combinational decoders. Finally, the paper presents an analysis of the complexity and delay of combinational decoders, and of the throughput gains obtained by hybrid-logic decoders with respect to purely synchronous architectures.
85 citations
TL;DR: The designed neural network can well perform the Pavlov associative memory in the network with at least three interconnected neurons and can also perform two kinds of forgetting activities after the learning process is completed.
Abstract: In this paper, implementation of memristive neural network with full-function Pavlov associative memory is designed based on a proposed associative memory rule. The designed neural network can well perform the Pavlov associative memory in the network with at least three interconnected neurons. This neural network and the associative memory rule that is partly based on spike-rate-dependent plasticity (SRDP) protocol are inspired by the famous Pavlov’s dog-experiment that demonstrated the interrelation between the “sight of food” and the “ringing.” Besides the learning activity, the proposed network can also perform two kinds of forgetting activities after the learning process is completed: on one hand, when the salivation neuron is stimulated by the food neuron alone, after a period of time, the ring neuron can no longer trigger the salivation neuron; on the other hand, when the salivation neuron is stimulated by the ring neuron alone, at first the salivation neuron can be triggered but after the salivation neuron realizes that the “ringing” is not associated with “food,” the salivation neuron will not be triggered any longer. How to integrate the proposed network into large scale memristive neural network with multiple associations is also introduced. Simulations results demonstrate the correctness of the designs.
TL;DR: Both theoretical analysis and simulation results confirm the promising benefits of the new DCSK modulation scheme, which employs I/Q channels to send these two signals in a parallel and simultaneous manner, making the system easily extendable to multi-carriers.
Abstract: A novel non-coherent multi-level differential chaos shift keying (DCSK) modulation scheme is proposed in this paper. This new scheme is based on both the transmitted-reference technique and $M$ -ary orthogonal modulation, where each data-bearing signal is chosen from a set of orthogonal chaotic wavelets constructed by a reference signal. Thanks to this signaling design, the new scheme can achieve a higher attainable data rate, lower energy loss in reference transmission, increased bandwidth efficiency, better data security and better bit error rate (BER) performance as compared to the conventional DCSK. Unlike other DCSK-based systems that separate the reference and data-bearing signals using the TDMA scheme, this new system employs I/Q channels to send these two signals in a parallel and simultaneous manner, making the system easily extendable to multi-carriers. This transmission mechanism not only can further increase data rate but also can remove all radio frequency delay lines from detectors. Analytical BER expressions of the proposed system are derived for both additive white Gaussian noise (AWGN) and multipath Rayleigh fading channels. Relevant simulation results are given and compared to non-coherent binary/ $M$ -ary DCSK systems. In addition, the impacts of various system parameters on noise performance are discussed. Both theoretical analysis and simulation results confirm the promising benefits of the new design.
TL;DR: This paper presents a novel capacitor-less low-dropout regulator (LDO) for mobile applications that utilizes multiple feedback loops to satisfy several design challenges for some mobile applications which were not considered in the previous capacitor- less LDOs.
Abstract: This paper presents a novel capacitor-less low-dropout regulator (LDO) for mobile applications. The proposed capacitor-less LDO utilizes multiple feedback loops to satisfy several design challenges for some mobile applications which were not considered in the previous capacitor-less LDOs. The proposed LDO has a wide bandwidth of 3.03 MHz at a load current of 150 mA with a bias current of 40 $\mu\mbox{A}$ , and the best line and load regulations of 0.0024%/V and 0.0000417%/mA, respectively, which are improvements over previously reported LDOs. This chip has a 100 mV dropout voltage with a 150 mA maximum load current. A total capacitance of 29 pF was used with a chip size of 0.279 $\mbox{mm}^{2}$ .
TL;DR: The loop-gain function of an integrated 3-level buck converter with parasitic capacitors and time mismatch is derived with the state-space averaging method, and the derived loop- gain functions are verified with time-domain small signal injection simulation and measurement.
Abstract: This paper presents a systematic analysis of integrated 3-level buck converters under both ideal and real conditions as a guidance for designing robust and fast 3-level buck converters Under ideal conditions, the voltage conversion ratio, the output voltage ripple and, in particular, the system's loop-gain function are derived Design considerations for real circuitry implementations of an integrated 3-level converter, such as the implementation of the flying capacitor, the impacts of the parasitic capacitors of the flying capacitor and the 4 power switches, and the time mismatch between the 2 duty-cycle signals are thoroughly discussed Under these conditions, the voltage conversion ratio, the voltage across the flying capacitor and the power efficiency are analyzed and verified with Cadence simulation results The loop-gain function of an integrated 3-level buck converter with parasitic capacitors and time mismatch is derived with the state-space averaging method The derived loop-gain functions are verified with time-domain small signal injection simulation and measurement, with a good match between the analytical and experimental results
TL;DR: A new Doherty amplifier configuration with attractive behaviors including bandpass filtering, wideband harmonic suppression, and enhanced efficiency, is presented, a component crucial to the successful implementation of the proposed configuration is the bandpass quadrature coupler with arbitrary coupling coefficient.
Abstract: There is an ever increasing demand for both function integration and improved performance in wireless communication devices. Therefore, the integration of efficient linearizing amplifying and bandpass filtering functions is proposed for the first time in this paper. A new Doherty amplifier configuration with attractive behaviors including bandpass filtering, wideband harmonic suppression, and enhanced efficiency, is presented. A component crucial to the successful implementation of the proposed configuration is the bandpass quadrature coupler with arbitrary coupling coefficient. Owing to the flexibility of a circular patch in locating the frequencies of different operational modes, it is thus possible to implement good bandpass characteristics. With the introduction of this new component, the Main and Auxiliary amplifiers can be driven more efficiently, resulting in both linearity and efficiency improvements. To verify the validity of the proposed configuration, a Doherty amplifier has been designed and fabricated. Its measured performance is compared with the conventional design and found to exhibit a bandpass filtering characteristics with a wide suppression band up to the third harmonic frequency. Meanwhile, the proposed amplifier achieves a measured power-added-efficiency improvement of 10% and an ACLR improvement better than 5.8 dB at the higher output power region.
TL;DR: This paper presents a new family of Class-AB operational transconductance amplifier (OTA) circuits based on single-stage topologies with non-linear current amplifiers that are well-suited for low-power switched-capacitor circuits and specifically optimized for switched-OpAmp fast on-off operation and multi-decade load-Capacitance specifications.
Abstract: This paper presents a new family of Class-AB operational transconductance amplifier (OTA) circuits based on single-stage topologies with non-linear current amplifiers. The proposed variable-mirror amplifier (VMA) architecture is mainly characterized by generating all Class-AB current in the output transistors only, by exhibiting very low sensitivity to both technology and temperature deviations, and by avoiding the need for any internal frequency-compensation mechanism. Hence, this family of OTAs is well-suited for low-power switched-capacitor circuits and specifically optimized for switched-OpAmp fast on-off operation and multi-decade load-capacitance specifications. Analytical expressions valid in all regions of operation are presented to minimize VMA settling time in discrete-time circuits. Also, a complete OTA design example integrated in 0.18 $\mu\text{m}$ 1P6M MiM 1.8 V CMOS technology is supplied with detailed simulation and experimental results. Compared to resistor-free state-of-art Class-AB OpAmp and OTA literature, the proposed architecture returns the highest measured figure-of-merit value.
TL;DR: The proposed circuits feature a lower voltage stress on its semiconductors (both switch and diodes) than that on the equivalent devices of a boost stage and are therefore non-isolated power electronics circuits with a very high dc gain.
Abstract: A simple graph with four nodes and eleven branches is defined. Its branches are filled in different ways with passive elements (capacitors, inductors, diodes) or replaced by shortcircuits in order to get potential voltage step-up switching cells. These cells are inserted in boost converter, obtaining thus non-isolated power electronics circuits with a very high dc gain. Such circuits are necessary today in the green energy systems. The proposed circuits feature a lower voltage stress on its semiconductors (both switch and diodes) than that on the equivalent devices of a boost stage. A state-space-based dc and ac analysis allows for deriving the dc gain, the switches voltage and current stresses, and the frequency characteristics of the obtained converters. The steady-state analysis is performed for both the continuous and discontinuous conduction mode operations. The converters belonging to the new family are compared between them and then compared with available solutions of similar complexity as defined by the component count. Simulation and experimental results confirm the theoretical equations.
TL;DR: A novel nonlinear filter, which incorporates the concept of exponential sinusoidal models into nonlinear filters based on functional link networks (FLNs) has been developed in this paper and an adaptive exponential filtered-s least mean square algorithm has been derived.
Abstract: A novel nonlinear filter, which incorporates the concept of exponential sinusoidal models into nonlinear filters based on functional link networks (FLNs) has been developed in this paper. The proposed filter is designed to provide improved convergence characteristics over traditional FLN filters. The conventional trigonometric FLN may be considered as a special case of the proposed adaptive exponential FLN (AEFLN). An adaptive exponential least mean square (AELMS) algorithm has been derived and the same has been successfully applied for identification of a couple of nonlinear plants. The AEFLN-based nonlinear active noise control (ANC) system has also been designed and an adaptive exponential filtered-s least mean square (AEFsLMS) algorithm has been developed to update the weights as well as the exponential factor. Simulation study has revealed the improved noise mitigation offered by the AEFLN-based nonlinear ANC system.
TL;DR: This paper addresses the stability problem for a class of switched nonlinear systems subject to random disturbances whose τ-order moments (τ > 1) are finite by using the average dwell-time approach to study the noise-to-state stability, the eλt-weighted (integral) noise- to- state stability and the global asymptotic stability of random switched systems.
Abstract: This paper addresses the stability problem for a class of switched nonlinear systems subject to random disturbances whose $\tau $ -order moments ( $\tau >1$ ) are finite. First, some general conditions are given to guarantee the existence and uniqueness of solutions to random switched systems. Next, these results are used to deduce the criteria of noise-to-state stability under probabilistic switching signal. Then, the average dwell-time approach is adopted to study the noise-to-state stability, the $e^{\lambda t}$ -weighted (integral) noise-to-state stability and the global asymptotic stability of random switched systems. All the criteria on global existence and stability of solutions are developed by virtue of multiple Lyapunov functions. Finally, two numerical examples are given to demonstrate the validity of the theoretical results.
TL;DR: The mathematical foundations of the security implications of utilizing various on-chip voltage converters as a countermeasure against differential power analysis (DPA) attacks are investigated and an exhaustive mathematical analysis of a recently proposed converter-reshuffling (CoRe) technique is presented.
Abstract: In this paper, the mathematical foundations of the security implications of utilizing various on-chip voltage converters as a countermeasure against differential power analysis (DPA) attacks are investigated. An exhaustive mathematical analysis of a recently proposed converter-reshuffling (CoRe) technique is presented where measurement to disclose (MTD) is used to compare the security of the proposed on-chip CoRe regulator with the security of conventional on-chip voltage regulators. A DPA-resistant and lightweight advanced encryption standard (AES) engine implementation that leverages the CoRe technique is proposed. The impact of the centralized and distributed placement of the voltage regulators on the security of a pipelined AES engine is explored. The security implications of the relationship between the clock frequency of the device under attack and the switching frequency of the voltage regulator are investigated. As compared to an unprotected AES engine, the MTD value of the proposed improved pipelined AES engine with a centralized on-chip CoRe regulator is enhanced over 9100 times.
TL;DR: In this paper, the authors present an example OPF problem with two equivalent formulations, and demonstrate that physically-based conditions cannot universally explain algorithm behavior, and that the SDP relaxation fails for one formulation but succeeds in finding the global solution to the other.
Abstract: Recently, there has been significant interest in convex relaxations of the optimal power flow (OPF) problem. A semidefinite programming (SDP) relaxation globally solves many OPF problems. However, there exist practical problems for which the SDP relaxation fails to yield the global solution. Conditions for the success or failure of the SDP relaxation are valuable for determining whether the relaxation is appropriate for a given OPF problem. To move beyond existing conditions, which only apply to a limited class of problems, a typical conjecture is that failure of the SDP relaxation can be related to physical characteristics of the system. By presenting an example OPF problem with two equivalent formulations, this paper demonstrates that physically based conditions cannot universally explain algorithm behavior. The SDP relaxation fails for one formulation but succeeds in finding the global solution to the other formulation. Since these formulations represent the same system, success (or otherwise) of the SDP relaxation must involve factors beyond just the network physics. The lack of universal physical conditions for success of the SDP relaxation motivates the development of tighter convex relaxations capable of solving a broader class of problems. Tools from polynomial optimization theory provide a means of developing tighter relaxations. This paper uses the example problem to illustrate relaxations from the Lasserre hierarchy for polynomial optimization and a related “mixed semidefinite/second-order cone programming” hierarchy.
TL;DR: A physical memristor/resistive switching device SPICE compact model is proposed, able to accurately fit both unipolar/bipolar devices settling to its current-voltage relationship, capable of reproducing essential device characteristics such as multilevel storage, temperature dependence, cycle/event handling and even the evolution of variability/parameter degradation with time.
Abstract: In this work, we propose a physical memristor/resistive switching device SPICE compact model, that is able to accurately fit both unipolar/bipolar devices settling to its current-voltage relationship. The proposed model is capable of reproducing essential device characteristics such as multilevel storage, temperature dependence, cycle/event handling and even the evolution of variability/parameter degradation with time. The developed compact model has been validated against two physical devices, fitting unipolar and bipolar switching. With no requirement of Verilog-A code, LTSpice, and Spectre simulations reproduce distinctive phenomena such as the preforming state, voltage/cycle dependent random telegraph noise and device degradation.
TL;DR: This paper reviews how tiny transducers generate power and how state-of-the-art diode bridges and switched inductors and their derivatives draw and output as much power as possible.
Abstract: Wireless microsystems can add intelligence to hospitals, homes, and factories that can save money, energy, and lives Unfortunately, tiny batteries cannot store sufficient energy to sustain useful microsystems for long, and replacing or recharging the batteries of hundreds of networked nodes is costly and invasive in the case of the human body Thankfully, shocks and vibrations are prevalent in many applications, so ambient kinetic energy can continually replenish batteries to extend the life of the systems they support And since tiny devices produce minimal damping effects on motion, they can draw as much power as the microelectronics allow Unfortunately, uncollected charge, breakdown voltages, and energy losses limit how much power harvesting microsystems can generate This is why this paper reviews how tiny transducers generate power and how state-of-the-art diode bridges and switched inductors and their derivatives draw and output as much power as possible Of prevailing technologies, in fact, the recycling bridge pre-damps the transducer at the highest voltage possible all the time to output the highest power But because it still needs a regulating charger to stay at its maximum power point, other pre-damping switched inductors suffer lower losses and require less space Although the pre-damping bridgeless solution pre-damps every other half cycle, it generates comparable power with only two switches No harvester, however, escapes the limits that power losses and breakdown voltages impose, so output power is always finite, and in the case of miniaturized systems, not very high
TL;DR: This paper introduces an efficient reconfigurable, multiple voltage gain switched-capacitor dc-dc buck converter as part of a power management unit for wearable electronics.
Abstract: This paper introduces an efficient reconfigurable, multiple voltage gain switched-capacitor dc-dc buck converter as part of a power management unit for wearable electronics. The proposed switched-capacitor converter has an input voltage of 0.6 V to 1.2 V generated from an energy harvesting source. The switched-capacitor converter utilizes pulse frequency modulation to generate multiple regulated output voltage levels, namely 1 V, 0.8 V, and 0.6 V based on two reconfigurable bits over a wide range of load currents from 10 $\mu\text{A}$ to 800 $\mu\text{A}$ . The switched-capacitor converter is designed and fabricated in 65-nm low-power CMOS technology and occupies an area of 0.493 mm2. The design utilizes a stack of MIM and MOS capacitances to optimize the circuit area and efficiency. The measured peak efficiency is 80% at a load current of 800 $\mu\text{A}$ and regulated load voltage of 1 V.
TL;DR: An ultra-low voltage, low power, low line sensitivity MOSFET-only sub-threshold voltage reference with no amplifiers is presented, which allows a remarkable reduction in the minimum supply voltage and power consumption and second-order compensation improves the temperature stability.
Abstract: An ultra-low voltage, low power, low line sensitivity MOSFET-only sub-threshold voltage reference with no amplifiers is presented. The low sensitivity is realized by the difference between two complementary currents and second-order compensation improves the temperature stability. The bulk-driven technique is used and most of the transistors work in the sub-threshold region, which allow a remarkable reduction in the minimum supply voltage and power consumption. Moreover, a trimming circuit is adopted to compensate the process-related reference voltage variation while the line sensitivity is not affected. The proposed voltage reference has been fabricated in the 0.18 $\mu\text{m}$ 1.8 V CMOS process. The measurement results show that the reference could operate on a 0.45 V supply voltage. For supply voltages ranging from 0.45 to 1.8 V the power consumption is 15.6 nW, and the average temperature coefficient is 59.4 ppm/°C across a temperature range of −40 to 85 °C and a mean line sensitivity of 0.033%. The power supply rejection ratio measured at 100 Hz is −50.3 dB. In addition, the chip area is 0.013 mm2.
TL;DR: A thorough study of the dynamics emerging in the nanoscale element under various input/initial condition combinations reveals a fundamental property of the tantalum oxide device, which was unnoticed so far, which implies the uniqueness of asymptotic behavior of the memristor.
Abstract: This work presents a detailed study of the nonlinear dynamics of a tantalum oxide memristor recently fabricated at Hewlett Packard Labs. Our investigations uncover direct current, quasi-static, and alternating current behavior of the nanodevice. A thorough study of the dynamics emerging in the nanoscale element under various input/initial condition combinations reveals a fundamental property of the tantalum oxide device, which was unnoticed so far. The initial condition has no effect on the steady-state operation of the memristor under non-zero input. This property, known as fading memory in system theory, implies the uniqueness of asymptotic behavior of the memristor. The progressive input-induced memory erase phenomenon is solely determined by the switching dynamics of the nanodevice, mathematically described by the state evolution function, which governs the rate of evolution of the memristor state. A constant-sign DC input will activate on or off switching dynamics only. Consequently, due to the limited on/off memductance ratio, the memristor will asymptotically attain a fully-conducting or highly-resistive state, irrespective of the initial condition. Most interestingly, under AC periodic excitations, it is the pronounced asymmetry in the state dependence of on and off switching processes which is at the basis of the reported history erase effect. It is important to point out that this novel fading memory phenomenon does not compromise the nonvolatile behavior of the nanostructure. In fact, despite the device may be stimulated so as to forget its past history, it still has a continuum of analog nonvolatile memory states.
TL;DR: Five novel VLA architectures, based on Brent-Kung, Ladner-Fisher, Sklansky, Hybrid Han-Carlson, and Carry increment parallel-prefix topologies are proposed and results show that proposed VLAs outperform previous speculative architectures and standard (non-speculative) adders when high-speed is required.
Abstract: A variable latency adder (VLA) reduces average addition time by using speculation: the exact arithmetic function is replaced by an approximated one, that is faster and gives correct results most of the times. When speculation fails, an error detection and correction circuit gives the correct result in the following clock cycle. Previous papers investigate VLAs based on Kogge-Stone, Han-Carlson or carry select topologies, speculating that carry propagation involves only a few consecutive bits. In several applications using 2's complement representation, however, operands have a Gaussian distribution and a nontrivial portion of carry chains can be as long as the adder size. In this paper we propose five novel VLA architectures, based on Brent-Kung, Ladner-Fisher, Sklansky, Hybrid Han-Carlson, and Carry increment parallel-prefix topologies. Moreover, we present a new efficient error detection and correction technique, that makes proposed VLAs suitable for applications using 2's complement representation. In order to investigate VLAs performances, proposed architectures have been synthesized using the UMC 65 nm library, for operand lengths ranging from 32 to 128 bits. Obtained results show that proposed VLAs outperform previous speculative architectures and standard (non-speculative) adders when high-speed is required.
TL;DR: This paper proposes two distributed synchronization protocols for a network of continuous-time coupled harmonic oscillators by utilizing current and past relative sampled position data, respectively.
Abstract: This paper proposes two distributed synchronization protocols for a network of continuous-time coupled harmonic oscillators by utilizing current and past relative sampled position data, respectively. Some necessary and sufficient conditions in terms of coupling strength and sampling period are established to achieve network synchronization. By designing the coupling strength based on the nonzero eigenvalues of the Laplacian matrix of the network, it is shown that the synchronization in the network can be reached if and only if the sampling period is taken from a sequence of disjoint open intervals. In particular, when the Laplacian matrix has some complex eigenvalues, it is found that the sampling period should be larger than a positive threshold, that is, any small sampling period less than this threshold will not lead to network synchronization. Numerical examples are given to demonstrate the effectiveness of the theoretical analysis.
TL;DR: Numerical appraisals focus on hybrid control systems recast into delay algebraic-differential equations as well as a benchmark dynamic power system model with inclusion of long transmission lines.
Abstract: This paper focuses on the small-signal stability analysis of systems modelled as differential-algebraic equations and with inclusions of delays in both differential equations and algebraic constraints. The paper considers the general case for which the characteristic equation of the system is a series of infinite terms corresponding to an infinite number of delays. The expression of such a series and the conditions for its convergence are first derived analytically. Then, the effect on small-signal stability analysis is evaluated numerically through a Chebyshev discretization of the characteristic equations. Numerical appraisals focus on hybrid control systems recast into delay algebraic-differential equations as well as a benchmark dynamic power system model with inclusion of long transmission lines.
TL;DR: A CMOS power amplifier integrated circuit with an optimized dual-mode supply modulator, based on a hybrid buck converter consisting of a wideband linear amplifier and a highly efficient switching amplifier, provides two operation modes: envelope tracking for high average output power and average power tracking (APT) for low output power.
Abstract: A CMOS power amplifier integrated circuit with an optimized dual-mode supply modulator is presented. The dual-mode supply modulator, based on a hybrid buck converter consisting of a wideband linear amplifier and a highly efficient switching amplifier, provides two operation modes: envelope tracking (ET) for high average output power and average power tracking (APT) for low output power. For the APT mode, the linear amplifier is switched off and the switching amplifier operates as a normal buck converter to supply DC voltage to the power amplifier according to the average output power. The optimum switch sizes of the switching amplifier were analyzed and applied for each operation mode for higher efficiency. An integrated circuit with a power amplifier and the dual-mode supply modulator was designed and fabricated using a 0.18- $\mu\mbox{m}$ CMOS process for LTE applications at a frequency of 0.78 GHz. For the 16-QAM uplink LTE signal, the measured efficiency with an ET mode is as high as 45.4%, which is 7.0% higher than that from the stand-alone power amplifier at an average output power of 24 dBm. An efficiency of 14.1% was achieved with an APT mode at an average output power of 9 dBm. This is 3.2% higher than that with the ET mode.