Showing papers in "IEEE Transactions on Circuits and Systems I-regular Papers in 2004"
TL;DR: This work explains the main reason why significantly less local controllers are required by specifically pinning the most highly connected nodes in a scale-free network than those required by the randomly pining scheme, and why there is no significant difference between specifically and randomly pinning schemes for controlling random dynamical networks.
Abstract: It is now known that the complexity of network topology has a great impact on the stabilization of complex dynamical networks. In this work, we study the control of random networks and scale-free networks. Conditions are investigated for globally or locally stabilizing such networks. Our strategy is to apply local feedback control to a small fraction of network nodes. We propose the concept of virtual control for microscopic dynamics throughout the process with different pinning schemes for both random networks and scale-free networks. We explain the main reason why significantly less local controllers are required by specifically pinning the most highly connected nodes in a scale-free network than those required by the randomly pinning scheme, and why there is no significant difference between specifically and randomly pinning schemes for controlling random dynamical networks. We also study the synchronization phenomenon of controlled dynamical networks in the stabilization process, both analytically and numerically.
878 citations
TL;DR: It is shown that the maximum synchronizability of a network is completely determined by its associated feedback system, which has a precise meaning in terms of synchronous communication.
Abstract: Many real-world complex networks display a small-world feature-a high degree of clustering and a small average distance. We show that the maximum synchronizability of a network is completely determined by its associated feedback system, which has a precise meaning in terms of synchronous communication. We introduce a new concept of synchronizability matrix to characterize the maximum synchronizability of a network. Several new concepts, such as sensitive edge and robust edge, are proposed for analyzing the robustness and fragility of synchronization of a network. Using the knowledge of synchronizability, we can purposefully increase the robustness of the network synchronization and prevent it from attacks. Some applications in small-world networks are also discussed briefly.
438 citations
TL;DR: This work investigates synchronization of an array of linearly coupled identical connected neural networks with delays with delays using the linear matrix inequality approach to judge synchronization with global convergence property.
Abstract: We investigate synchronization of an array of linearly coupled identical connected neural networks with delays; Variational method is used to investigate local synchronization. Global exponential stability is studied, too. We do not assume that the coupling matrix A is symmetric or irreducible. The linear matrix inequality approach is used to judge synchronization with global convergence property.
409 citations
TL;DR: This paper presents a new technique for the passivity enforcement of linear time-invariant multiport systems in state-space form based on a study of the spectral properties of related Hamiltonian matrices, aimed at the displacement of the imaginary eigenvalues of the Hamiltonian matrix.
Abstract: This paper presents a new technique for the passivity enforcement of linear time-invariant multiport systems in state-space form. This technique is based on a study of the spectral properties of related Hamiltonian matrices. The formulation is applicable in case the system input-output transfer function is in admittance, impedance, hybrid, or scattering form. A standard test for passivity is first performed by checking the existence of imaginary eigenvalues of the associated Hamiltonian matrix. In the presence of imaginary eigenvalues the system is not passive. In such a case, a new result based on first-order perturbation theory is presented for the precise characterization of the frequency bands where passivity violations occur. This characterization is then used for the design of an iterative perturbation scheme of the state matrices, aimed at the displacement of the imaginary eigenvalues of the Hamiltonian matrix. The result is an effective algorithm leading to the compensation of the passivity violations. This procedure is very efficient when the passivity violations are small, so that first-order perturbation is applicable. Several examples illustrate and validate the procedure.
377 citations
TL;DR: Simulation results show that the 4- 2 compressor with the proposed XOR-XNOR module and the new fast 5-2 compressor architecture are able to function at supply voltage as low as 0.6 V, and outperform many other architectures including the classical CMOS logic compressors and variants of compressors constructed with various combinations of recently reported superior low-power logic cells.
Abstract: This paper presents several architectures and designs of low-power 4-2 and 5-2 compressors capable of operating at ultra low supply voltages. These compressor architectures are anatomized into their constituent modules and different static logic styles based on the same deep submicrometer CMOS process model are used to realize them. Different configurations of each architecture, which include a number of novel 4-2 and 5-2 compressor designs, are prototyped and simulated to evaluate their performance in speed, power dissipation and power-delay product. The newly developed circuits are based on various configurations of the novel 5-2 compressor architecture with the new carry generator circuit, or existing architectures configured with the proposed circuit for the exclusive OR (XOR) and exclusive NOR ( XNOR) [XOR-XNOR] module. The proposed new circuit for the XOR-XNOR module eliminates the weak logic on the internal nodes of pass transistors with a pair of feedback PMOS-NMOS transistors. Driving capability has been considered in the design as well as in the simulation setup so that these 4-2 and 5-2 compressor cells can operate reliably in any tree structured parallel multiplier at very low supply voltages. Two new simulation environments are created to ensure that the performances reflect the realistic circuit operation in the system to which these cells are integrated. Simulation results show that the 4-2 compressor with the proposed XOR-XNOR module and the new fast 5-2 compressor architecture are able to function at supply voltage as low as 0.6 V, and outperform many other architectures including the classical CMOS logic compressors and variants of compressors constructed with various combinations of recently reported superior low-power logic cells.
349 citations
TL;DR: Analysis of a 15-year time series of North American electric power transmission system blackouts shows evidence of self-organized criticality (SOC), and blackout data seem consistent with SOC.
Abstract: We analyze a 15-year time series of North American electric power transmission system blackouts for evidence of self-organized criticality (SOC). The probability distribution functions of various measures of blackout size have a power tail and rescaled range analysis of the time series shows moderate long-time correlations. Moreover, the same analysis applied to a time series from a sandpile model known to be self-organized critical gives results of the same form. Thus, the blackout data seem consistent with SOC. A qualitative explanation of the complex dynamics observed in electric power system blackouts is suggested.
335 citations
TL;DR: A two-dimensional (2D) Poincare/spl acute/ return map is rigorously derived for verifying the chaotic behaviors of the double-scroll chaotic attractor, which is a basic generator of various multiscroll chaotic attractors investigated in the paper.
Abstract: This paper initiates a saturated function series approach for chaos generation. The systematic saturated function series methodology developed here can create multiscroll chaotic attractors from a three-dimensional (3D) linear autonomous system with a simple saturated function series controller, including one-directional n-scroll, two-directional n/spl times/m-grid scroll, and 3-D n/spl times/m/spl times/l-grid scroll chaotic attractors. The dynamical behaviors and chaos generation mechanism of multiscroll systems are further investigated by analyzing the system trajectories. In particular, a two-dimensional (2D) Poincare/spl acute/ return map is rigorously derived for verifying the chaotic behaviors of the double-scroll chaotic attractor, which is a basic generator of various multiscroll chaotic attractors investigated in the paper.
289 citations
TL;DR: A high data- rate frequency-shift keying (FSK) modulation protocol, a wideband inductive link, and three demodulator circuits have been developed with a data-rate-to-carrier-frequency ratio of up to 67%.
Abstract: A high data-rate frequency-shift keying (FSK) modulation protocol, a wideband inductive link, and three demodulator circuits have been developed with a data-rate-to-carrier-frequency ratio of up to 67%. The primary application of this novel FSK modulation/demodulation technique is to send data to inductively powered wireless biomedical implants at data rates in excess of 1 Mbps, using comparable carrier frequencies. This method can also be used in other applications such as radio-frequency identification tags and contactless smartcards by adding a back telemetry link. The inductive link utilizes a series-parallel inductive-capacitance tank combination on the transmitter side to provide more than 5 MHz of bandwidth. The demodulator circuits detect data bits by directly measuring the duration of each received FSK carrier cycle, as well as derive a constant frequency clock, which is used to sample the data bits. One of the demodulator circuits, digital FSK, occupies 0.29 mm/sup 2/ in the AMI 1.5-/spl mu/m, 2M/2P, standard CMOS process, and consumes 0.38 mW at 5 V. This circuit is simulated up to 4 Mbps, and experimentally tested up to 2.5 Mbps with a bit error rate of 10/sup -5/, while receiving a 5/10-MHz FSK carrier signal. It is also used in a wireless implantable neural microstimulation system.
282 citations
TL;DR: The proposed TRBG is subjected to statistical tests which are the well-known Federal Information Processing Standards-140-1 and Diehard test suite in the area of cryptography and successfully passes all these tests and can be implemented in integrated circuits.
Abstract: In this paper, a novel true random bit generator (TRBG) based on a double-scroll attractor is proposed. The double-scroll attractor is obtained from a simple model which is qualitatively similar to Chua's circuit. In order to face the challenge of using the proposed TRBG in cryptography, the proposed TRBG is subjected to statistical tests which are the well-known Federal Information Processing Standards-140-1 and Diehard test suite in the area of cryptography. The proposed TRBG successfully passes all these tests and can be implemented in integrated circuits.
272 citations
TL;DR: It is shown how speed, resolution, and A/D complexity can be optimized for a given design, and how with some special digital filters improved speed/resolution ratio can be achieved.
Abstract: Analog-Digital (A/D) converters used in instrumentation and measurements often require high absolute accuracy, including very high linearity and negligible dc offset. The realization of high-resolution Nyquist-rate converters becomes very expensive when the resolution exceeds 16 bits. The conventional delta-sigma (/spl Delta//spl Sigma/) structures used in telecommunication and audio applications usually cannot satisfy the requirements of high absolute accuracy and very small offset. The incremental (or integrating) converter provides a solution for such measurement applications, as it has most advantages of the /spl Delta//spl Sigma/ converter, yet is capable of offset-free and accurate conversion. In this paper, theoretical and practical aspects of higher order incremental converters are discussed. The operating principles, topologies, specialized digital filter design methods, and circuit level issues are all addressed. It is shown how speed, resolution, and A/D complexity can be optimized for a given design, and how with some special digital filters improved speed/resolution ratio can be achieved. The theoretical results are verified by showing design examples and simulation results.
269 citations
TL;DR: A stable low dropout (LDO) voltage regulator topology for low equivalent series resistance (ESR) capacitive loads is presented and it is demonstrated that this scheme realizes robust frequency compensation, facilitates the use of multilayer ceramic capacitors for the load of LDO regulators, and improves transient response and noise performance.
Abstract: A stable low dropout (LDO) voltage regulator topology for low equivalent series resistance (ESR) capacitive loads is presented. The proposed scheme generates a zero internally instead of relying on the zero generated by the load capacitor and its ESR combination for stability. It is demonstrated that this scheme realizes robust frequency compensation, facilitates the use of multilayer ceramic capacitors for the load of LDO regulators, and improves transient response and noise performance. Test results from a prototype fabricated in AMI 0.5-/spl mu/m CMOS technology provide the most important parameters of the regulator viz., ground current, load regulation, line regulation, output noise, and start-up time.
TL;DR: It is shown that the amplitude information of a bandlimited signal can be perfectly recovered if the difference between any two consecutive values of the time sequence is bounded by the inverse of the Nyquist rate.
Abstract: A time encoding machine is a real-time asynchronous mechanism for encoding amplitude information into a time sequence. We investigate the operating characteristics of a machine consisting of a feedback loop containing an adder, a linear filter, and a noninverting Schmitt trigger. We show that the amplitude information of a bandlimited signal can be perfectly recovered if the difference between any two consecutive values of the time sequence is bounded by the inverse of the Nyquist rate. We also show how to build a nonlinear inverse time decoding machine (TDM) that perfectly recovers the amplitude information from the time sequence. We demonstrate the close relationship between the recovery algorithms for time encoding and irregular sampling. We also show the close relationship between time encoding and a number of nonlinear modulation schemes including FM and asynchronous sigma-delta modulation. We analyze the sensitivity of the time encoding recovery algorithm and demonstrate how to construct a TDM that perfectly recovers the amplitude information from the time sequence and is trigger parameter insensitive. We derive bounds on the error in signal recovery introduced by the quantization of the time sequence. We compare these with the recovery error introduced by the quantization of the amplitude of the bandlimited signal when irregular sampling is employed. Under Nyquist-type rate conditions, quantization of a bandlimited signal in the time and amplitude domains are shown to be largely equivalent methods of information representation.
TL;DR: In this paper, a generalized canonical nonlinear programming circuit (G-NPC) was proposed to solve a general class of nonsmooth non-linear programming problems, where the objective function and constraints are assumed to satisfy only the weak condition of being regular functions.
Abstract: In 1988 Kennedy and Chua introduced the dynamical canonical nonlinear programming circuit (NPC) to solve in real time nonlinear programming problems where the objective function and the constraints are smooth (twice continuously differentiable) functions. In this paper, a generalized circuit is introduced (G-NPC), which is aimed at solving in real time a much wider class of nonsmooth nonlinear programming problems where the objective function and the constraints are assumed to satisfy only the weak condition of being regular functions. G-NPC, which derives from a natural extension of NPC, has a neural-like architecture and also features the presence of constraint neurons modeled by ideal diodes with infinite slope in the conducting region. By using the Clarke's generalized gradient of the involved functions, G-NPC is shown to obey a gradient system of differential inclusions, and its dynamical behavior and optimization capabilities, both for convex and nonconvex problems, are rigorously analyzed in the framework of nonsmooth analysis and the theory of differential inclusions. In the special important case of linear and quadratic programming problems, salient dynamical features of G-NPC, namely the presence of sliding modes , trajectory convergence in finite time, and the ability to compute the exact optimal solution of the problem being modeled, are uncovered and explained in the developed analytical framework.
TL;DR: The ACE16k as mentioned in this paper is a member of the third generation of the ACE chips, which is designed in a 0.35-/spl mu/m standard CMOS technology, and exhibits peak computing figures of 330 GOPS, 3.6 GOPS/mm/sup 2/ and 82.5 GOPS /W.
Abstract: Today, with 0.18-/spl mu/m technologies mature and stable enough for mixed-signal design with a large variety of CMOS compatible optical sensors available and with 0.09-/spl mu/m technologies knocking at the door of designers, we can face the design of integrated systems, instead of just integrated circuits. In fact, significant progress has been made in the last few years toward the realization of vision systems on chips (VSoCs). Such VSoCs are eventually targeted to integrate within a semiconductor substrate the functions of optical sensing, image processing in space and time, high-level processing, and the control of actuators. The consecutive generations of ACE chips define a roadmap toward flexible VSoCs. These chips consist of arrays of mixed-signal processing elements (PEs) which operate in accordance with single instruction multiple data (SIMD) computing architectures and exhibit the functional features of CNN Universal Machines. They have been conceived to cover the early stages of the visual processing path in a fully-parallel manner, and hence more efficiently than DSP-based systems. Across the different generations, different improvements and modifications have been made looking to converge with the newest discoveries of neurobiologists regarding the behavior of natural retinas. This paper presents considerations pertaining to the design of a member of the third generation of ACE chips, namely to the so-called ACE16k chip. This chip, designed in a 0.35-/spl mu/m standard CMOS technology, contains about 3.75 million transistors and exhibits peak computing figures of 330 GOPS, 3.6 GOPS/mm/sup 2/ and 82.5 GOPS/W. Each PE in the array contains a reconfigurable computing kernel capable of calculating linear convolutions on 3/spl times/3 neighborhoods in less than 1.5 /spl mu/s, imagewise Boolean combinations in less than 200 ns, imagewise arithmetic operations in about 5 /spl mu/s, and CNN-like temporal evolutions with a time constant of about 0.5 /spl mu/s. Unfortunately, the many ideas underlying the design of this chip cannot be covered in a single paper; hence, this paper is focused on, first, placing the ACE16k in the ACE chip roadmap and, then, discussing the most significant modifications of ACE16K versus its predecessors in the family.
TL;DR: A tutorial review of complex signal processing for wireless applications emphasizing a graphical and pictorial description rather than an equation-based approach is presented.
Abstract: Wireless systems often make use of the quadrature relationship between pairs of signals to effectively cancel out-of-band and interfering in-band signal components. The understanding of these systems is often simplified by considering both the signals and system transfer functions as "complex" quantities. The complex approach is especially useful in highly integrated multistandard receivers where the use of narrow-band fixed-coefficient filters at the RF and high IF must be minimized. This paper first presents a tutorial review of complex signal processing for wireless applications. The review emphasizes a graphical and pictorial description rather than an equation-based approach. Next, a number of classical modulation architectures are described using this formulation. Finally, more recent developments such as complex filters, image-reject mixers, low-IF receivers, and oversampling analog-digital converters are discussed.
TL;DR: An adaptive digital technique to calibrate pipelined analog-to-digital converters (ADCs) and shows that, with the help of a slow but accurate ADC, the proposed code-domain adaptive finite-impulse-response filter is sufficient to remove the effect of component errors.
Abstract: We present an adaptive digital technique to calibrate pipelined analog-to-digital converters (ADCs). Rather than achieving linearity by adjustment of analog component values, the new approach infers component errors from conversion results and applies digital postprocessing to correct those results. The scheme proposed here draws close analogy to the channel equalization problem commonly encountered in digital communications. We show that, with the help of a slow but accurate ADC, the proposed code-domain adaptive finite-impulse-response filter is sufficient to remove the effect of component errors including capacitor mismatch, finite op-amp gain, op-amp offset, and sampling-switch-induced offset, provided they are not signal-dependent. The algorithm is all digital, fully adaptive, data-driven, and operates in the background. Strong tradeoffs between accuracy and speed of pipelined ADCs are greatly relaxed in this approach with the aid of digital correction techniques. Analog precision problems are translated into the complexity of digital signal-processing circuits, allowing this approach to benefit from CMOS device scaling in contrast to most conventional correction techniques.
TL;DR: Techniques for correcting and detecting sample-time error in a two-channel ADC are described, and simulation results are presented.
Abstract: Offset mismatch, gain mismatch, and sample-time error between time-interleaved channels limit the performance of time-interleaved analog-to-digital converters (ADCs). This paper focuses on the sample-time error. Techniques for correcting and detecting sample-time error in a two-channel ADC are described, and simulation results are presented.
TL;DR: An asynchronous implementation of a scalable multiple-access inter-chip link that communicates binary activity between two-dimensional arrays fabricated in deep submicrometer CMOS is presented, synthesized by performing a series of program decompositions.
Abstract: We present a transmitter for a scalable multiple-access inter-chip link that communicates binary activity between two-dimensional arrays fabricated in deep submicrometer CMOS. Transmission is initiated by active cells but cells are not read individually. An entire row is read in parallel; this increases communication capacity with integration density. Access is random but not inequitable. A row is not reread until all those waiting are serviced; this increases parallelism as more of its cells become active in the mean time. Row and column addresses identify active cells but they are not transmitted simultaneously. The row address is followed sequentially by a column address for each active cell; this cuts pad count in half without sacrificing capacity. We synthesized an asynchronous implementation by performing a series of program decompositions, starting from a high-level description. Links using this design have been implemented successfully in three generations of submicrometer CMOS technology.
TL;DR: It is shown that the requirement of a high-Q factor to realize a low- power oscillator need not be contradictory to achieving optimal far-field radiation characteristics, and an approach to sizing loop antennas for low-power oscillator transmitters is suggested.
Abstract: Analysis determining the optimal transmission frequency for maximum power transfer across a short-range wireless link is introduced, including a comparison of near-field transmission with far-field transmission. A new near-field power transfer formula has been derived, which allows direct comparison with the well-known far-field Friis transmission formula. Operating charts are presented, which provide the designer with the preferred transmission frequency as a function of distance and antenna dimensions, together with surface plots which show the power transfer for this frequency. The analysis, performed for loop antennas, has been used to evaluate the oscillator transmitter as a low-power topology. It is shown that the requirement of a high-Q factor to realize a low-power oscillator need not be contradictory to achieving optimal far-field radiation characteristics. Based on this fact an approach to sizing loop antennas for low-power oscillator transmitters is suggested.
TL;DR: A systematic approach is proposed to develop a high throughput decoder for quasi-cyclic low-density parity check (LDPC) codes, whose parity check matrix is constructed by circularly shifted identity matrices, and the maximum concurrency of the two stages is explored by a novel scheduling algorithm.
Abstract: In this paper, a systematic approach is proposed to develop a high throughput decoder for quasi-cyclic low-density parity check (LDPC) codes, whose parity check matrix is constructed by circularly shifted identity matrices. Based on the properties of quasi-cyclic LDPC codes, the two stages of belief propagation decoding algorithm, namely, check node update and variable node update, could be overlapped and thus the overall decoding latency is reduced. To avoid the memory access conflict, the maximum concurrency of the two stages is explored by a novel scheduling algorithm. Consequently, the decoding throughput could be increased by about twice assuming dual-port memory is available.
TL;DR: The continuum model presented here therefore relaxes the isotropy and homogeneity constraints assumed in the prior work and is able to model the real power systems that tend to be highly irregular in terms of their geographical topology and the power injections, loads, and shunt elements at the bus locations.
Abstract: In this paper, we propose a continuum model for real power systems that tend to be highly irregular in terms of their geographical topology and the power injections, loads, and shunt elements at the bus locations. The continuum model presented here therefore relaxes the isotropy and homogeneity constraints assumed in our prior work. The network, with its transmission lines, generators, and loads, are treated as a continuum in spatial coordinates. We are consequently able to model the system as a pair of nonlinear partial differential equations (PDEs). The first PDE is the continuum equivalent of the load flow equations of the power system and is a boundary value problem. The second equation is the continuum equivalent of the swing equations of the power system. The parameters of these equations are functions of spatial coordinates and the network topology is embedded in them. The computational effort needed to solve the PDEs depends on the uniformity in the parameter distributions. A systematic approach of smoothening the parameter distributions is also proposed. While a continuum system with these smooth parameter distributions looses some of its ability to accurately model the detailed behavior of the power system, the global behavior of the system remains preserved. Furthermore, the electromechanical wave propagation behavior observed in actual power systems is readily recognized from the PDE model. A theoretical analysis of the continuum model as well as test simulations show that disturbances in the system's phase angles propagate through the continuum system with velocities much slower than the speed of light and exhibit dispersion phenomena.
TL;DR: The estimation method requires no knowledge about the input signal except that it should be bandlimited to the Nyquist frequency for the complete ADC system, which means that the errors can be estimated while the ADC is running.
Abstract: To significantly increase the sampling rate of an A/D converter (ADC), a time-interleaved ADC system is a good option. The drawback of a time-interleaved ADC system is that the ADCs are not exactly identical due to errors in the manufacturing process. This means that time, gain, and offset mismatch errors are introduced in the ADC system. These errors cause distortion in the sampled signal. In this paper, we present a method for estimation and compensation of the mismatch errors. The estimation method requires no knowledge about the input signal except that it should be bandlimited to the Nyquist frequency for the complete ADC system. This means that the errors can be estimated while the ADC is running. The method is also adaptive to slow changes in the mismatch errors. The estimation method has been validated with simulations and measurements from a time-interleaved ADC system.
TL;DR: In this article, an exact analysis for third-order charge-pump phase-locked loops using state equations is presented, and the effect of the loop parameters and the reference frequency on the loop phase margin and stability is analyzed.
Abstract: In this paper, we present an exact analysis for third-order charge-pump phase-locked loops using state equations. Both the large-signal lock acquisition process and the small-signal linear tracking behavior are described using this analysis. The nonlinear state equations are linearized for the small-signal condition and the z-domain noise transfer functions are derived. A comparison to some of the existing analysis methods such as the impulse-invariant transformation and s-domain analysis is provided. The effect of the loop parameters and the reference frequency on the loop phase margin and stability is analyzed. The analysis is verified using behavioral simulations in MATLAB and SPECTRE.
TL;DR: A general comprehensive stochastic model of the substrate and P/G noise sources in very large-scale integration (VLSI) circuits is proposed and a comparison between the results obtained by the mathematical model and those obtained by HSPICE simulation prove the accuracy of the predicted model.
Abstract: Phase-locked loops (PLL) in radio-frequency (RF) and mixed analog-digital integrated circuits (ICs) experience substrate coupling due to the simultaneous circuit switching and power/ground (P/G) noise which translate to a timing jitter. In this paper. an analysis of the PLL timing jitter due to substrate noise resulting from P/G noise and large-signal switching is presented. A general comprehensive stochastic model of the substrate and P/G noise sources in very large-scale integration (VLSI) circuits is proposed. This is followed by calculation of the phase noise of the constituent voltage-controlled oscillator (VCO) in terms of the statistical properties of substrate and P/G noise. The PLL timing jitter is then predicted in response to the VCO phase noise. Our mathematical method is utilized to study the jitter-induced P/G noise in a CMOS PLL, which is designed and simulated in a 0.25-/spl mu/m standard CMOS process. A comparison between the results obtained by our mathematical model and those obtained by HSPICE simulation prove the accuracy of the predicted model.
TL;DR: In this article, the third-order intermodulation distortion in a MOSFET amplifier is analyzed by means of Volterra Series representation, which reveals a significant peaking of the thirdorder intercept point in the moderate inversion region.
Abstract: The implications for radio frequency circuit design of the nonlinear behavior of a MOSFET transistor over all regions of operation, including moderate inversion region, are investigated. Third-order intermodulation distortion in a MOSFET amplifier is analyzed by means of Volterra Series representation. Analysis and measurements reveal a significant peaking, or "sweet-spot" of the third-order intercept point in the moderate inversion region. As a result, a significant increase in linearity with low power consumption is possible. Analysis and measurements shows the dependance of distortion on the frequency, and transistor parameters, as well as the effects of the load impedance and feedback.
TL;DR: In this paper, a single-stage multibit /spl Delta-spl Sigma/ modulator with a high-order finite-impulse-response NTF is proposed to achieve high signal-toquantization-noise ratios at low oversampling ratio.
Abstract: High-speed high-resolution /spl Delta//spl Sigma/ analog-to-digital converters (ADCs) for broad-band communication applications must be designed at a low oversampling ratio (OSR) However, lowering the OSR limits the efficiency of a /spl Delta//spl Sigma/ ADC in achieving a high-resolution A/D conversion This paper presents several techniques that enable the OSR reduction in /spl Delta//spl Sigma/ ADCs without compromising the resolution 1) Noise transfer function (NTF) In this paper, a single-stage multibit /spl Delta//spl Sigma/ modulator with a high-order finite-impulse-response NTF is proposed to achieve high signal-to-quantization-noise ratios at low OSRs Its key features include: decreased circuit complexity, improved robustness to modulator coefficient variations, and reduced sensitivity to integrator nonlinearities Its performance is validated through behavioral simulations and compared to traditional /spl Delta//spl Sigma/ modulator structures 2) Signal transfer function (STF) This paper describes how the STF of a /spl Delta//spl Sigma/ modulator can be designed, independently of the NTF, in order to significantly reduce the harmonic distortion due to opamp nonidealities and to help lower the power dissipation 3) Dynamic element matching (DEM) is also presented Data weighted averaging (DWA) has prevailed as the most practical DEM technique to linearize the internal digital-to-analog converter (DAC) of a multibit /spl Delta//spl Sigma/ modulator, especially when the number of DAC elements is large However, the occurrence of in-band signal-dependent tones, when using DWA at a low OSR, degrades the spurious-free dynamic range This paper proposes a simple technique, called pseudo DWA, to solve the DWA tone problem without sacrificing the signal-to-noise ratio Its implementation adds no extra delay in the /spl Delta//spl Sigma/ feedback loop and requires only minimal additional digital hardware Existing schemes for DWA tone reduction are also compared
TL;DR: Dynamic comparators and multiplexers are designed using the diode-footed domino and conventional techniques to demonstrate the effectiveness of the proposed scheme in improving leakage-tolerance and performance of high fan-in circuits.
Abstract: A leakage-tolerant design technique for high fan-in dynamic logic circuits is presented. An NMOS transistor with gate and drain terminals tied together (diode) is added in series with the evaluation network of standard domino circuits. Due to the stacking effect, the leakage of the evaluation path significantly decreases, thereby improving the robustness of the circuit against deep-submicron subthreshold leakage and input noise. To improve the speed of the circuit, a current mirror is also employed in the evaluation network to increase the evaluation current. The proposed technique (diode-footed domino) exhibits considerable improvement in leakage and noise immunity as compared to the standard domino circuits. Simulation results of wide fan-in gates designed using Berkeley Predictive Technology Models of 70-nm technology demonstrate at least 1.9/spl times/ noise-immunity improvement at the same delay compared to the standard domino circuits. Dynamic comparators and multiplexers are designed using the diode-footed domino and conventional techniques to demonstrate the effectiveness of the proposed scheme in improving leakage-tolerance and performance of high fan-in circuits.
TL;DR: A new control scheme for a Class DE inverter, that is, frequency modulation/pulsewidth modulation (FM/PWM) control, which has one more degree of freedom for the control than the inverter with the conventional control scheme.
Abstract: This paper presents a new control scheme for a Class DE inverter, that is, frequency modulation/pulsewidth modulation (FM/PWM) control. Further, the FM/PWM controlled Class DE inverter is analyzed and we clarify performance characteristics. Since the FM/PWM controlled inverter has two control parameters, namely, the switching frequency and the switch-on duty ratio, it has one more degree of freedom for the control than the inverter with the conventional control scheme. The increased degree of freedom is used to minimize the switching losses. Therefore, it is possible to control the output power with high power-conversion efficiency for wide-range control. Carrying out the circuit experiments, we confirm that the experimental results agree well with the theoretical predictions quantitatively. For example, the proposed controlled inverter can control the output voltage from 56% to 191% of the optimum one, which is designed for 1.8 W at 1.0 MHz, with maintaining over 90% power-conversion efficiency.
TL;DR: The paper presents a practical object-oriented approach to implementing the DAIS model, which outlines a number of inverse problems, including parameter uncertainty, parameter estimation, grazing bifurcations, boundary value problems, and dynamic embedded optimization.
Abstract: Large disturbances in power systems often initiate complex interactions between continuous dynamics and discrete events. The paper develops a hybrid automaton that describes such behavior. Hybrid systems can be modeled in a systematic way by a set of differential-algebraic equations, modified to incorporate impulse (state reset) action and constraint switching. This differential-algebraic impulsive-switched (DAIS) model is a realization of the hybrid automaton. The paper presents a practical object-oriented approach to implementing the DAIS model. Each component of a system is modeled autonomously. Connections between components are established by simple algebraic equations. The systematic nature of the DAIS model enables efficient computation of trajectory sensitivities, which in turn facilitate algorithms for solving inverse problems. The paper outlines a number of inverse problems, including parameter uncertainty, parameter estimation, grazing bifurcations, boundary value problems, and dynamic embedded optimization.
TL;DR: This paper presents an analysis of the effect of duty ratio on power loss and efficiency of the Class-E amplifier and shows rapid drop in efficiency for low duty ratio (below approximately 30%).
Abstract: This paper presents an analysis of the effect of duty ratio on power loss and efficiency of the Class-E amplifier. Conduction loss for each Class-E circuit component is derived and total amplifier losses and efficiency are expressed as functions of duty ratio. Two identical 300-W Class-E amplifiers operating at 7.29 MHz are designed, constructed, and tested in the laboratory. Dependence of total efficiency upon duty ratio when using real components is derived and verified experimentally. Derived loss and efficiency equations demonstrate rapid drop in efficiency for low duty ratio (below approximately 30%). Experimental results very closely matched calculated power loss and efficiency.