Showing papers in "IEEE Transactions on Circuits and Systems I-regular Papers in 2005"

The flipped voltage follower: a useful cell for low-voltage low-power circuit design

Abstract: In this paper, a basic cell for low-power and/or low-voltage operation is identified. It is evidenced how different versions of this cell, coined as "flipped voltage follower (FVF)" have been used in the past for many applications. A detailed classification of basic topologies derived from the FVF is given. In addition, a comprehensive list of recently proposed low-voltage/low-power CMOS circuits based on the FVF is given. Although the paper has a tutorial taste, some new applications of the FVF are also presented and supported by a set of simulated and experimental results. Finally, a design example showing the application of the FVF to build systems based on translinear loops is described which shows the potential of this cell for the design of high-performance low-power/low-voltage analog and mixed-signal circuits.

Global asymptotic and robust stability of recurrent neural networks with time delays

Abstract: In this paper, two related problems, global asymptotic stability (GAS) and global robust stability (GRS) of neural networks with time delays, are studied. First, GAS of delayed neural networks is discussed based on Lyapunov method and linear matrix inequality. New criteria are given to ascertain the GAS of delayed neural networks. In the designs and applications of neural networks, it is necessary to consider the deviation effects of bounded perturbations of network parameters. In this case, a delayed neural network must be formulated as a interval neural network model. Several sufficient conditions are derived for the existence, uniqueness, and GRS of equilibria for interval neural networks with time delays by use of a new Lyapunov function and matrix inequality. These results are less restrictive than those given in the earlier references.

EEG-based drowsiness estimation for safety driving using independent component analysis

Abstract: Preventing accidents caused by drowsiness has become a major focus of active safety driving in recent years. It requires an optimal technique to continuously detect drivers' cognitive state related to abilities in perception, recognition, and vehicle control in (near-) real-time. The major challenges in developing such a system include: 1) the lack of significant index for detecting drowsiness and 2) complicated and pervasive noise interferences in a realistic and dynamic driving environment. In this paper, we develop a drowsiness-estimation system based on electroencephalogram (EEG) by combining independent component analysis (ICA), power-spectrum analysis, correlation evaluations, and linear regression model to estimate a driver's cognitive state when he/she drives a car in a virtual reality (VR)-based dynamic simulator. The driving error is defined as deviations between the center of the vehicle and the center of the cruising lane in the lane-keeping driving task. Experimental results demonstrate the feasibility of quantitatively estimating drowsiness level using ICA-based multistream EEG spectra. The proposed ICA-based method applied to power spectrum of ICA components can successfully (1) remove most of EEG artifacts, (2) suggest an optimal montage to place EEG electrodes, and estimate the driver's drowsiness fluctuation indexed by the driving performance measure. Finally, we present a benchmark study in which the accuracy of ICA-component-based alertness estimates compares favorably to scalp-EEG based.

Design and analysis of an adaptive transcutaneous power telemetry for biomedical implants

Abstract: Inductively coupled coil pair is the most common way of wirelessly transferring power to medical implants. However, the coil displacements and/or loading changes may induce large fluctuations in transmitted power into the implant if no adaptive control is used. In such cases, it is required to transmit excessive power to accommodate all the working conditions, which substantially reduces the power efficiency and imposes potential safety concerns. We have implemented a power transfer system with adaptive control technique to eliminate the power variations due to the loading or coupling coefficient changes. A maximum of 250mW power is transmitted through an optimized coil pair driven by Class-E power amplifier. Load shift keying is implemented to wirelessly transfer data back from the secondary to primary side over the same coil pair, with data rate of 3.3 kbps and packet error rate less than 10/sup -5/. A pseudo pulsewidth modulation has been designed to facilitate back data transmission along with forward power transmission. Through this back telemetry the system transmits the information on received power, back from implant to primary side. According to the data received, the system adjusts the supply voltage of the Class-E power amplifier through a digitally controlled dc-dc converter, thus varying the power sent to the implant. The key system parameters are optimized to ensure the stability of the closed-loop system. Measurements show that the system can transmit the 'just-needed' power for a wide range of coil separation and/or loading conditions, with power efficiency doubled when compared to the uncompensated link.

Block-LDPC: a practical LDPC coding system design approach

Abstract: This paper presents a joint low-density parity-check (LDPC) code-encoder-decoder design approach, called Block-LDPC, for practical LDPC coding system implementations. The key idea is to construct LDPC codes subject to certain hardware-oriented constraints that ensure the effective encoder and decoder hardware implementations. We develop a set of hardware-oriented constraints, subject to which a semi-random approach is used to construct Block-LDPC codes with good error-correcting performance. Correspondingly, we develop an efficient encoding strategy and a pipelined partially parallel Block-LDPC encoder architecture, and a partially parallel Block-LDPC decoder architecture. We present the estimation of Block-LDPC coding system implementation key metrics including the throughput and hardware complexity for both encoder and decoder. The good error-correcting performance of Block-LDPC codes has been demonstrated through computer simulations. With the effective encoder/decoder design and good error-correcting performance, Block-LDPC provides a promising vehicle for real-life LDPC coding system implementations.

Global exponential stability and periodicity of recurrent neural networks with time delays

Abstract: In this paper, the global exponential stability and periodicity of a class of recurrent neural networks with time delays are addressed by using Lyapunov functional method and inequality techniques. The delayed neural network includes the well-known Hopfield neural networks, cellular neural networks, and bidirectional associative memory networks as its special cases. New criteria are found to ascertain the global exponential stability and periodicity of the recurrent neural networks with time delays, and are also shown to be different from and improve upon existing ones.

Security of public-key cryptosystems based on Chebyshev polynomials

Abstract: Chebyshev polynomials have been recently proposed for designing public-key systems. Indeed, they enjoy some nice chaotic properties, which seem to be suitable for use in Cryptography. Moreover, they satisfy a semi-group property, which makes possible implementing a trapdoor mechanism. In this paper, we study a public-key cryptosystem based on such polynomials, which provides both encryption and digital signature. The cryptosystem works on real numbers and is quite efficient. Unfortunately, from our analysis, it comes up that it is not secure. We describe an attack which permits to recover the corresponding plaintext from a given ciphertext. The same attack can be applied to produce forgeries if the cryptosystem is used for signing messages. Then, we point out that also other primitives, a Diffie-Hellman like key agreement scheme and an authentication scheme, designed along the same lines of the cryptosystem, are not secure due to the aforementioned attack. We close the paper by discussing the issues and the possibilities of constructing public-key cryptosystems on real numbers.

Robust impulsive synchronization of uncertain dynamical networks

Abstract: This paper studies robust impulsive synchronization of uncertain dynamical networks. By utilizing the concept of impulsive control and the stability results for impulsive systems, several criteria for robust local and robust global impulsive synchronization are established for complex dynamical networks, in which the network coupling functions are unknown but bounded. Three examples are also worked through for illustrating the main results.

Design-oriented estimation of thermal noise in switched-capacitor circuits

Abstract: Thermal noise represents a major limitation on the performance of most electronic circuits. It is particularly important in switched circuits, such as the switched-capacitor (SC) filters widely used in mixed-mode CMOS integrated circuits. In these circuits, switching introduces a boost in the power spectral density of the thermal noise due to aliasing. Unfortunately, even though the theory of noise in SC circuits is discussed in the literature, it is very intricate. The numerical calculation of noise in switched circuits is very tedious, and requires highly sophisticated and not widely available software. The purpose of this paper is twofold. It provides a tutorial description of the physical phenomena taking place in an SC circuit while it processes noise (Sections II-III). It also proposes some specialized but highly efficient algorithms for estimating the resulting sampled noise in SC circuits, which need only simple calculations (Sections IV-VI ). A practical design procedure, which follows directly from the estimate, is also described. The accuracy of the proposed estimation algorithms is verified by simulation using SpectreRF. As an example, it is applied to the estimation of the total thermal noise in a second-order low-distortion delta-sigma converter.

An optimal design methodology for inductive power link with class-E amplifier

Abstract: This paper presents a design methodology of a highly efficient power link based on Class-E driven, inductively coupled coil pair. An optimal power link design for retinal prosthesis and/or other implants must take into consideration the allowable safety limits of magnetic fields, which in turn govern the inductances of the primary and secondary coils. In retinal prosthesis, the optimal coil inductances have to deal with the constraints of the coil sizes, the tradeoffs between the losses, H-field limitation and dc supply voltage required by the Class-E driver. Our design procedure starts with the formation of equivalent circuits, followed by the analysis of the loss of the rectifier and coils and the H-field for induced voltage and current. Both linear and nonlinear models for the analysis are presented. Based on the procedure, an experimental power link is implemented with an overall efficiency of 67% at the optimal distance of 7 mm between the coils. In addition to the coil design methodology, we are also presenting a closed-loop control of Class-E amplifier for any duty cycle and any value of the systemQ.

Design and analysis of switched-capacitor-based step-up resonant converters

Abstract: A switched-capacitor-based step-up resonant converter is proposed. The voltage conversion of the converters is in step-up mode. By adding a different number of switched-capacitor cells, different output voltage conversion ratios can be obtained. The voltage conversion ratio from 2 to any whole number can therefore be generated by these switching-capacitor techniques. A resonant tank is used to assist in zero-current switching hence the current spike, which usually exists for classical switched-capacitor can be eliminated. Both high-frequency operations and high efficiency are possible. Generalized analysis and design method of the converters are also presented. Experimental results verified the theoretical analysis.

Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation

Abstract: The successful realization of a wireless body area network (WBAN) requires innovative solutions to meet the energy consumption budget of the autonomous sensor nodes. The radio interface is a major challenge, since its power consumption must be reduced below 100 /spl mu/W (energy scavenging limit). The emerging ultra-wide-band (UWB) technology shows strong advantages in reaching this target. First, most of the complexity of an UWB system is in the receiver, which is a perfect scenario in the WBAN context. Second, the very little hardware complexity of a UWB transmitter offers the potential for low-cost and highly integrated solutions. Finally, in a pulse-based UWB scheme, the transmitter can be duty-cycled at the pulse rate, thereby reducing the baseline power consumption. We present a low-power UWB transmitter that can be fully integrated in standard CMOS technology. Measured performances of a fully integrated pulse generator are provided, showing the potential of UWB for low power and low cost implementations. Finally, using a WBAN channel model, we present a comparison between our UWB solution and state-of-the-art low-power narrow-band implementations. This paper shows that UWB performs better in the short range due to a reduced baseline power consumption.

A CMOS analog front-end IC for portable EEG/ECG monitoring applications

Abstract: A new digital programmable CMOS analog front-end (AFE) IC for measuring electroencephalograph or electrocardiogram signals in a portable instrumentation design approach is presented. This includes a new high-performance rail-to-rail instrumentation amplifier (IA) dedicated to the low-power AFE IC. The measurement results have shown that the proposed biomedical AFE IC, with a die size of 4.81 mm/sup 2/, achieves a maximum stable ac gain of 10 000 V/V, input-referred noise of 0.86 /spl mu/ V/sub rms/ (0.3 Hz-150 Hz), common-mode rejection ratio of at least 115 dB (0-1 kHz), input-referred dc offset of less than 60 /spl mu/V, input common mode range from -1.5 V to 1.3 V, and current drain of 485 /spl mu/A (excluding the power dissipation of external clock oscillator) at a /spl plusmn/1.5-V supply using a standard 0.5-/spl mu/m CMOS process technology.

T-S fuzzy controllers for nonlinear interconnected systems with multiple time delays

Abstract: This paper investigates the effectiveness of a passive tuned mass damper (TMD) and fuzzy controller in reducing the structural responses subject to the external force. In general, TMD is good for linear systems. We proposed here an approach of Takagi-Sugeno (T-S) fuzzy controller to deal with the nonlinear system. To overcome the effect of modeling error between nonlinear multiple time-delay systems and T-S fuzzy models, a robustness design of fuzzy control via model-based approach is proposed in this paper. A stability criterion in terms of Lyapunov's direct method is derived to guarantee the stability of nonlinear multiple time-delay interconnected systems. Based on the decentralized control scheme and this criterion, a set of model-based fuzzy controllers is then synthesized via the technique of parallel distributed compensation (PDC) to stabilize the nonlinear multiple time-delay interconnected system and the H/sup /spl infin// control performance is achieved at the same time. Finally, the proposed methodology is illustrated by an example of a nonlinear TMD system.

Hierarchical identification of lifted state-space models for general dual-rate systems

Abstract: This paper is motivated by practical consideration that the input updating and output sampling rates are often limited due to sensor and actuator speed constraints. In particular, for general dual-rate systems with different updating and sampling periods, we derive the lifted state-space models (mapping relations between available dual-rate input-output data), and, by using a hierarchical identification principle, present combined parameter and state estimation algorithms for identifying the canonical lifted models based on the given dual-rate input-output data, taking into account the causality constraints of the lifted systems. Finally, we give an illustrative example to indicate that the proposed algorithm is effective.

A model for /spl mu/-power rectifier analysis and design

Abstract: This paper proposes a linear two-port model for an N-stage modified-Greinacher full-wave rectifier. It predicts the overall conversion efficiency at low power levels where the diodes are operating near their threshold voltage. The output electrical behavior of the rectifier is calculated as a function of the received power and the antenna parameters. Moreover, the two-port parameter values are computed for particular input voltages and output currents for the complete N-stage rectifier circuit using only the measured I-V and C-V characteristics of a single diode. To validate the model a three-stage modified-Greinacher full-wave rectifier was realized in an silicon-on-sapphire (SOS) CMOS 0.5-/spl mu/m technology. The measurements are in excellent agreement with the values calculated using the presented model.

A fully integrated low-power BPSK demodulator for implantable medical devices

Abstract: During the past decades, research has progressed on the biomedical implantable electronic devices that require power and data communication through wireless inductive links. In this paper, we present a fully integrated binary phase-shift keying (BPSK) demodulator, which is based on a hard-limited COSTAS loop topology, dedicated to such implantable medical devices. The experimental results of the proposed demodulator show a data transmission rate of 1.12 Mbps, less than 0.7 mW consumption under a supply voltage of 1.8 V, and silicon area of 0.2 mm/sup 2/ in the Taiwan Semiconductor Manufacturing Company (TSMC) CMOS 0.18-/spl mu/m technology. The transmitter satisfies the requirement of applications relative to high forward-transferring data rate, such as cortical stimulation. Moreover, the employment of BPSK demodulation along with a passive modulation method allows full-duplex data communication between an external controller and the implantable device, which may improve the controllability and observability of the overall implanted system.

A general-purpose processor-per-pixel analog SIMD vision chip

Abstract: A smart-sensor VLSI circuit suitable for focal-plane low-level image processing applications is presented. The architecture of the device is based on a fine-grain software-programmable SIMD processor array. Processing elements, integrated within each pixel of the imager, are implemented utilising a switched-current analog microprocessor concept. This allows the achievement of real-time image processing speeds with high efficiency in terms of silicon area and power dissipation. The prototype 21 /spl times/ 21 vision chip is fabricated in a 0.6 /spl mu/m CMOS technology and achieves a cell size of 98.6 /spl mu/m /spl times/ 98.6 /spl mu/m. It executes over 1.1 giga instructions per second (GIPS) while dissipating under 40 mW of power. The architecture, circuit design and experimental results are presented in this paper.

Design and implementation of n-scroll chaotic attractors from a general jerk circuit

Abstract: This paper proposes a novel nonlinear modulating function approach for generating n-scroll chaotic attractors based on a general jerk circuit. The systematic nonlinear modulating function methodology developed here can arbitrarily design the swings, widths, slopes, breakpoints, equilibrium points, shapes, and even the general phase portraits of the n-scroll chaotic attractors by using the adjustable sawtooth wave, triangular wave, and transconductor wave functions. The dynamic mechanism and chaos generation condition of the general jerk circuit are further investigated by analyzing the system stability. A simple block circuit diagram, including integrator, sawtooth wave and triangular wave generators, buffer, switch linkages, and voltage-current conversion resistors, is designed for the hardware implementations of various 3-12-scroll chaotic attractors via switchings of the switch linkages. This is the first time to experimentally verify a 12-scroll chaotic attractor generated by an analog circuit. In particular, the recursive formulas of system parameters and real physical circuit parameters are rigorously derived for the hardware implementations of the n-scroll chaotic attractors. Moreover, the adjustability of the nonlinear modulating function and the rigorous recursive formulas together provide a theoretical principle for the hardware implementations of various chaotic attractors with a large number of scrolls.

Fault detection and diagnosis for general stochastic systems using B-spline expansions and nonlinear filters

Abstract: This paper presents a new fault detection and diagnosis (FDD) algorithm for general stochastic systems Different from the classical FDD design, the distribution of system output is supposed to be measured rather than the output signal itself The task of such an FDD algorithm design is to use the measured output probability density functions (PDFs) and the input of the system to construct a stable filter-based residual generator such that the fault can be detected and diagnosed For this purpose, square root B-spline expansions are applied to model the output PDFs and the concerned problem is transformed into a nonlinear FDD algorithm design subjected to a nonlinear weight dynamical system A linear matrix inequality based solution is presented such that the estimation error system is stable and the fault can be detected through a threshold Moreover, an adaptive fault diagnosis method is also provided to estimate the size of the fault Simulations are provided to show the efficiency of the proposed approach

A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs

Abstract: The use of bang-bang phase-locked loops (BBPLLs) has become increasingly common in a lot of communications systems, in particular in the area of clock and data recovery. Although most of the BBPLLs implemented up to now use analog loop filters, the binary output of the phase detector naturally lends itself to a digital implementation. In this paper, the nonlinear dynamics of first- and second-order digital BBPLLs is analyzed from a design perspective. In particular, the effects of loop delays on the PLL performances are emphasized. Conditions for the existence of orbits (limit cycles) are derived, and the timing jitter performances are evaluated. Finally, useful expressions for the design and optimization of the PLL parameters for low jitter are given.

A bio-physically inspired silicon neuron

Abstract: The physical principles governing ion flow in biological neurons share interesting similarities to electron flow through the channels of MOSFET transistors. Here, is described a circuit which exploits the similarities better than previous approaches to build an elegant circuit with electrical properties similar to real biological neurons. A two-channel model is discussed including sodium (Na/sup +/) and potassium (K/sup +/). The Na/sup +/ channel uses four transistors and two capacitors. The K/sup +/ channel uses two transistors and one capacitor. One more capacitor simulates the neuron membrane capacitance yielding a total circuit of four capacitors and six transistors. This circuit operates in real-time, is fabricated on standard CMOS processes, runs in subthreshold, and has a power supply similar to that of real biology. Voltage and current responses of this circuit correspond well with biology in terms of shape, magnitude, and time.

Modeling the closed-current loop of PWM boost DC-DC converters operating in CCM with peak current-mode control

Abstract: This paper derives the transfer function from error voltage to duty cycle, which captures the quasi-digital behavior of the closed-current loop for pulsewidth modulated (PWM) dc-dc converters operating in continuous-conduction mode (CCM) using peak current-mode (PCM) control, the current-loop gain, the transfer function from control voltage to duty cycle (closed-current loop transfer function), and presents experimental verification. The sample-and-hold effect, or quasi-digital (discrete) behavior in the current loop with constant-frequency PCM in PWM dc-dc converters is described in a manner consistent with the physical behavior of the circuit. Using control theory, a transfer function from the error voltage to the duty cycle that captures the quasi-digital behavior is derived. This transfer function has a pole that can be in either the left-half plane or right-half plane, and captures the sample-and-hold effect accurately, enabling the characterization of the current-loop gain and closed-current loop for PWM dc-dc converters with PCM. The theoretical and experimental response results were in excellent agreement, confirming the validity of the transfer functions derived. The closed-current loop characterization can be used for the design of a controller for the outer voltage loop.

LMS adaptive filters using distributed arithmetic for high throughput

Abstract: We present a new hardware adaptive filter architecture for very high throughput LMS adaptive filters using distributed arithmetic (DA). DA uses bit-serial operations and look-up tables (LUTs) to implement high throughput filters that use only about one cycle per bit of resolution regardless of filter length. However, building adaptive DA filters requires recalculating the LUTs for each adaptation which can negate any performance advantages of DA filtering. By using an auxiliary LUT with special addressing, the efficiency and throughput of DA adaptive filters can be of the same order as fixed DA filters. In this paper, we discuss a new hardware adaptive filter structure for very high throughput LMS adaptive filters. We describe the development of DA adaptive filters and show that practical implementations of DA adaptive filters have very high throughput relative to multiply and accumulate architectures. We also show that DA adaptive filters have a potential area and power consumption advantage over digital signal processing microprocessor architectures.

Neuromorphic implementation of orientation hypercolumns

Abstract: Neurons in the mammalian primary visual cortex are selective along multiple stimulus dimensions, including retinal position, spatial frequency, and orientation. Neurons tuned to different stimulus features but the same retinal position are grouped into retinotopic arrays of hypercolumns. This paper describes a neuromorphic implementation of orientation hypercolumns, which consists of a single silicon retina feeding multiple chips, each of which contains an array of neurons tuned to the same orientation and spatial frequency, but different retinal locations. All chips operate in continuous time, and communicate with each other using spikes transmitted by the address-event representation protocol. This system is modular in the sense that orientation coverage can be increased simply by adding more chips, and expandable in the sense that its output can be used to construct neurons tuned to other stimulus dimensions. We present measured results from the system, demonstrating neuronal selectivity along position, spatial frequency and orientation. We also demonstrate that the system supports recurrent feedback between neurons within one hypercolumn, even though they reside on different chips. The measured results from the system are in excellent concordance with theoretical predictions.

Event-driven Simulation and modeling of phase noise of an RF oscillator

Abstract: A novel simulation technique that uses an event-driven VHDL simulator to model phase noise behavior of an RF oscillator for wireless applications is proposed and demonstrated. The technique is well suited to investigate complex interactions in large system-on-chip systems, where traditional RF and analog simulation tools do not work effectively. The oscillator phase noise characteristic comprising of flat electronic noise, as well as, upconverted thermal and 1/f noise regions are described using time-domain equations and simulated as either accumulative or nonaccumulative random perturbations of the fundamental oscillator period. The VHDL simulation environment was selected for its high simulation speed, the direct correlation between the simulated and built circuits and its ability to model mixed-signal systems of high complexity. The presented simulation technique has been successfully applied and validated in a Bluetooth transceiver integrated circuit fabricated in a digital 130-nm process.

A generic approach to the theory of superregenerative reception

Abstract: The superregenerative receiver has been widely used for many decades in short-range wireless communications because of its relative simplicity, reduced cost, and low power consumption. However, the theory that describes the behavior of this type of receiver, which was mainly developed prior to 1950, is of limited scope, since it applies to particular implementations, usually operating under continuous-wave signal or narrow-band modulation. As a novelty, we present the theory of superregenerative reception from a generic point of view. We develop an analytic study based on a generic block diagram of the receiver and consider not only narrow-band, but a wider variety of input signals. The study allows general results and conclusions that can be easily particularized to specific implementations to be obtained. Starting from the proposed model, the differential equation that describes the operation of the receiver in the linear mode is deducted and solved. Normalized parameters and functions characterizing the performance of the receiver are presented, as well as the requirements for proper operation. Several characteristic phenomena, such as hangover and multiple resonance, are described. The nonlinear behavior of the active device is also modeled to obtain a solution of the differential equation in the logarithmic mode of operation. The study is completed with a practical example operating at 2.4 GHz and illustrating the typical performance of a superregenerative receiver.

Performance bounds of forgetting factor least-squares algorithms for time-varying systems with finite measurement data

Abstract: This paper on performance analysis of parameter estimation is motivated by a practical consideration that the data length is finite. In particular, for time-varying systems, we study the properties of the well-known forgetting factor least-squares (FFLS) algorithm in detail in the stochastic framework, and derive upperbounds and lowerbounds of the parameter estimation errors (PEE), using directly the finite input-output data. The analysis indicates that the mean square PEE upperbounds and lowerbounds of the FFLS algorithm approach two finite positive constants, respectively, as the data length increases, and that these PEE upperbounds can be minimized by choosing appropriate forgetting factors. We further show that for time-invariant systems, the PEE upperbounds and lowerbounds of the ordinary least-squares algorithm both tend to zero as the data length increases. Finally, we illustrate and verify the theoretical findings with several example systems, including an experimental water-level system.

A new two-stage sharpened comb decimator

Abstract: This paper presents a new sharpened comb decimator structure consisting of a cascade of a comb-filter based decimator and a sharpened comb decimator. The proposed realization scheme allows the sharpened section to operate at a lower rate that depends on the decimation factor of the first section. Using a polyphase decomposition, the subfilters of the first section can also be operated at this lower rate.

New continuous-flow mixed-radix (CFMR) FFT Processor using novel in-place strategy

Abstract: The paper proposes a new continuous-flow mixed-radix (CFMR) fast Fourier transform (FFT) processor that uses the MR (radix-4/2) algorithm and a novel in-place strategy. The existing in-place strategy supports only a fixed-radix FFT algorithm. In contrast, the proposed in-place strategy can support the MR algorithm, which allows CF FFT computations regardless of the length of FFT. The novel in-place strategy is made by interchanging storage locations of butterfly outputs. The CFMR FFT processor provides the MR algorithm, the in-place strategy, and the CF FFT computations at the same time. The CFMR FFT processor requires only two N-word memories due to the proposed in-place strategy. In addition, it uses one butterfly unit that can perform either one radix-4 butterfly or two radix-2 butterflies. The CFMR FFT processor using the 0.18 /spl mu/m SEC cell library consists of 37,000 gates excluding memories, requires only 640 clock cycles for a 512-point FFT and runs at 100 MHz. Therefore, the CFMR FFT processor can reduce hardware complexity and computation cycles compared with existing FFT processors.