Showing papers in "IEEE Transactions on Circuits and Systems I-regular Papers in 2006"
TL;DR: A nonlinear model for genetic regulatory networks with SUM regulatory functions with linear matrix inequalities is presented and it is shown that the genetic network can be transformed into Lur'e form.
Abstract: In this paper, we present a nonlinear model for genetic regulatory networks with SUM regulatory functions. We show that the genetic network can be transformed into Lur'e form. Based on the Lyapunov method and the Lur'e system approach, sufficient conditions for the stability of the genetic networks are derived, in particular for the cases with time delays owing to the slow processes of transcription, translation, and translocation, and for the cases with stochastic perturbations due to natural random intra- and inter-cellular fluctuations. All the stability conditions are given in terms of linear matrix inequalities (LMIs), which are very easy to be verified. To test the effectiveness of our theoretical results, several examples of genetic networks are also presented in this paper
310 citations
TL;DR: A simple unified approach to the design of fixed-frequency pulsewidth-modulation-based sliding-mode controllers for dc-dc converters operating in the continuous conduction mode is presented.
Abstract: This paper presents a simple unified approach to the design of fixed-frequency pulsewidth-modulation-based sliding-mode controllers for dc-dc converters operating in the continuous conduction mode. The design methodology is illustrated on the three primary dc-dc converters: buck, boost, and buck-boost converters. To illustrate the feasibility of the scheme, an experimental prototype of the derived boost controller/converter system is developed. Several tests are performed to validate the functionalities of the system
289 citations
TL;DR: Some simple yet generic criteria ensuring delay-independent and delay-dependent synchronization are derived, which are less conservative than those reported so far in the literature.
Abstract: This paper investigates synchronization dynamics of a general model of complex delayed networks as well as the effects of time delays. Some simple yet generic criteria ensuring delay-independent and delay-dependent synchronization are derived, which are less conservative than those reported so far in the literature. Moreover, a scale "nu" denoted by a function of the smallest and the second largest eigenvalues of coupling matrix is presented to analyze the effects of time delays on synchronization of the networks. Furthermore, various kinds of coupling schemes, including small-world networks and scale-free networks, are studied. It is shown that, if the coupling delays are less than a positive threshold, then the network will be synchronized. On the other hand, with the increase of the coupling delays, the synchronizability of the network will be restrained and even eventually desynchronized. The results are illustrated by a prototype composed of the chaotic Duffing oscillators. Numerical simulations are also given to verify theoretical results
269 citations
TL;DR: Two hardware architectures are proposed that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches and an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation is proposed.
Abstract: Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory
269 citations
TL;DR: This result uses a Riccati-type Lyapunov functional under a condition on the time delay to stabilize a switching system composed of a finite number of linear delay differential equations.
Abstract: We consider a switching system composed of a finite number of linear delay differential equations (DDEs). It has been shown that the stability of a switching system composed of a finite number of linear ordinary differential equations (ODEs) may be achieved by using a common Lyapunov function method switching rule. We modify this switching rule for ODE systems to a common Lyapunov functional method switching rule for DDE systems and show that it stabilizes our model. Our result uses a Riccati-type Lyapunov functional under a condition on the time delay.
267 citations
TL;DR: This paper presents the design and demonstration of a variable-capacitance vibration energy harvester that combines an asynchronous diode-based charge pump with an inductive energy flyback circuit to deliver 1.8 /spl mu/W to a resistive load.
Abstract: Past research on vibration energy harvesting has focused primarily on the use of magnets or piezoelectric materials as the basis of energy transduction, with few experimental studies implementing variable-capacitance-based scavenging. In contrast, this paper presents the design and demonstration of a variable-capacitance vibration energy harvester that combines an asynchronous diode-based charge pump with an inductive energy flyback circuit to deliver 1.8 /spl mu/W to a resistive load. A cantilever beam variable capacitor with a 650-pF dc capacitance and a 348-pF zero-to-peak ac capacitance, formed by a 43.56cm/sup 2/ spring steel top plate attached to an aluminum base, drives the charge pump at its out-of-plane resonant frequency of 1.56 kHz. The entire harvester requires only one gated MOSFET for energy flyback control, greatly simplifying the clocking scheme and avoiding synchronization issues. Furthermore, the system exhibits a startup voltage requirement below 89 mV, indicating that it can potentially be turned on using just a piezoelectric film.
239 citations
TL;DR: A systematic methodology for circuit design is proposed for experimental verification of multidirectional multiscroll chaotic attractors, including one-directional (1-D) n-scroll, 2-D n/spl times/m-grid scroll, and 3-D w/o times/l-gridscroll chaotic attractor, useful for future circuitry design and engineering applications.
Abstract: A systematic methodology for circuit design is proposed for experimental verification of multidirectional multiscroll chaotic attractors, including one-directional (1-D) n-scroll, 2-D n/spl times/m-grid scroll, and 3-D n/spl times/m/spl times/l-grid scroll chaotic attractors. Two typical cases are investigated in detail: the hysteresis and saturated multiscroll chaotic attractors. A simple blocking circuit diagram is designed for experimentally verifying 1-D 5/spl sim/11-scroll, 2-D 3/spl times/5/spl sim/11-grid scroll, and 3-D 3/spl times/3/spl times/5/spl sim/11-grid scroll hysteresis chaotic attractors by manipulating the switchers. Moreover, a block circuitry is also designed for physically realizing 1-D 10, 12, 14-scroll, 2-D 10, 12, 14/spl times/10-grid scroll, and 3-D 10/spl times/10/spl times/10-grid scroll saturated chaotic attractors via switching. In addition, one can easily realize chaotic attractors with a desired odd number of scrolls by slightly modifying the corresponding voltage saturated function series of the circuit, to produce for instance a 1-D 13-scroll saturated chaotic attractor. This is the first time in the literature to report an experimental verification of a 1-D 14-scroll, a 2-D 14/spl times/10-grid scroll and a 3-D 10/spl times/10/spl times/10-grid (totally 1000) scroll chaotic attractors. Only the 3-D case is reported in detail for simplicity of presentation. It is well known that hardware implementation of 1-D n-scroll with n/spl ges/10, 2-D n/spl times/m-grid scroll with n,m/spl ges/10, and 3-D n/spl times/m/spl times/l-grid scroll with n,m,l/spl ges/10 chaotic attractors is very difficult technically, signifying the novelty and significance of the achievements reported in this paper. Finally, this circuit design approach provides some principles and guidelines for hardware implementation of chaotic attractors with a multidirectional orientation and with a large number of scrolls, useful for future circuitry design and engineering applications.
190 citations
TL;DR: A new CMOS high-performance electronically tunable second-generation current conveyor (ECCII) is presented that realizes low-pass, bandpass, and high-pass responses simultaneously and can be independently tuned by changing the current gain of the relevant CC.
Abstract: In this paper, a new CMOS high-performance electronically tunable second-generation current conveyor (ECCII) is presented. The current gain of the proposed ECCII can be controlled electronically by adjusting the ratio of dc bias currents of the ECCII. The output terminal of the proposed ECCII has high impedance, which enables easy cascadability. Also, as an application, the proposed ECCII is used for realizing a universal current-mode filter. The filter realizes low-pass, bandpass, and high-pass responses simultaneously. The low-pass response is obtained at high impedance output and its gain can be independently tuned by changing the current gain of the relevant CC. SPICE simulation results using TSMC 0.35-/spl mu/m CMOS process model shows excellent performance for the proposed ECCII. The proposed circuit consumes average power of 6.6 mW using /spl plusmn/1.5-V supply voltages.
184 citations
TL;DR: A unified analysis of the relationships between time-domain jitter and various spectral characterizations of phase noise is presented and practical results on computing jitter from spectral phase noise characteristics for oscillators and PLLs with both white (thermal, shot) and 1/f noise are presented.
Abstract: Phase noise and timing jitter in oscillators and phase-locked loops (PLLs) are of major concern in wireless and optical communications. In this paper, a unified analysis of the relationships between time-domain jitter and various spectral characterizations of phase noise is first presented. Several notions of phase noise spectra are considered, in particular, the power-spectral density (PSD) of the excess phase noise, the PSD of the signal generated by a noisy oscillator/PLL, and the so-called single-sideband (SSB) phase noise spectrum. We investigate the origins of these phase noise spectra and discuss their mathematical soundness. A simple equation relating the variance of timing jitter to the phase noise spectrum is derived and its mathematical validity is analyzed. Then, practical results on computing jitter from spectral phase noise characteristics for oscillators and PLLs with both white (thermal, shot) and 1/f noise are presented. We are able to obtain analytical timing jitter results for free-running oscillators and first-order PLLs. A numerical procedure is used for higher order PLLs. The phase noise spectrum needed for computing jitter may be obtained from analytical phase noise models, oscillator or PLL noise analysis in a circuit simulator, or from actual measurements
177 citations
TL;DR: A gain control mechanism is introduced for the first time in the proposed design by varying the biasing current of the gain stage without influencing the other figures of merit of the circuit so as to accommodate the UWB LNA in various UWB wireless transmission systems with different link budgets.
Abstract: An ultra-wideband (UWB) 3.1- to 10.6-GHz low-noise amplifier (LNA) employing a common-gate stage for wideband input matching is presented in this paper. Designed in a commercial 0.18-mum 1.8-V standard RFCMOS technology, the proposed UWB LNA achieves fully on-chip circuit implementation, contributing to the realization of a single-chip CMOS UWB receiver. The proposed UWB LNA achieves 16.7plusmn0.8 dB power gain with a good input match (S11<-9 dB) over the 7500-MHz bandwidth (from 3.1 GHz to 10.6 GHz), and an average noise figure of 4.0 dB, while drawing 18.4-mA dc biasing current from the 1.8-V power supply. A gain control mechanism is also introduced for the first time in the proposed design by varying the biasing current of the gain stage without influencing the other figures of merit of the circuit so as to accommodate the UWB LNA in various UWB wireless transmission systems with different link budgets
163 citations
TL;DR: The proposed scheme is effective in achieving the expected chaos synchronization in the complex network and can be transformed to a linear matrix inequality and easily solved by a numerical toolbox.
Abstract: In this paper, a new approach for synchronization of complex dynamical networks is proposed based on state observer design. Unlike the common diagonally coupling networks, where full state coupling is typically needed between two nodes, here it is suggested that only a scalar coupling signal is required to achieve network synchronization. Some conditions for synchronization, in the form of an inequality, are established based on the Lyapunov stability theory, which can be transformed to a linear matrix inequality and easily solved by a numerical toolbox. Two typical dynamical network configurations, i.e., global coupling and nearest-neighbor coupling, with each node being a modified Chua's circuit, are simulated. It is demonstrated that the proposed scheme is effective in achieving the expected chaos synchronization in the complex network
TL;DR: An adaptive alertness estimation methodology based on electroencephalogram, power spectrum analysis, independent component analysis (ICA), and fuzzy neural network (FNNs) models is proposed in this paper for continuously monitoring driver's drowsiness level with concurrent changes in the alertness level.
Abstract: Drivers' fatigue has been implicated as a causal factor in many accidents. The development of human cognitive state monitoring system for the drivers to prevent accidents behind the steering wheel has become a major focus in the field of safety driving. It requires a technique that can continuously monitor and estimate the alertness level of drivers. The difficulties in developing such a system are lack of significant index for detecting drowsiness and the interference of the complicated noise in a realistic and dynamic driving environment. An adaptive alertness estimation methodology based on electroencephalogram, power spectrum analysis, independent component analysis (ICA), and fuzzy neural network (FNNs) models is proposed in this paper for continuously monitoring driver's drowsiness level with concurrent changes in the alertness level. A novel adaptive feature selection mechanism is developed for automatically selecting effective frequency bands of ICA components for realizing an on-line alertness monitoring system based on the correlation analysis between the time-frequency power spectra of ICA components and the driving errors defined as the deviation between the center of the vehicle and the cruising lane in the virtual-reality driving environment. The mechanism also provides effective and efficient features that can be fed into ICA-mixture-model-based self-constructing FNN to indirectly estimate driver's drowsiness level expressed by approximately and predicting the driving error
TL;DR: An all-CMOS variable gain amplifier (VGA) that adopts a new approximated exponential equation is presented, characterized by a wide range of gain variation, temperature-independence gain characteristic, low-power consumption, small chip size, and controllable dynamic gain range.
Abstract: An all-CMOS variable gain amplifier (VGA) that adopts a new approximated exponential equation is presented. The proposed VGA is characterized by a wide range of gain variation, temperature-independence gain characteristic, low-power consumption, small chip size, and controllable dynamic gain range. The two-stage VGA is fabricated in 0.18-mum CMOS technology and shows the maximum gain variation of more than 95 dB and a 90-dB linear range with linearity error of less than plusmn 1 dB. The range of gain variation can be controlled from 68 to 95 dB. The P1dB varies from - 48 to - 17 dBm, and the 3-dB bandwidth is from 32 MHz (at maximum gain of 43 dB) to 1.05 GHz (at minimum gain of - 52 dB). The VGA dissipates less than 3.6 mA from 1.8-V supply while occupying 0.4 mm2 of chip area excluding bondpads
TL;DR: A generalized predictive control method based on self-recurrent wavelet neural network (SRWNN) is proposed for stable path tracking of mobile robots and the ALRs for training the parameters of the SRWNN identifier are derived from the discrete Lyapunov stability theorem, which are used to guarantee the convergence of the GPC system.
Abstract: In this paper, a generalized predictive control (GPC) method based on self-recurrent wavelet neural network (SRWNN) is proposed for stable path tracking of mobile robots. Since the SRWNN has a self-recurrent mother wavelet layer, it can well attract the complex nonlinear system although the SRWNN has less mother wavelet nodes than the wavelet neural network. Thus, the SRWNN is used as a model identifier for approximating on-line the states of the mobile robot. In our control system, since the control inputs, as well as the parameters of the SRWNN identifier are trained by the gradient descent method with the adaptive learning rates (ALRs), the optimal learning rates which are suitable for the time-varying trajectory of the mobile robot can be found rapidly. The ALRs for training the parameters of the SRWNN identifier and those for learning the control inputs are derived from the discrete Lyapunov stability theorem, which are used to guarantee the convergence of the GPC system. Finally, simulation results are provided to demonstrate the effectiveness of the proposed control strategy
TL;DR: The power efficiency of a RF Class-D amplifier with a bandpass sigma-delta (SigmaDeltaM) modulator is analyzed for a complementary voltage-switched configuration and results show a drain efficiency of 52% with a 10-dB peak-to-average power ratio W-CDMA source signal at a frequency of 500 MHz.
Abstract: The power efficiency of a RF Class-D amplifier with a bandpass sigma-delta (SigmaDeltaM) modulator is analyzed for a complementary voltage-switched configuration. The modulator broadens the application of the amplifier to include signals with time varying envelopes such as W-CDMA. The addition of a modulator introduces new design variables which affect amplifier power efficiency including coding efficiency and the average transition frequency of the pulse train. Design equations are derived for the optimum load impedance, output power, conduction losses, capacitive switching losses, and drain efficiency. The general design equations are consistent with both periodic and aperiodic drive signals. Analytic and simulated results are compared for an example design with pseudomorphic high-electron mobility transistor and metal-semiconductor field-effect transistor switches with a fourth-order bandpass SigmaDeltaM. The results show a drain efficiency of 52% with a 10-dB peak-to-average power ratio W-CDMA source signal at a frequency of 500 MHz
TL;DR: A novel hardware architecture for elliptic curve cryptography (ECC) over GF(p) is introduced, based on a new unified modular inversion algorithm that offers considerable improvement over previous ECC techniques that use Fermat's Little Theorem for this operation.
Abstract: A novel hardware architecture for elliptic curve cryptography (ECC) over GF(p) is introduced. This can perform the main prime field arithmetic functions needed in these cryptosystems including modular inversion and multiplication. This is based on a new unified modular inversion algorithm that offers considerable improvement over previous ECC techniques that use Fermat's Little Theorem for this operation. The processor described uses a full-word multiplier which requires much fewer clock cycles than previous methods, while still maintaining a competitive critical path delay. The benefits of the approach have been demonstrated by utilizing these techniques to create a field-programmable gate array (FPGA) design. This can perform a 256-bit prime field scalar point multiplication in 3.86 ms, the fastest FPGA time reported to date. The ECC architecture described can also perform four different types of modular inversion, making it suitable for use in many different ECC applications
TL;DR: The theoretical and experimental results were in good agreement, confirming the validity of the transfer functions derived, and the closed-loop transfer function from reference voltage to output voltage.
Abstract: A new transfer function from control voltage to duty cycle, the closed-current loop, which captures the natural sampling effect is used to design a controller for the voltage-loop of a pulsewidth modulated (PWM) dc-dc converter operating in continuous-conduction mode (CCM) with peak current-mode control (PCM). This paper derives the voltage loop gain and the closed-loop transfer function from reference voltage to output voltage. The closed-loop transfer function from the input voltage to the output voltage, or the closed-loop audio-susceptibility is derived. The closed-loop transfer function from output current to output voltage, or the closed loop output impedance is also derived. The derivation is performed using an averaged small-signal model of the example boost converter for CCM. Experimental verification is presented. The theoretical and experimental results were in good agreement, confirming the validity of the transfer functions derived.
TL;DR: Global robust convergence properties of continuous-time neural networks with discrete delays are studied and a set of delay-independent sufficient conditions for the existence, uniqueness, and global robust asymptotic stability of the equilibrium point are derived.
Abstract: Global robust convergence properties of continuous-time neural networks with discrete delays are studied. By employing suitable Lyapunov functionals, we derive a set of delay-independent sufficient conditions for the existence, uniqueness, and global robust asymptotic stability of the equilibrium point. The conditions can be easily verified as they can be expressed in terms of the network parameters only. Some numerical examples are given to compare our results with previous robust stability results derived in the literature. One of our main results is shown to improve and generalize a previously published result. Other results proved to establish a new set of robust stability criteria for delayed neural networks.
TL;DR: Low-pass filtering the ADC subchannels to this alias-free band reduces the blind calibration problem to a conventional gain and time delay estimation problem for an unknown signal in noise.
Abstract: In this paper, we describe a blind calibration method for gain and timing mismatches in a two-channel time-interleaved low-pass analog-to-digital converters (ADC). The method requires that the input signal should be slightly oversampled. This ensures that there exists a frequency band around the zero frequency where the Fourier transforms of the ADC subchannels are alias free. Low-pass filtering the ADC subchannels to this alias-free band reduces the blind calibration problem to a conventional gain and time delay estimation problem for an unknown signal in noise. An adaptive filtering structure with three fixed FIR filters and two adaptive gain and delay parameters is employed to achieve the calibration. A convergence analysis is presented for the blind calibration technique. Numerical simulations for a bandlimited white noise input and for inputs containing several sinusoidal components demonstrate the effectiveness of the proposed method
TL;DR: A neuromorphic cortical-layer processing microchip for address event representation (AER) spike-based processing systems that computes convolutions of programmable kernels over the AER visual input information flow and allows for a bio-inspired coincidence detection processing.
Abstract: We present a neuromorphic cortical-layer processing microchip for address event representation (AER) spike-based processing systems. The microchip computes 2-D convolutions of video information represented in AER format in real time. AER, as opposed to conventional frame-based video representation, describes visual information as a sequence of events or spikes in a way similar to biological brains. This format allows for fast information identification and processing, without waiting to process complete image frames. The neuromorphic cortical-layer processing microchip presented in this paper computes convolutions of programmable kernels over the AER visual input information flow. It not only computes convolutions but also allows for a programmable forgetting rate, which in turn allows for a bio-inspired coincidence detection processing. Kernels are programmable and can be of arbitrary shape and arbitrary size of up to 32 times 32 pixels. The convolution processor operates on a pixel array of size 32 times 32, but can process an input space of up to 128 times 128 pixels. Larger pixel arrays can be directly processed by tiling arrays of chips. The chip receives and generates data in AER format, which is asynchronous and digital. However, its internal operation is based on analog low-current circuit techniques. The paper describes the architecture of the chip and circuits used for the pixels, including calibration techniques to overcome mismatch. Extensive experimental results are provided, describing pixel operation and calibration, convolution processing with and without forgetting, and high-speed recognition experiments like discriminating rotating propellers of different shape rotating at speeds of up to 5000 revolutions per second
TL;DR: In this paper, the authors analyzed the complete stability of cellular neural networks with time-varying delays using the induction method and the contraction mapping principle and obtained delay-dependent and delay-independent conditions for locally stable equilibrium points to be located anywhere.
Abstract: In this paper, the complete stability of cellular neural networks with time-varying delays is analyzed using the induction method and the contraction mapping principle. Delay-dependent and delay-independent conditions are obtained for locally stable equilibrium points to be located anywhere, which differ from the existing results on complete stability where the existence of equilibrium points in the saturation region is necessary for complete stability and locally stable equilibrium points can be in the saturation region only. In addition, some existing stability results in the literature are special cases of a new result herein. Simulation results are also discussed by use of two illustrative examples.
TL;DR: A background calibration technique is presented that digitally measures and cancels ADC error arising from distortion introduced by the residue amplifiers, thereby significantly reducing overall power consumption relative to conventional pipelined ADCs.
Abstract: Pipelined analog-to-digital converters (ADCs) are sensitive to distortion introduced by the residue amplifiers in their first few stages. Unfortunately, residue amplifier distortion tends to be inversely related to power consumption in practice, so the residue amplifiers usually are the dominant consumers of power in high-resolution pipelined ADCs. This paper presents a background calibration technique that digitally measures and cancels ADC error arising from distortion introduced by the residue amplifiers. It allows the use of higher distortion and, therefore, lower power residue amplifiers in high-accuracy pipelined ADCs, thereby significantly reducing overall power consumption relative to conventional pipelined ADCs
TL;DR: It is shown that despite its lack of stationarity it is possible to derive a closed form expression for its effect on an oscillator PSD and that the oscillator output can be considered to be wide-sense stationary.
Abstract: In this paper, we apply correlation theory methods to obtain a model for the near-carrier oscillator power-spectral density (PSD). Based on the measurement-driven representation of phase noise as a sum of power-law processes, we evaluate closed form expressions for the relevant oscillator autocorrelation functions. These expressions form the basis of an enhanced oscillator spectral model that has a Gaussian PSD at near-carrier frequencies followed by a sequence of power-law regions. New results for the effect of white phase noise, flicker phase noise and random walk frequency modulated phase noise on the near-carrier oscillator PSD are derived. In particular, in the case of 1/f phase noise, we show that despite its lack of stationarity it is possible to derive a closed form expression for its effect on an oscillator PSD and show that the oscillator output can be considered to be wide-sense stationary
TL;DR: This paper presents a fully automated recurrent neural network (FARNN) that is capable of self-structuring its network in a minimal representation with satisfactory performance for unknown dynamic system identification and control.
Abstract: This paper presents a fully automated recurrent neural network (FARNN) that is capable of self-structuring its network in a minimal representation with satisfactory performance for unknown dynamic system identification and control. A novel recurrent network, consisting of a fully-connected single-layer neural network and a feedback interconnected dynamic network, was developed to describe an unknown dynamic system as a state-space representation. Next, a fully automated construction algorithm was devised to construct a minimal state-space representation with the essential dynamics captured from the input-output measurements of the unknown system. The construction algorithm integrates the methods of minimal model determination, parameter initialization and performance optimization into a systematic framework that totally exempt trial-and-error processes on the selections of network sizes and parameters. Computer simulations on benchmark examples of unknown nonlinear dynamic system identification and control have successfully validated the effectiveness of the proposed FARNN in constructing a parsimonious network with superior performance
TL;DR: A chaotic Feistel cipher and a chaotic uniform cipher are proposed to examine crypto components from both dynamical-system and cryptographical points of view, thus to explore connection between these two fields.
Abstract: Digital chaotic ciphers have been investigated for more than a decade. However, their overall performance in terms of the tradeoff between security and speed, as well as the connection between chaos and cryptography, has not been sufficiently addressed. We propose a chaotic Feistel cipher and a chaotic uniform cipher. Our plan is to examine crypto components from both dynamical-system and cryptographical points of view, thus to explore connection between these two fields. In the due course, we also apply dynamical system theory to create cryptographically secure transformations and evaluate cryptographical security measures
TL;DR: The focus of the work presented in this paper has been to incorporate recent results of chaos theory, proven to be cryptographically secure, into arithmetic coding, to devise a convenient method to make the structure of the model unpredictable and variable in nature, and yet to retain, as far as is possible, statistical harmony, so that compression is possible.
Abstract: Past research in the field of cryptography has not given much consideration to arithmetic coding as a feasible encryption technique, with studies proving compression-specific arithmetic coding to be largely unsuitable for encryption. Nevertheless, adaptive modeling, which offers a huge model, variable in structure, and as completely as possible a function of the entire text that has been transmitted since the time the model was initialized, is a suitable candidate for a possible encryption-compression combine. The focus of the work presented in this paper has been to incorporate recent results of chaos theory, proven to be cryptographically secure, into arithmetic coding, to devise a convenient method to make the structure of the model unpredictable and variable in nature, and yet to retain, as far as is possible, statistical harmony, so that compression is possible. A chaos-based adaptive arithmetic coding-encryption technique has been designed, developed and tested and its implementation has been discussed. For typical text files, the proposed encoder gives compression between 67.5% and 70.5%, the zeroth-order compression suffering by about 6% due to encryption, and is not susceptible to previously carried out attacks on arithmetic coding algorithms.
TL;DR: Two low-area designs for the advanced encryption standard on field-programmable gate arrays (FPGAs) are presented, believed to be the smallest to date.
Abstract: This paper presents two low-area designs for the advanced encryption standard on field-programmable gate arrays (FPGAs). Both these designs are believed to be the smallest to date. The first design is an 8-bit application-specific instruction processor, which supports key expansion (currently programmed for a 128-bit key), encipher and decipher. The design utilizes less than 60% of the resources of the smallest available Xilinx Spartan II FPGA (XC2S15). The average encipher-decipher throughput is 2.1 Mbps when clocked at 70 MHz. The design has numerous applications where low area and low power are priorities. The second design, using the Xilinx PicoBlaze soft core is included to provide an embedded 8-bit microcontroller comparison baseline.
TL;DR: Noise figure optimization techniques for inductively degenerated cascode CMOS low-noise amplifiers (LNAs) with on-chip gate inductors are discussed, and three of the power matched techniques significantly improve the noise figures for LNA designs that are to employ on- chip gate inducters.
Abstract: This paper discusses noise figure optimization techniques for inductively degenerated cascode CMOS low-noise amplifiers (LNAs) with on-chip gate inductors. Seven different optimizations techniques are discussed. Of these, five new cases provide power match and balance the transistor noise contribution and the noise contribution from all parasitic resistances in the gate circuit to achieve the best noise performance under the constraints of integrated gate inductor quality factor, power consumption, and gain. Three of the power matched techniques (two power constrained optimizations and a gain-and-power constrained optimization) are recommended as design strategies. These three optimization techniques significantly improve the noise figures for LNA designs that are to employ on-chip gate inductors.
TL;DR: An architecture and implementation of a multichannel potentiostat array based on a novel semi-synchronous sigma-delta (SigmaDelta) analog-to-digital conversion algorithm that combines continuous time SigmaDelta with time-encoding machines, and enables measurement of currents down to femtoampere range is presented.
Abstract: Rapid and accurate detection of pathogens using conductometric biosensors requires potentiostats that can measure small variations in conductance. In this paper, we present an architecture and implementation of a multichannel potentiostat array based on a novel semi-synchronous sigma-delta (SigmaDelta) analog-to-digital conversion algorithm. The algorithm combines continuous time SigmaDelta with time-encoding machines, and enables measurement of currents down to femtoampere range. A 3-mmtimes3-mm chip implementing a 42-channel potentiostat array has been prototyped in a 0.5-mum CMOS technology. Measured results demonstrate that the prototype can achieve 10 bits of resolution, with a sensitivity down to 50-fA current. The power consumption of the potentiostat has been measured to be 11 muW per channel for a sampling rate of 250 kHz. Experiments with a conductometric biosensor specific to Bacillus Cereus bacterium, demonstrate the ability of the potentiostat in identifying different concentration levels of the pathogen in a biological sample
TL;DR: The delay differences cancellation (DDC) technique to reduce the impact of the delay differences on the SFDR property is proposed and verified by simulation results.
Abstract: For a current-steering digital-to-analog converter (DAC) without an extra output stage, the variation of the output voltage will result in the variation of the output delay. These output-dependent delay differences will deteriorate the spurious-free dynamic range (SFDR) of a high-speed high-accuracy DAC, especially when glitches exist. In this paper, a convenient mathematical model is presented to analyze during design the impact of this kind of delay differences on the SFDR. The results are verified by comparison to the results of more detailed simulations. Also the impact of glitches on this effect is demonstrated. Possible solutions to reduce this impact are discussed and summarized