Showing papers in "IEEE Transactions on Circuits and Systems I-regular Papers in 2007"

Pinning Complex Networks by a Single Controller

Abstract: In this paper, without assuming symmetry, irreducibility, or linearity of the couplings, we prove that a single controller can pin a coupled complex network to a homogenous solution. Sufficient conditions are presented to guarantee the convergence of the pinning process locally and globally. An effective approach to adapt the coupling strength is proposed. Several numerical simulations are given to verify our theoretical analysis.

Delay-Dependent $H_{\infty }$ Control and Filtering for Uncertain Markovian Jump Systems With Time-Varying Delays

Abstract: This paper deals with the problems of delay-dependent robust Hinfin control and filtering for Markovian jump linear systems with norm-bounded parameter uncertainties and time-varying delays. In terms of linear matrix inequalities, improved delay-dependent stochastic stability and bounded real lemma (BRL) for Markovian delay systems are obtained by introducing some slack matrix variables. The conservatism caused by either model transformation or bounding techniques is reduced. Based on the proposed BRL, sufficient conditions for the solvability of the robust Hinfin control and Hinfin filtering problems are proposed, respectively. Dynamic output feedback controllers and full-order filters, which guarantee the resulting closed-loop system and the error system, respectively, to be stochastically stable and satisfy a prescribed Hinfin performance level for all delays no larger than a given upper bound, are constructed. Numerical examples are provided to demonstrate the reduced conservatism of the proposed results in this paper.

Full On-Chip CMOS Low-Dropout Voltage Regulator

Abstract: This paper proposes a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture. The large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications. A compensation scheme is presented that provides both a fast transient response and full range alternating current (AC) stability from 0- to 50-mA load current even if the output load is as high as 100 pF. The 2.8-V capacitorless LDO voltage regulator with a power supply of 3 V was fabricated in a commercial 0.35-mum CMOS technology, consuming only 65 muA of ground current with a dropout voltage of 200 mV. Experimental results demonstrate that the proposed capacitorless LDO architecture overcomes the typical load transient and ac stability issues encountered in previous architectures.

Analysis and Design Strategy of UHF Micro-Power CMOS Rectifiers for Micro-Sensor and RFID Applications

Abstract: Design strategy and efficiency optimization of ultrahigh-frequency (UHF) micro-power rectifiers using diode-connected MOS transistors with very low threshold voltage is presented. The analysis takes into account the conduction angle, leakage current, and body effect in deriving the output voltage. Appropriate approximations allow analytical expressions for the output voltage, power consumption, and efficiency to be derived. A design procedure to maximize efficiency is presented. A superposition method is proposed to optimize the performance of multiple-output rectifiers. Constant-power scaling and area-efficient design are discussed. Using a 0.18-mum CMOS process with zero-threshold transistors, 900-MHz rectifiers with different conversion ratios were designed, and extensive HSPICE simulations show good agreement with the analysis. A 24-stage triple-output rectifier was designed and fabricated, and measurement results verified the validity of the analysis

Low-Power CMOS Rectifier Design for RFID Applications

Abstract: We investigate theoretical and practical aspects of the design of far-field RF power extraction systems consisting of antennas, impedance matching networks and rectifiers. Fundamental physical relationships that link the operating bandwidth and range are related to technology dependent quantities like threshold voltage and parasitic capacitances. This allows us to design efficient planar antennas, coupled resonator impedance matching networks and low-power rectifiers in standard CMOS technologies (0.5-mum and 0.18-mum) and accurately predict their performance. Experimental results from a prototype power extraction system that operates around 950 MHz and integrates these components together are presented. Our measured RF power-up threshold (in 0.18-mum, at 1 muW load) was 6 muWplusmn10%, closely matching the predicted value of 5.2 muW.

AER EAR: A Matched Silicon Cochlea Pair With Address Event Representation Interface

Abstract: In this paper, we present an analog integrated circuit containing a matched pair of silicon cochleae and an address event interface. Each section of the cochlea, modeled by a second-order low-pass filter, is followed by a simplified inner hair cell circuit and a spiking neuron circuit. When the neuron spikes, an address event is generated on the asynchronous data bus. We present the results of the chip characterization and the results of an interaural time difference based sound localization experiment using the address event representation (AER) EAR. The chip was fabricated in a 3-metal 2-poly 0.5-mum CMOS process

A Wide-Band Power-Efficient Inductive Wireless Link for Implantable Microelectronic Devices Using Multiple Carriers

Abstract: This paper presents a novel inductive link for wireless transmission of power and data to biomedical implantable microelectronic devices using multiple carrier signals. Achieving higher data bandwidth without compromising the power efficiency is the driving force behind using multiple separate carriers. Two separate pairs of coils have been utilized for inductive power and forward data transmission, plus a pair of miniature antennas for back telemetry. One major challenge, however, is to minimize the interference among these carriers especially on the implantable side, where size and power are highly limited. Planar power coils with spiral shape are optimized in geometry to provide maximum coupling coefficient k. The data coils are designed rectangular in shape and wound across the power coils diameter to be oriented perpendicular to the power coil planes. The goal is to maximize data coils direct coupling, while minimize their cross-coupling with the power coils. The effects of coils geometry, orientation, relative distance, and misalignments on the coupling coefficients have been modeled and experimentally evaluated.

A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design

Abstract: In this paper, we propose a novel full adder design using as few as ten transistors per bit. Compared with other low-gate-count full adder designs using pass transistor logic, the proposed design features lower operating voltage, higher computing speed and lower energy (power delay product) operation. The design adopts inverter buffered xor/xnor designs to alleviate the threshold voltage loss problem commonly encountered in pass transistor logic design. This problem usually prevents the full adder design from operating in low supply voltage or cascading directly without extra buffering. The proposed design successfully embeds the buffering circuit in the full adder design and the transistor count is minimized. The improved buffering helps the design operate under lower supply voltage compared with existing works. It also enhances the speed performance of the cascaded operation significantly while maintaining the performance edge in energy consumption. For performance comparison, both dc andperformances of the proposed design against various full adder designs are evaluated via extensive HSPICE simulations. The simulation results, based on TSMC 2P4M 0.35-mum process models, indicate that the proposed design has the lowest working Vdd and highest working frequency among all designs using ten transistors. It also features the lowest energy consumption per addition among these designs. In addition, the performance edge of the proposed design in both speed and energy consumption becomes even more significant as the word length of the adder increases

An Accurate, Low-Voltage, CMOS Switching Power Supply With Adaptive On-Time Pulse-Frequency Modulation (PFM) Control

Abstract: Integrated switching power supplies with multimode control are gaining popularity in state-of-the-art portable applications like cellular phones, personal digital assistants (PDAs), etc., because of their ability to adapt to various loading conditions and therefore achieve high efficiency over a wide load-current range, which is critical for extended battery life. Constant-frequency, pulsewidth modulated (PWM) switching converters, for instance, have poor light-load efficiencies because of higher switching losses while pulse-frequency modulation (PFM) control in discontinuous-conduction mode (DCM) is more efficient at light loads because the switching frequency and associated switching losses are scaled down with load current. This paper presents the design and integrated circuit prototype results of an 83% power efficient 0.5-V 50-mA CMOS PFM buck (step-down) dc-dc converter with a novel adaptive on-time scheme that generates a 27-mV output ripple voltage from a 1.4- to 4.2-V input supply (battery-compatible range). The output ripple voltage variation and steady-state accuracy of the proposed supply was 5 mV (22-27 mV) and 0.6% whereas its constant on-time counterpart was 45 mV (10-55 mV) and 3.6%, respectively. The proposed control scheme provides an accurate power supply while achieving 2%-10% higher power efficiency than conventional fixed on-time schemes with little circuit complexity added, which is critical during light-loading conditions, where quiescent current plays a pivotal role in determining efficiency and battery-life performance

Analytic Solution to the Photovoltaic Maximum Power Point Problem

Abstract: Photovoltaic (PV) power has been successfully used for over five decades. Whether in dc or ac form, photovoltaic cells provide power for systems in many applications on earth and space. Its principles of operation are therefore well understood, and circuit equivalents have been developed that accurately model the nonlinear relationship between the current and voltage of a photovoltaic cell. With the improved efficiencies of power electronics converters, it is now possible to operate photovoltaic system about its maximum power point (MPP) in order to improve the overall system efficiency. Hitherto, this problem has been tackled using tracking (MPPT) algorithms that iteratively find the point of maximum power and respond to changes in solar irradiance accordingly. A mathematical manipulation that uses the mean value theorem is presented here that provides the analytic solution of a point in a close neighborhood of the MPP. It is thoroughly proved that this point is enclosed in a ball of small radius that also contains the MPP and therefore can practically be considered as the MPP. Since the solution is analytic, no iterative schemes are necessary, and only a periodic measurement is required to adjust to changes in solar irradiance. A circuit is implemented that shows the validity of the theory and the accuracy of the solution.

Advances in Reversed Nested Miller Compensation

Abstract: The use of two frequency compensation schemes for three-stage operational transconductance amplifiers, namely the reversed nested Miller compensation with nulling resistor (RN-MCNR) and reversed active feedback frequency compensation (RAFFC), is presented in this paper. The techniques are based on the basic RNMC and show an inherent advantage over traditional compensation strategies, especially for heavy capacitive loads. Moreover, they are implemented without entailing extra transistors, thus saving circuit complexity and power consumption. A well-defined design procedure, introducing phase margin as main design parameter, is also developed for each solution. To verify the effectiveness of the techniques, two amplifiers have been fabricated in a standard 0.5-mum CMOS process. Experimental measurements are found in good agreement with theoretical analysis and show an improvement in small-signal and large-signal amplifier performances. Finally, an analytical comparison with the nonreversed counterparts topologies, which shows the superiority of the proposed solutions, is also included.

Efficient Adaptive Nonlinear Filters for Nonlinear Active Noise Control

Abstract: In this paper, we treat nonlinear active noise control (NANC) with a linear secondary path (LSP) and with a nonlinear secondary path (NSP) in a unified structure by introducing a new virtual secondary path filter concept and using a general function expansion nonlinear filter. We discover that using the filtered-error structure results in greatly reducing the computational complexity of NANC. As a result, we extend the available filtered-error-based algorithms to solve NANC/LSP problems and, furthermore, develop our adjoint filtered-error-based algorithms for NANC/NSP. This family of algorithms is computationally efficient and possesses a simple structure. We also find that the computational complexity of NANC/NSP can be reduced even more using block-oriented nonlinear models, such as the Wiener, Hammerstein, or linear-nonlinear-linear (LNL) models for the NSP. Finally, we use the statistical properties of the virtual secondary path and the robustness of our proposed methods to further reduce the computational complexity and simplify the implementation structure of NANC/NSP when the NSP satisfies certain conditions. Computational complexity and simulation results are given to confirm the efficiency and effectiveness of all of our proposed methods

A CMOS 3-D Imager Based on Single Photon Avalanche Diode

Abstract: A 64-pixel linear array aimed at 3-D vision applications is implemented in a high-voltage 0.8 mum CMOS technology. The detection of the incident light signals is performed using photodiodes biased above breakdown voltage so that an extremely high sensitivity can be achieved exploiting the intrinsic multiplication effect of the avalanche phenomenon. Each 38times180-mum2 pixel includes, besides the single photon avalanche diode, a dedicated read-out circuit for the arrival-time estimation of incident light pulses. To increase the distance measurement resolution a multiple pulse measurement is used, extracting the mean value of the light pulse arrival-time directly in each pixel; this innovative approach dramatically reduces the dead-time of the pixel read-out, allowing a high frame rate imaging to be achieved. The sensor array provides a range map from 2 m to 5 m with a precision better than plusmn0.75% without any external averaging operation. Moreover, with the same chip, we have explored for the first time the implementation of an indirect time-of-flight measurement by operating the proposed active pixel in the photon counting mode

On Designing Time-Varying Delay Feedback Controllers for Master–Slave Synchronization of Lur'e Systems

Abstract: This paper is concerned with the problem of designing time-varying delay feedback controllers for master-slave synchronization of Lur'e systems. Two cases of time-varying delays are fully considered; one is the time-varying delay being continuous uniformly bounded while the other is the time-varying delay being differentiable uniformly bounded with the derivative of the delay bounded by a constant. Based on Lyapunov-Krasovskii functional approach, some delay-dependent synchronization criteria are first obtained and formulated in the form of linear matrix inequalities (LMIs). The relationship between synchronization criteria for the two cases of time-varying delays is built. Then, sufficient conditions on the existence of a time-varying delay feedback controller are derived by employing these newly-obtained synchronization criteria. The controller gains can be achieved by solving a set of LMIs. Finally, Chua's circuit is used to illustrate the effectiveness of the design method.

A 1-V CMOS Current Reference With Temperature and Process Compensation

Abstract: A 1-V current reference fabricated in a standard CMOS process is described. Temperature compensation is achieved from a bandgap reference core using a transimpedance amplifier in order to generate an intermediate voltage reference, VREF. This voltage applied to the gate of a carefully sized nMOS output transistor provides a reference drain current, IREF , nearly independent of temperature by mutual compensation of mobility and threshold voltage variations. The circuit topology allows for compensation of threshold voltage variation due to process parameters as well. The current reference has been fabricated in a standard 0.18-mum CMOS process. Results from nineteen samples measured over a temperature range of 0degC to 100degC , showed values of IREF of 144.3 muA plusmn 7% and VREF of 610.9 mV plusmn 2% due to the combined effect of temperature and process variations.

Blind Calibration of Timing Offsets for Four-Channel Time-Interleaved ADCs

Abstract: In this paper, we describe a blind calibration method for timing mismatches in a four-channel time-interleaved analog-to-digital converter (ADC). The proposed method requires that the input signal should be slightly oversampled. This ensures that there exists a frequency band around the zero frequency where the Fourier transforms of the four ADC subchannels contain only three alias components, instead of four. Then the matrix power spectral density (PSD) of the ADC subchannels is rank deficient over this frequency band. Accordingly, when the timing offsets are known, we can construct a filter bank that nulls the vector signal at the ADC outputs. We employ a parametrization of this filter bank to develop an adaptive null steering algorithm for estimating the ADC timing offsets. The null steering filter bank employs seven fixed finite-impulse response filters and three unknown timing offset parameters which are estimated by using an adaptive stochastic gradient technique. A convergence analysis is presented for the blind calibration method. Numerical simulations for a bandlimited white noise input and for inputs containing several sinusoidal components demonstrate the effectiveness of the proposed technique

Design of an FFT/IFFT Processor for MIMO OFDM Systems

Abstract: In this paper, we present a novel 128/64 point fast Fourier transform (FFT)/ inverse FFT (IFFT) processor for the applications in a multiple-input multiple-output orthogonal frequency-division multiplexing based IEEE 802.11n wireless local area network baseband processor. The unfolding mixed-radix multipath delay feedback FFT architecture is proposed to efficiently deal with multiple data sequences. The proposed processor not only supports the operation of FFT/IFFT in 128 points and 64 points but can also provide different throughput rates for 1-4 simultaneous data sequences to meet IEEE 802.11n requirements. Furthermore, less hardware complexity is needed in our design compared with traditional four-parallel approach. The proposed FFT/IFFT processor is designed in a 0.13-mum single-poly and eight-metal CMOS process. The core area is 660times2142 mum2 , including an FFT/IFFT processor and a test module. At the operation clock rate of 40 MHz, our proposed processor can calculate 128-point FFT with four independent data sequences within 3.2 mus meeting IEEE 802.11n standard requirements

Circuit Theoretic Classification of Parallel Connected DC–DC Converters

Abstract: This paper describes a classification of paralleling schemes for dc-dc converters from a circuit theoretic viewpoint. The purpose is to provide a systematic classification of the types of parallel converters that can clearly identify all possible structures and control configurations, allowing simple and direct comparison of the characteristics and limitations of different paralleling schemes. In the proposed classification, converters are modeled as current sources or voltage sources, and their connection possibilities, as constrained by Kirchhoff's laws, are categorized systematically into three basic types. Moreover, control arrangements are classified according to the presence of current sharing and voltage-regulation loops. Computer simulations are presented to illustrate the characteristics of the various paralleling schemes

A Scalable Wavelet Transform VLSI Architecture for Real-Time Signal Processing in High-Density Intra-Cortical Implants

Abstract: This paper describes an area and power-efficient VLSI approach for implementing the discrete wavelet transform on streaming multielectrode neurophysiological data in real time. The VLSI implementation is based on the lifting scheme for wavelet computation using the symmlet4 basis with quantized coefficients and integer fixed-point data precision to minimize hardware demands. The proposed design is driven by the need to compress neural signals recorded with high-density microelectrode arrays implanted in the cortex prior to data telemetry. Our results indicate that signal integrity is not compromised by quantization down to 5-bit filter coefficient and 10-bit data precision at intermediate stages. Furthermore, results from analog simulation and modeling show that a hardware-minimized computational core executing filter steps sequentially is advantageous over the pipeline approach commonly used in DWT implementations. The design is compared to that of a B-spline approach that minimizes the number of multipliers at the expense of increasing the number of adders. The performance demonstrates that in vivo real-time DWT computation is feasible prior to data telemetry, permitting large savings in bandwidth requirements and communication costs given the severe limitations on size, energy consumption and power dissipation of an implantable device.

An Ultra-Low-Power Long Range Battery/Passive RFID Tag for UHF and Microwave Bands With a Current Consumption of 700 nA at 1.5 V

Abstract: We present for the first time, a fully integrated battery powered RFID integrated circuit (IC) for operation at ultrahigh frequency (UHF) and microwave bands The battery powered RFID IC can also work as a passive RFID tag without a battery or when the battery has died (ie, voltage has dropped below 13 V); this novel dual passive and battery operation allays one of the major drawbacks of currently available active tags, namely that the tag cannot be used once the battery has died When powered by a battery, the current consumption is 700 nA at 15 V (400 nA if internal signals are not brought out on test pads) This ultra-low-power consumption permits the use of a very small capacity battery of 100 mA-hr for lifetimes exceeding ten years; as a result a battery tag that is very close to a passive tag both in form factor and cost is made possible The chip is built on a 1-mum digital CMOS process with dual poly layers, EEPROM and Schottky diodes The RF threshold power at 245 GHz is -19 dBm which is the lowest ever reported threshold power for RFID tags and has a range exceeding 35 m under FCC unlicensed operation at the 24-GHz microwave band The low threshold is achieved with architectural choices and low-power circuit design techniques At 915 MHz, based on the experimentally measured tag impedance (92-j837) and the threshold spec of the tag (200 mV), the theoretical minimum range is 24 m The tag initially is in a "low-power" mode to conserve power and when issued the appropriate command, it operates in "full-power" mode The chip has on-chip voltage regulators, clock and data recovery circuits, EEPROM and a digital state machine that implements the ISO 18000-4 B protocol in the "full-power" mode We provide detailed explanation of the clock recovery circuits and the implementation of the binary sort algorithm, which includes a pseudorandom number generator Other than the antenna board and a battery, no external components are used

3-D nFPGA: A Reconfigurable Architecture for 3-D CMOS/Nanomaterial Hybrid Digital Circuits

Abstract: In this paper, we introduce a novel reconfigurable architecture, named 3D field-programmable gate array (3D nFPGA), which utilizes 3D integration techniques and new nanoscale materials synergistically. The proposed architecture is based on CMOS nanohybrid techniques that incorporate nanomaterials such as carbon nanotube bundles and nanowire crossbars into CMOS fabrication process. This architecture also has built-in features for fault tolerance and heat alleviation. Using unique features of FPGAs and a novel 3D stacking method enabled by the application of nanomaterials, 3D nFPGA obtains a 4x footprint reduction comparing to the traditional CMOS-based 2D FPGAs. With a customized design automation flow, we evaluate the performance and power of 3D nFPGA driven by the 20 largest MCNC benchmarks. Results demonstrate that 3D nFPGA is able to provide a performance gain of 2.6 x with a small power overhead comparing to the traditional 2D FPGA architecture.

Carbon Nanotube Electronics: Design of High-Performance and Low-Power Digital Circuits

Abstract: Scaling of silicon transistors continue in the sub 100-nm regime amidst severe roadblocks. Increased short-channel effects, rising leakage currents, severe process parameter variations are only a few of the overwhelming challenges that the device and circuit designers are faced with. In an attempt to alleviate the problems associated with the scaling of silicon transistors, researchers have began a quest for novel alternate materials in a post-Si nanoelectronics era. Of the different materials investigated so far, carbon nanotubes with their superior transport properties, excellent thermal conductivities and high current handling capacities have proved to be a potential heir to Si. This paper reviews the promise of carbon nanotube field-effect transistors as future devices for high-performance as well as low-power electronics.

A Multichip Pulse-Based Neuromorphic Infrastructure and Its Application to a Model of Orientation Selectivity

Abstract: The growing interest in pulse-mode processing by neural networks is encouraging the development of hardware implementations of massively parallel networks of integrate-and-fire neurons distributed over multiple chips. Address-event representation (AER) has long been considered a convenient transmission protocol for spike based neuromorphic devices. One missing, long-needed feature of AER-based systems is the ability to acquire data from complex neuromorphic systems and to stimulate them using suitable data. We have implemented a general-purpose solution in the form of a peripheral component interconnect (PCI) board (the PCI-AER board) supported by software. We describe the main characteristics of the PCI-AER board, and of the related supporting software. To show the functionality of the PCI-AER infrastructure we demonstrate a reconfigurable multichip neuromorphic system for feature selectivity which models orientation tuning properties of cortical neurons

Contact Imaging: Simulation and Experiment

Abstract: We report simulated and experimental image quality for contact imaging, a method for imaging objects close to the sensor surface without intervening optics. This technique preserves microscale resolution for applications that can not tolerate the size or weight of conventional optical elements. In order to assess image quality, we investigated the spatial resolution of contact imaging, which depends on the sensor size as well as the distance between objects and the sensor surface. We studied how this distance affects image quality using a commercial optical simulator. Simulation results show that the image quality degrades as objects move away from the sensor surface. To experimentally validate these results, an image sensor was designed and fabricated in a commercially available three metal, two poly, 0.5 mum CMOS technology. Experiments with the contact imager corroborate the simulation results. Two specific applications of contact imaging are demonstrated.

Expandable Networks for Neuromorphic Chips

Abstract: We have developed a grid network that broadcasts spikes (all-or-none events) in a multichip neuromorphic system by relaying them from chip to chip The grid is expandable because, unlike a bus, its capacity does not decrease as more chips are added The multiple relays do not increase latency because the grid's cycle time is shorter than the bus We describe an asynchronous relay implementation that automatically assigns chip addresses to indicate the source of spikes, encoded as word-serial address-events This design, which is integrated on each chip, connects neurons at corresponding locations on each of the chips (pointwise connectivity) and supports oblivious, targeted, and excluded delivery of spikes Results from two chips fabricated in 025-mum technology are presented, showing word-rates up to 454 M events/s

Ultra-Low-Power Interface Chip for Autonomous Capacitive Sensor Systems

Abstract: Traditionally, most of the sensor interfaces must be tailored towards a specific application. This approach results in a high recurrent design cost and time to market. On the other hand, generic sensor interface design reduces the costs and offers a handy solution for multisensor applications. This paper presents a generic sensor interface chip (GSIC), which can read out a broad range of capacitive sensors. It contains capacitance-to-voltage converters, a switched-capacitor amplifier, an analog-to-digital converter, oscillators, clock generation circuits and a reference circuit. The system combines a very low-power design with a smart energy management, which adapts the current consumption according to the accuracy and speed requirements of the application. The GSIC is used in a pressure and an acceleration monitoring system. The pressure monitoring system achieves a current drain of 2.3 muA for a 10-Hz sample frequency and an 8-bit accuracy. In the acceleration monitoring system, we measured a current of 3.3 muA for a sample frequency of 10 Hz and an accuracy of 9 bits

RNS-to-Binary Converters for Two Four-Moduli Sets $\{2^{n}-1,2^{n},2^{n}+1,2^{{n}+1}-1\}$ and $\{2^{n}-1,2^{n},2^{n}+1,2^{{n}+1}+1\}$

Abstract: In this paper, reverse converters for two recently proposed four-moduli sets {2n - 1,2n,2n + 1,2n+1 - 1} and {2n - 1, 2n, 2n + 1, 2n+1 + 1} are described. The reverse conversion in the three-moduli set {2n - 1,2n,2n + 1} has been optimized in literature. Hence, the proposed converters are based on two new moduli sets {(2n(22n-1)),2n+1-1} and {(2n(22n-1)), 2n+1+1} and use mixed radix conversion. The resulting designs do not require any ROM. Both are similar in their architecture except that the converter for the moduli set {2n - 1, 2n, 2n + 1, 2n+1 + 1} is slightly complicated due to the difficulty in performing reduction modulo (2n+1+1) as compared with modulo (2n+1-1). The proposed conversion techniques are compared with earlier realizations described in literature with regard to conversion time as well as area requirements.

Signature Testing of Analog and RF Circuits: Algorithms and Methodology

Abstract: There are mainly two factors responsible for rapidly escalating production test costs of today's RF and high-speed analog circuits: 1) the high cost of high-speed and RF automatic test equipments and 2) long test times required by elaborate performance tests. In this paper, we propose a low-cost signature test methodology for accelerated production testing of analog and RF integrated circuits. As opposed to prior work, the key contribution of this paper is a new test generation algorithm that directly tracks the ability of input test waveforms to predict the test specification values from the observed test response, even in the presence of measurement noise. The response of the device-under-test (DUT) is used as a "signature" from which all of the performance specifications are predicted. The applied test stimulus is optimized in such a way that the error between the measured DUT performances and the predicted DUT performances is minimized. While existing low-cost test approaches have only been applied to low- and medium-frequency analog circuits, the proposed methodology extends low-cost signature testing to RF integrated circuits by incorporating modulation of a baseband test stimulus and subsequent demodulation of the obtained response to obtain the DUT signature. The proposed low-cost solution can be easily built into a load board that can be interfaced to an inexpensive tester

Super-Resolution Time Delay Estimation in Multipath Environments

Abstract: The super-resolution time delay estimation in multipath environment is very important for many applications. Conventional super-resolution approaches can only deal with signals with wideband and flat spectra. In this paper, we propose a novel super-resolution time delay estimation method that can treat signals with narrowband spectra. In our method, the time delay estimation is first transformed into the frequency domain, in which the problem is converted into the parameter estimation of sinusoidal signals with lowpass envelopes. Then a MUSIC-type algorithm taking account of the envelope variation is applied to achieve the super-resolution estimation. Time delay estimation in active and passive systems are considered. Simulation results confirm that the proposed estimators provide better performance than the classical correlation approach and the conventional MUSIC algorithm for separating closely spaced signals with narrowband spectra.

Analytical Design Equations for Class-E Power Amplifiers

Abstract: This paper presents the analytical solution in time domain for the ideal single-ended class-E power amplifier (PA). Based on the analytical solution a coherent noniterative procedure for choosing the circuit parameters is presented for class-E PA's with arbitrary duty-cycle and finite dc-feed inductance (e.g., continuously ranging from class-E with small finite drain inductance to class-E with RF choke). The obtained analysis results link all known class-E PA design equations as well as presenting new design equations. The result of the analysis gives more degrees of freedom to designers in their design and optimization by further expanding the design space of class-E PA.