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Showing papers in "IEEE Transactions on Circuits and Systems I-regular Papers in 2008"


Journal ArticleDOI
TL;DR: This paper proposes a low-power maximum power point tracker (MPPT) circuit specifically designed for wireless sensor nodes, i.e., a power transferring circuit for optimally conveying solar energy into rechargeable batteries even in not optimal weather conditions.
Abstract: The success of wireless sensor networks and their pervasive use is somehow constrained by energy supply which, generally provided by batteries, is a finite resource. Energy harvesting mechanisms must hence be taken into account to grant a long time operational life, with solar energy being the most interesting one in outdoor deployments due to its relatively high power density. In this paper we propose a low-power maximum power point tracker (MPPT) circuit specifically designed for wireless sensor nodes (hence effective, flexible, low cost and power-aware), i.e., a power transferring circuit for optimally conveying solar energy into rechargeable batteries even in not optimal weather conditions. High efficiency is granted by an ad hoc adaptive algorithm which, by keeping the MPPT electronics in its optimal working point, maximizes energy transfer from the solar cell to the batteries. The suggested implementation is particularly effective in critical weather conditions where traditional solutions do not work and is characterized by a flexible enough design for immediately hosting, in a plug in fashion, different solar panels and battery typologies.

441 citations


Journal ArticleDOI
TL;DR: The principle of operation, theoretical analysis, and experimental results of one prototype rated 40 W and operating at 94 kHz are provided in this paper to verify the performance of this new family of converters.
Abstract: A new family of a single-switch three-diode dc-dc pulsewidth-modulated (PWM) converters operating at constant frequency and constant duty cycle is presented in this paper. The proposed converters are different from the conventional dc-dc step-up converters, and they posses higher voltage gain with small output voltage ripples. Other advantages of the proposed converters include lower voltage stress on the semiconductor devices, simple structure, and control. Moreover, the reduced voltage stress on the diodes allows using Schottky diodes for alleviating the reverse-recovery current problem, as well as decreasing the switching and conduction losses. The principle of operation, theoretical analysis, and experimental results of one prototype rated 40 W and operating at 94 kHz are provided in this paper to verify the performance of this new family of converters.

318 citations


Journal ArticleDOI
TL;DR: The Barhkausen condition for a linear noninteger-order (fractional-order) dynamical system to oscillate is derived and the oscillation condition and oscillation frequency of some famous integer-order sinusoidal oscillators can be obtained as special cases from general equations governing their fractional- order counterparts.
Abstract: Sinusoidal oscillators are known to be realized using dynamical systems of second-order or higher. Here we derive the Barhkausen condition for a linear noninteger-order (fractional-order) dynamical system to oscillate. We show that the oscillation condition and oscillation frequency of some famous integer-order sinusoidal oscillators can be obtained as special cases from general equations governing their fractional-order counterparts. Examples including fractional-order Wien oscillators, Colpitts oscillator, phase-shift oscillator and LC tank resonator are given supported by numerical and PSpice simulations.

286 citations


Journal ArticleDOI
TL;DR: A time-domain analysis is proposed that accounts for the time varying nature of the circuit exploiting some basic results from the solution of stochastic differential equations and the resulting symbolic expressions allow focusing designers' attention on the most influential noise contributors.
Abstract: The need for highly integrable and programmable analog-to-digital converters (ADCs) is pushing towards the use of dynamic regenerative comparators to maximize speed, power efficiency and reconfigurability. Comparator thermal noise is, however, a limiting factor for the achievable resolution of several ADC architectures with scaled supply voltages. While mismatch in these comparators can be compensated for by calibration, noise can irreparably hinder performance and is less straightforward to be accounted for at design time. This paper presents a method to estimate the input referred noise in fully dynamic regenerative comparators leveraging a reference architecture. A time-domain analysis is proposed that accounts for the time varying nature of the circuit exploiting some basic results from the solution of stochastic differential equations. The resulting symbolic expressions allow focusing designers' attention on the most influential noise contributors. Analysis results are validated by comparison with electrical simulations and measurement results from two ADC prototypes based on the reference comparator architecture, implemented in 0.18-mum and 90-nm CMOS technologies.

277 citations


Journal ArticleDOI
TL;DR: An adaptive step-perturbation method is proposed to achieve the objective of maximum power point tracking, and an active sun tracking scheme without any light sensors is investigated to make PV plates face the sun directly in order to capture maximum irradiation and enhance system efficiency.
Abstract: This study addresses a grid-connected photovoltaic (PV) generation system. In order to make the PV generation system more flexible and expandable, the backstage power circuit is composed of a high step-up converter and a pulsewidth-modulation (PWM) inverter. In the dc-dc power conversion, the high step-up converter is introduced to improve the conversion efficiency of conventional boost converters and to allow the parallel operation of low-voltage PV modules. Moreover, an adaptive total sliding-mode control system is designed for the current control of the PWM inverter to maintain the output current with a higher power factor and less variation under load changes. In addition, an adaptive step-perturbation method is proposed to achieve the objective of maximum power point tracking, and an active sun tracking scheme without any light sensors is investigated to make PV plates face the sun directly in order to capture maximum irradiation and enhance system efficiency. Experimental results are given to verify the validity of the high step-up converter, the PWM inverter control, the ASP method, and the active sun tracker for a grid-connected PV generation system.

250 citations


Journal ArticleDOI
TL;DR: All proposed conditions for the existence of positive observers and dynamic output-feedback controllers for positive linear systems with interval uncertainties are expressed in terms of the system matrices, and can be verified easily by effective algorithms.
Abstract: This paper is concerned with the design of observers and dynamic output-feedback controllers for positive linear systems with interval uncertainties. The continuous-time case and the discrete-time case are both treated in a unified linear matrix inequality (LMI) framework. Necessary and sufficient conditions for the existence of positive observers with general structure are established, and the desired observer matrices can be constructed easily through the solutions of LMIs. An optimization algorithm to the error dynamics is also given. Furthermore, the problem of positive stabilization by dynamic output-feedback controllers is investigated. It is revealed that an unstable positive system cannot be positively stabilized by a certain dynamic output-feedback controller without taking the positivity of the error signals into account. When the positivity of the error signals is considered, an LMI-based synthesis approach is provided to design the stabilizing controllers. Unlike other conditions which may require structural decomposition of positive matrices, all proposed conditions in this paper are expressed in terms of the system matrices, and can be verified easily by effective algorithms. Two illustrative examples are provided to show the effectiveness and applicability of the theoretical results.

246 citations


Journal ArticleDOI
TL;DR: It is shown that TL converters are highly suitable for high input/output voltage and medium-to-high-power dc-dc power conversions and the virtues and drawbacks of these converters as compared to conventional converters.
Abstract: This paper discusses the basic family of three-level (TL) dc-dc converters. The origin of TL converters and their basic topological variations are described. Systematic procedures leading to improved and simplified circuit topologies are discussed. A feedforward control scheme that ensures the proper functioning of these converters is proposed. Moreover, the virtues and drawbacks of these converters as compared to conventional converters are highlighted. In particular, the advantages of TL converters include reduced voltage stress of the switches, reduced filter size, and improved dynamic response. It is shown that TL converters are highly suitable for high input/output voltage and medium-to-high-power dc-dc power conversions.

239 citations


Journal ArticleDOI
TL;DR: Filippov's method - which has commonly been applied to mechanical switching systems - can be used fruitfully in power electronic circuits to achieve the same end by describing the behavior of the system during the switchings by combining this and the Floquet theory.
Abstract: To study the stability of a nominal cyclic steady state in power electronic converters, it is necessary to obtain a linearization around the periodic orbit. In many past studies, this was achieved by explicitly deriving the Poincare map that describes the evolution of the state from one clock instant to the next and then locally linearizing the map at the fixed point. However, in many converters, the map cannot be derived in closed form, and therefore this approach cannot directly be applied. Alternatively, the orbital stability can be worked out by studying the evolution of perturbations about a nominal periodic orbit, and some studies along this line have also been reported. In this paper, we show that Filippov's method - which has commonly been applied to mechanical switching systems - can be used fruitfully in power electronic circuits to achieve the same end by describing the behavior of the system during the switchings. By combining this and the Floquet theory, it is possible to describe the stability of power electronic converters. We demonstrate the method using the example of a voltage-mode-controlled buck converter operating in continuous conduction mode. We find that the stability of a converter is strongly dependent upon the so-called saltation matrix - the state transition matrix relating the state just after the switching to that just before. We show that the Filippov approach, especially the structure of the saltation matrix, offers some additional insights on issues related to the stability of the orbit, like the recent observation that coupling with spurious signals coming from the environment causes intermittent subharmonic windows. Based on this approach, we also propose a new controller that can significantly extend the parameter range for nominal period-1 operation.

210 citations


Journal ArticleDOI
TL;DR: It is proven experimentally that the STC low-drop-out provides stable voltage regulation at a variety of output-capacitor/ESR conditions and is also stable in no output capacitor condition.
Abstract: The design issues of a single-transistor-control (STC) low-drop-out (LDO) based on flipped voltage follower is discussed in this paper, in particular the feedback stability at different conditions of output capacitors, equivalent series resistances (ESRs) and load current. Based on the analysis, an STC LDO was implemented in a standard 0.35-mum MOS technology. It is proven experimentally that the LDO provides stable voltage regulation at a variety of output-capacitor/ESR conditions and is also stable in no output capacitor condition. The preset output voltage, minimum unregulated input voltage, maximum output current at a dropout voltage of 200 mV, ground current and active chip area are 1 V, 1.2 V, 50 mA, 95 muA, and 140 mum times 320 mum, respectively. The full-load transient response in the no output capacitor case is faster than a micro second and is about 300 ns.

188 citations


Journal ArticleDOI
TL;DR: An adaptive scheme for the stabilization and synchronization of chaotic Lur'e systems with time-varying delay based on the invariant principle of functional differential equations is proposed, which is quite robust against the effect of parameters uncertainty and noise.
Abstract: In this paper, we propose an adaptive scheme for the stabilization and synchronization of chaotic Lur'e systems with time-varying delay. Based on the invariant principle of functional differential equations, the strength of the feedback controller is enhanced adaptively to stabilize and synchronize chaotic Lur'e systems. The derivative-constraint that the time-varying delay is required to be differentiable and its derivation is less than one can be removed by using LaSalle-Razumikhin-type theorems. The time-varying delay is allowed to be bounded without any additional constraint or unbounded with derivative-constraint. This method is analytical, rigorous and simple to implement in practice. In addition, it is quite robust against the effect of parameters uncertainty and noise. Two examples are provided to show the effectiveness of the proposed scheme. The results of the paper demonstrate the fruitfulness of the modern feedback and adaptive control theory application to the stabilization and synchronization problems for delayed chaotic systems.

160 citations


Journal ArticleDOI
TL;DR: Passive RC polyphase filters (PPFs) are analyzed in detail in this paper and the rules for optimal pole frequency planning to maximize the image-reject ratio provided by a PPF are given.
Abstract: Passive RC polyphase filters (PPFs) are analyzed in detail in this paper. First, a method to calculate the output signals of an n-stage PPF is presented. As a result, all relevant properties of PPFs, such as amplitude and phase imbalance and loss, are calculated. The rules for optimal pole frequency planning to maximize the image-reject ratio provided by a PPF are given. The loss of PPF is divided into two factors, namely the intrinsic loss caused by the PPF itself and the loss caused by termination impedances. Termination impedances known a priori can be used to derive such component values, which minimize the overall loss. The effect of parasitic capacitance and component value deviation are analyzed and discussed. The method of feeding the input signal to the first PPF stage affects the mechanisms of the whole PPF. As a result, two slightly different PPF topologies can be distinguished, and they are separately analyzed and compared throughout this paper. A design example is given to demonstrate the developed design procedure.

Journal ArticleDOI
TL;DR: Using a minimum number of passive components, i.e., new grounded and floating inductance simulators, grounded capacitance multipliers, and frequency-dependent negative resistors based on one/two modified current-feedback operational amplifiers (MCFOAs), are proposed.
Abstract: In this paper, using a minimum number of passive components, i.e., new grounded and floating inductance simulators, grounded capacitance multipliers, and frequency-dependent negative resistors (FDNRs) based on one/two modified current-feedback operational amplifiers (MCFOAs), are proposed. The type of the simulators depends on the passive element selection used in the structure of the circuit without requiring critical active and passive component-matching conditions and/or cancellation constraints. In order to show the flexibility of the proposed MCFOA, a single-input three-output (SITO) voltage-mode (VM) filter, two three-input single-output (TISO) VM filters, and an SITO current-mode (CM) filter employing a single MCFOA are reported. The layout of the proposed MCFOA is also given. A number of simulations using the SPICE program and some experimental tests are performed to exhibit the performance of the introduced structures.

Journal ArticleDOI
TL;DR: This work shows how the performance of TOF 3-D cameras can be improved in all relevant respects and contributes to opening up new application domains of the soaring optical TOF range imaging techniques.
Abstract: The reliable detection of the three-dimensional position of arbitrary objects in a scene is a key capability of most animals and one of the most important tasks in machine vision. Today's preferred technical solution is optical time-of-flight (TOF) range imaging, due to its simplicity, its distance resolution, its large and adaptable measurement range, as well as the absence of shadowing problems. In order significantly to extend the application areas of TOF 3-D cameras, in particular for outdoor use, we show how their performance can be improved in all relevant respects: background light suppression is improved by an order of magnitude by the minimum charge transfer method. Multicamera operation is achieved by a binary pseudo-noise modulation/demodulation technique. This method also avoids all practical ambiguity problems typically encountered with harmonic modulation. Higher temporal demodulation resolution becomes possible with a pixel structure employing lateral electric fields. We have realized such pixels with a commercially available CCD/CMOS process, and our measurement results confirm that gigahertz demodulation imaging is possible. The practicality of all theoretical concepts is demonstrated with a miniaturized TOF 3-D camera platform whose LED array light source is modulated at a typical rate of 20 MHz. Our work contributes, therefore, to opening up new application domains of the soaring optical TOF range imaging techniques.

Journal ArticleDOI
TL;DR: It is shown that sufficient information is propagated through the network to allow almost sure local synchronization as long as the expected value of the network is connected, and that the switching rate is sufficiently fast.
Abstract: We assess synchronization of oscillators that are coupled via a time-varying stochastic network, modeled as a weighted directed random graph that switches at a given rate between a set of possible graphs. The existence of any graph edge is probabilistic and independent from the existence of any other edge. We further allow each edge to be weighted differently. Even if the network is always instantaneously not connected, we show that sufficient information is propagated through the network to allow almost sure local synchronization as long as the expected value of the network is connected, and that the switching rate is sufficiently fast.

Journal ArticleDOI
TL;DR: A detailed analysis on the most recently published compensation techniques for single-stage modulators is performed, thus enabling their application to an arbitrary modulator, and results indicate that a compensation of ELD in every stage of the cascade is insufficient for optimal performance.
Abstract: Excess loop delay (ELD) is well known for its detrimental effect on the performance and stability of continuous-time sigma-delta modulators. A detailed analysis on the most recently published compensation techniques for single-stage modulators is performed in this paper, thus enabling their application to an arbitrary modulator. Based on different characteristics such as circuit complexity, achievable dynamic range, or requirements on the operational amplifiers, their advantages and disadvantages are investigated. Subsequently, the analysis is extended to cascaded modulators. Contrary to intuition, the results indicate that a compensation of ELD in every stage of the cascade is insufficient for optimal performance. Although not configured in a feedback configuration and as such not suffering from stability problems, each coupling network between two stages must additionally be compensated for ELD.

Journal ArticleDOI
TL;DR: A new class of single-switch nonisolated high step-up DC-DC converters with simple topologies utilizing a hybrid switched capacitor technique for providing a high voltage gain without extreme switch duty cycle and yet enabling the use of a lower voltage and RDS-ON MOSFET switch so as to reduce cost, switch conduction and turn-on losses.
Abstract: In this paper, a new class of single-switch nonisolated high step-up DC-DC converters with simple topologies is proposed. The proposed topologies utilize a hybrid switched capacitor technique for providing a high voltage gain without extreme switch duty cycle and yet enabling the use of a lower voltage and RDS-ON MOSFET switch so as to reduce cost, switch conduction and turn-on losses. Other advantages of the proposed topologies include: continuous input/output current, simple structure and control. The principle of operation in continuous conduction mode and discontinuous inductor current mode are analyzed. Experimental results obtained on a 45-W prototype are also presented.

Journal ArticleDOI
TL;DR: The following two architectures are developed in this paper: (1) sorting-based (XS) approach and (2) tree structure (TS) approach, which achieve higher speed performance at lower hardware cost.
Abstract: Given a set of numbers X, finding the minimum value of X, min_1st, is a very easy task. However, efficiently finding its second minimum value, min_2nd, requires the derivations of min_1st and finding the minimum value from the set of the remaining numbers. Efficient algorithms and cost-effective hardware of finding the two smallest of X are greatly needed for the low-density parity-check (LDPC) decoder design. The following two architectures are developed in this paper: (1) sorting-based (XS) approach and (2) tree structure (TS) approach. Experimental results show that the XS approach provides less number of comparisons, while the TS approach achieves higher speed performance at lower hardware cost. Since the hardware unit is repeatedly used in the LDPC decoder design, the proposed high-speed low-cost TS approach is strongly recommended.

Journal ArticleDOI
TL;DR: This paper focuses on modeling and compensation of frequency-dependent gain/phase imbalance and dc offset when the input and output of the direct upconverter are available and channel models are proposed to describe the effects on transmitted I/Q data streams.
Abstract: Impairments in the analog quadrature modulator can adversely impact the performance of a digital predistortion linearization system. In this paper, we focus on modeling and compensation of frequency-dependent gain/phase imbalance and dc offset when the input and output of the direct upconverter are available. We first propose channel models to describe the effects of these impairments on transmitted I/Q data streams. We then develop algorithms to estimate the parameters of these channel models and to construct I/Q compensators. Performance of the algorithms and the I/Q compensators is shown in conjunction with digital predistortion.

Journal ArticleDOI
TL;DR: A novel algorithm for designing low-power and hardware-efficient linear-phase finite-impulse response (FIR) filters is presented, a branch-and-bound-based algorithm that fixes a coefficient to a certain value using linear programming.
Abstract: A novel algorithm for designing low-power and hardware-efficient linear-phase finite-impulse response (FIR) filters is presented. The algorithm finds filter coefficients with reduced number of signed-power-of-two (SPT) terms given the filter frequency response characteristics. The algorithm is a branch-and-bound-based algorithm that fixes a coefficient to a certain value. The value is determined by finding the boundary values of the coefficient using linear programming. Although the worst case run time of the algorithm is exponential, its capability to find appreciably good solutions in a reasonable amount of time makes it a desirable CAD tool for designing low-power and hardware-efficient filters. The superiority of the algorithm on existing methods in terms of SPT term count, design time, hardware complexity, and power performance is shown with several design examples. Up to 30% reduction in the number of SPT terms is achieved over unoptimized Remez coefficients, which is 20% better than compared optimization methods. The average power saving is 20% over unoptimized coefficients, which is up to 14% better than optimized coefficients obtained with existing methods.

Journal ArticleDOI
TL;DR: This paper addresses the problem of investigating the limits of the linearized approach and applies it to the computation of the jitter transfer and the jitters depending on the level of noise at the binary phase detector input, and compares to phase noise measurements obtained from a digital bang-bang PLL implemented in 130-nm CMOS technology.
Abstract: In the last few years, several digital implementations of phase-locked loops (PLLs) have emerged, in some cases outperforming analog ones. Some of these PLLs use a bang-bang phase detector to convert the phase error into a digital value. Unfortunately, that introduces a hard nonlinearity in the loop which prevents the use of the traditional linear analysis. Nevertheless, authors resort to linearized models for the noise analysis of this kind of loops, but to the author's knowledge, no attempt has been made to evaluate the limits of this approach. In this paper, we address the problem of investigating the limits of the linearized approach, and we apply it to the computation of the jitter transfer and the jitter generation depending on the level of noise at the binary phase detector input. The results will be compared to phase noise measurements obtained from a digital bang-bang PLL implemented in 130-nm CMOS technology.

Journal ArticleDOI
TL;DR: The differentiator-multiplier cascade, a multistage reconstruction system that recovers the uniform samples from the nonuniform samples that reduces implementation costs substantially, especially in an application like time-interleaved analog-to-digital converters (TI-ADCs) where the timing mismatches among the ADCs may change during operation.
Abstract: This paper considers the problem of reconstructing a bandlimited signal from its nonuniform samples. Based on a discrete-time equivalent model for nonuniform sampling, we propose the differentiator-multiplier cascade, a multistage reconstruction system that recovers the uniform samples from the nonuniform samples. Rather than using optimally designed reconstruction filters, the system improves the reconstruction performance by cascading stages of linear-phase finite impulse response (FIR) filters and time-varying multipliers. Because the FIR filters are designed as differentiators, the system works for the general nonuniform sampling case and is not limited to periodic nonuniform sampling. To evaluate the reconstruction performance for a sinusoidal input signal, we derive the signal-to-noise-ratio at the output of each stage for the two-periodic and the general nonuniform sampling case. The main advantage of the system is that once the differentiators have been designed, they are implemented with fixed multipliers, and only some general multipliers have to be adapted when the sampling pattern changes; this reduces implementation costs substantially, especially in an application like time-interleaved analog-to-digital converters (TI-ADCs) where the timing mismatches among the ADCs may change during operation.

Journal ArticleDOI
TL;DR: An energy-efficient low-complexity pulse-generator design technique for multiband impulse-radio ultrawide-band (IR-UWB) system in 0.18-mum CMOS technology that can maintain its simplicity for low cost with core chip size of 0.3 mm2.
Abstract: This paper presents an energy-efficient low-complexity pulse-generator design technique for multiband impulse-radio ultrawide-band (IR-UWB) system in 0.18-mum CMOS technology. The short pulses are generated based on the on/off switching operation of an oscillator with subband switching functionality, which is mandatory for multiband IR-UWB systems. The relation between the oscillator switching operation and the resulting output pulse envelope, which determines pulse spectral characteristics, is analyzed, and the design guidelines for topology and component values are presented. Measurements show the output pulses with the duration of 3.5 ns, which corresponds to 520-MHz bandwidth. The output pulse spectrum centered at 3.8 GHz fully complies with the Federal Communication Commission spectral mask with more than 25 dB of sidelobe suppression without the need for additional filtering. Thus, the low-complexity pulse generator can maintain its simplicity for low cost with core chip size of 0.3 mm2. The pulse generator shows an excellent energy efficiency with average energy dissipation of 16.8 pJ per pulse from 1.5-V supply. The proposed pulse generator is best suited for energy-detection IR-UWB systems.

Journal ArticleDOI
TL;DR: A phase-domain macromodel is deduced which is able to capture high-order synchronization effects and the expressions derived for synchronization-regions are very general since they apply to any oscillator topology.
Abstract: This paper presents a novel approach to the analysis of oscillator injection locking due to weak external signals. From the intuitive concept of impulse-sensitivity function, a phase-domain macromodel is deduced which is able to capture high-order synchronization effects. Novel closed-form expressions for the synchronization regions are thus presented. The proposed phase-domain macromodel and the expressions derived for synchronization-regions are very general since they apply to any oscillator topology.

Journal ArticleDOI
TL;DR: Analysis based on a nonlinear simplified discrete-time model, which takes into account the effects of parasitics, is performed to investigate the coexistence of fast-scale and slow-scale bifurcations in simple dc/dc converters under peak current- modes operating in continuous conduction mode.
Abstract: This paper investigates the coexisting fast-scale and slow-scale bifurcations in simple dc/dc converters under peak current-mode control operating in continuous conduction mode. Our focus is the boost converter as it is a representative form of dc/dc converter requiring current-mode control. Effects of varying the input voltage and some chosen parameters on the qualitative behavior of the system are studied in detail. Analysis based on a nonlinear simplified discrete-time model, which takes into account the effects of parasitics, is performed to investigate the coexistence of fast-scale and slow-scale bifurcations, and to identify the different types of bifurcation. Boundaries of stable region, slow-scale bifurcation region, fast-scale bifurcation region, coexisting fast and slow-scale bifurcation region are identified. Experimental measurements of the boost converter are provided for verification of the analytical results.

Journal ArticleDOI
TL;DR: The sample design demonstrated that the match-line power consumption using a segmented match line was conservatively 44% of that produced by traditional parallel TCAM, which is designed using 0.18-mum CMOS technology.
Abstract: Power consumption in match lines is the most critical issue for low-power ternary content-addressable memory (TCAM) designs. In the proposed match-line architecture, the match line in each TCAM word is partitioned into four segments and is selectively pre-charged to reduce the match-line power consumption. The partially charged match lines are evaluated to determine the final comparison result by sharing the charges deposited in various parts of the partitioned segments. This arrangement reduces the match-line power consumption by reducing effective capacitor loading and voltage swing at match lines. The segmented architecture also enhances operational speed by evaluating multiple segments in parallel and by overlapping the pre-charging and evaluation stages. 512 times 72 TCAM is designed using 0.18-mum CMOS technology. The extracted RC values are used to show the power reduction benefits. The sample design demonstrated that the match-line power consumption using a segmented match line was conservatively 44% of that produced by traditional parallel TCAM. The power savings by segmenting match lines can be up to 41% over a low-voltage swing technique due to the independent discharge capability in segmented match-line architecture.

Journal ArticleDOI
TL;DR: It is proved that for a given nonsmooth convex optimization problem and sufficiently large penalty parameters, any trajectory of the neural network can reach the feasible region in finite time and stays there thereafter.
Abstract: This paper develops a neural network for solving the general nonsmooth convex optimization problems. The proposed neural network is modeled by a differential inclusion. Compared with the existing neural networks for solving nonsmooth convex optimization problems, this neural network has a wider domain for implementation. Under a suitable assumption on the constraint set, it is proved that for a given nonsmooth convex optimization problem and sufficiently large penalty parameters, any trajectory of the neural network can reach the feasible region in finite time and stays there thereafter. Moreover, we can prove that the trajectory of the neural network constructed by a differential inclusion and with arbitrarily given initial value, converges to the set consisting of the equilibrium points of the neural network, whose elements are all the optimal solutions of the primal constrained optimization problem. In particular, we give the condition that the equilibrium point set of the neural network coincides with the optimal solution set of the primal constrained optimization problem and the condition ensuring convergence to the optimal solution set in finite time. Furthermore, illustrative examples show the correctness of the results in this paper, and the good performance of the proposed neural network.

Journal ArticleDOI
TL;DR: The new rectifier eliminates the need for additional large switches for load modulation and provides more flexibility in choosing the most appropriate load shift keying (LSK) mechanism through shorting and/or opening the transponder coil for any certain application.
Abstract: This paper describes the design and implementation of an integrated full-wave standard CMOS rectifier with built-in passive back telemetry mechanism for radio frequency identification (RFID) and implantable biomedical device applications. The new rectifier eliminates the need for additional large switches for load modulation and provides more flexibility in choosing the most appropriate load shift keying (LSK) mechanism through shorting and/or opening the transponder coil for any certain application. The results are a more robust back telemetry link, improved read range, higher back telemetry data rate, reduced rectifier dropout voltage, and saving in chip area compared to the traditional topologies. A prototype version of the new rectifier is implemented in the AMI 0.5- mum n-well 3-metal 2-poly 5 V standard CMOS process, occupying ~ 0.25 mm2 of chip area. The prototype rectifier was powered through a wireless inductive link and proved to be fully functional in its three modes of operation: rectification, open coil (OC), and short coil (SC).

Journal ArticleDOI
TL;DR: A new algorithm, dynamic bacterial foraging algorithm (DBFA), for solving an OPF problem in a dynamic environment in which system loads are changing, which can more rapidly adapt to load changes, and more closely trace the global optimum of the system fuel cost, in comparison with BFA and particle swarm optimizer.
Abstract: Optimal power flow (OPF) problem has already been attempted as a static optimization problem, by adopting conventional gradient-based methods and more recently, nonconventional ones, such as evolutionary algorithms. However, as the loads, generation capacities and network connections in a power system are always in a changing status, these static-oriented methods are of limited use for this issue. This paper presents a new algorithm, dynamic bacterial foraging algorithm (DBFA), for solving an OPF problem in a dynamic environment in which system loads are changing. DBFA is based on the recently proposed BFA which mimics the basic foraging behavior of E. coli bacteria. A selection scheme for bacteria's reproduction is employed in DBFA, which explores the self-adaptability of each bacterium in the group searching activities. DBFA has been evaluated, for optimizing the power system fuel cost with the OPF embedded, on the standard IEEE 30-bus and 118-bus test systems, respectively, with a range of load changes which occurred in different probabilities. The simulation results show that DBFA can more rapidly adapt to load changes, and more closely trace the global optimum of the system fuel cost, in comparison with BFA and particle swarm optimizer.

Journal ArticleDOI
TL;DR: The modification involves a generalization of the synthesis approach to employ mirror elements in the admittance matrix expansion and ideal description of active elements, rather than using only nullor elements (nullators and norators).
Abstract: This paper proposes a modification for the symbolic synthesis method of analog circuits using admittance matrix expansion. The modification involves a generalization of the synthesis approach to employ mirror elements (voltage mirrors and current mirrors) in the admittance matrix expansion and ideal description of active elements, rather than using only nullor elements (nullators and norators). Accordingly, more alternative ideal representations, based on nullor-mirror elements, can be realized and a wide range of active elements can be used in the circuit synthesis. Systematic synthesis of the CCII-based generalized impedance converters (GICs) is presented as an application example to illustrate the potential of this generalized approach. Multiple equivalent nullor-mirror realizations for the GIC could be extracted easily, by virtue of using mirror elements in the admittance matrix expansion. Consequently, numerous circuit realizations, spanning various combinations of CCII types, have been generated in a simple and direct way.

Journal ArticleDOI
Maoyin Chen1
TL;DR: An analytical condition for chaos synchronization in complex networks with a time-invariant configuration and the inner-coupling matrix satisfy certain conditions is proposed and the effectiveness of the proposed synchronization criteria is verified.
Abstract: In this paper, we study chaos synchronization in complex networks with time-invariant, time-varying and switching configurations based on the matrix measure of complex matrices. To begin with, we propose an analytical condition for chaos synchronization in complex networks with a time-invariant configuration. Secondly, we obtain some less conservative synchronization conditions for networks with a time-varying configuration. Thirdly, we consider chaos synchronization in networks with time-average and switching configurations. If complex subnetworks satisfy certain conditions, the networks with time-average and switching configurations are M-synchronizable. At last, we analyze the nonsynchronizability of complex networks. Chaos synchronization in complex networks can't be realized if the coupling configuration and the inner-coupling matrix satisfy certain conditions. Theoretical analysis and numerical simulations verify the effectiveness of the proposed synchronization criteria.