# Showing papers in "IEEE Transactions on Circuits and Systems I-regular Papers in 2010"

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TL;DR: In this article, a distributed observer-type consensus protocol based on relative output measurements is proposed to solve the consensus problem of multi-agent systems with a time-invariant communication topology consisting of general linear node dynamics.

Abstract: This paper addresses the consensus problem of multiagent systems with a time-invariant communication topology consisting of general linear node dynamics. A distributed observer-type consensus protocol based on relative output measurements is proposed. A new framework is introduced to address in a unified way the consensus of multiagent systems and the synchronization of complex networks. Under this framework, the consensus of multiagent systems with a communication topology having a spanning tree can be cast into the stability of a set of matrices of the same low dimension. The notion of consensus region is then introduced and analyzed. It is shown that there exists an observer-type protocol solving the consensus problem and meanwhile yielding an unbounded consensus region if and only if each agent is both stabilizable and detectable. A multistep consensus protocol design procedure is further presented. The consensus with respect to a time-varying state and the robustness of the consensus protocol to external disturbances are finally discussed. The effectiveness of the theoretical results is demonstrated through numerical simulations, with an application to low-Earth-orbit satellite formation flying.

2,096 citations

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TL;DR: An approach to use memristors (resistors with memory) in programmable analog circuits in which low voltages are applied to memristor during their operation as analog circuit elements and high voltage are used to program the Memristor's states.

Abstract: We suggest an approach to use memristors (resistors with memory) in programmable analog circuits. Our idea consists in a circuit design in which low voltages are applied to memristors during their operation as analog circuit elements and high voltages are used to program the memristor's states. This way, as it was demonstrated in recent experiments, the state of memristors does not essentially change during analog mode operation. As an example of our approach, we have built several programmable analog circuits demonstrating memristor-based programming of threshold, gain and frequency. In these circuits the role of memristor is played by a memristor emulator developed by us.

553 citations

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TL;DR: It is shown that these proposed Bio-inspired Imprecise Computational blocks (BICs) can be exploited to efficiently implement a three-layer face recognition neural network and the hardware defuzzification block of a fuzzy processor.

Abstract: The conventional digital hardware computational blocks with different structures are designed to compute the precise results of the assigned calculations. The main contribution of our proposed Bio-inspired Imprecise Computational blocks (BICs) is that they are designed to provide an applicable estimation of the result instead of its precise value at a lower cost. These novel structures are more efficient in terms of area, speed, and power consumption with respect to their precise rivals. Complete descriptions of sample BIC adder and multiplier structures as well as their error behaviors and synthesis results are introduced in this paper. It is then shown that these BIC structures can be exploited to efficiently implement a three-layer face recognition neural network and the hardware defuzzification block of a fuzzy processor.

458 citations

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TL;DR: The paper answers the challenging questions in pinning control of complex networks: what sufficient conditions can guarantee global asymptotic stability of the pinning process; what nodes should be chosen as pinned candidates; and how many nodes are needed to be pinned for a fixed coupling strength.

Abstract: This paper presents some low-dimensional pinning criteria for global synchronization of both directed and undirected complex networks, and proposes specifically pinning schemes to select pinned nodes by investigating the relationship among pinning synchronization, network topology, and the coupling strength. The paper answers the challenging questions in pinning control of complex networks: 1) what sufficient conditions can guarantee global asymptotic stability of the pinning process; 2) what nodes should be chosen as pinned candidates; and 3) how many nodes are needed to be pinned for a fixed coupling strength? Furthermore, an adaptive pinning control scheme is developed to achieve synchronization of general complex networks. Numerical examples are given to verify our theoretical analysis.

412 citations

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TL;DR: Based on the concept of control topology, an impulsive controller is designed to achieve the exponential synchronization of CDNs, and moreover, the exponential convergence rate can be specified.

Abstract: In this paper, the synchronization of complex dynamical networks (CDNs) with system delay and multiple coupling delays is studied via impulsive distributed control. The concept of control topology is introduced to describe the whole controller structure, which consists of some directed connections between nodes. The control topology can be designed either to be the same as the non-delayed coupling topology of the network, or to be independent of the intrinsic network topology. Based on the concept of control topology, an impulsive controller is designed to achieve the exponential synchronization of CDNs, and moreover, the exponential convergence rate can be specified. Illustrated examples have been given to show the effectiveness of the proposed impulsive distributed control strategy.

395 citations

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TL;DR: In this article, the performance of VCO-based ADCs in the presence of nonidealities such as jitter, nonlinearity, mismatch, and the metastability of D flip-flops is analyzed.

Abstract: A voltage-controlled oscillator (VCO) based analog-to-digital converter (ADC) is a time-based architecture with a first-order noise-shaping property, which can be implemented using a VCO and digital circuits. This paper analyzes the performance of VCO-based ADCs in the presence of nonidealities such as jitter, nonlinearity, mismatch, and the metastability of D flip-flops. Based on this analysis, design criteria for determining parameters for VCO-based ADCs are described. In addition, a digital calibration technique to enhance the spurious-free dynamic range degraded by the nonlinearity is also introduced. To verify the theoretical analysis, a prototype chip is implemented in a 0.13-?m CMOS process. With a 500-MHz sampling frequency, the prototype achieves a signal-to-noise ratio ranging from 71.8 to 21.3 dB for an input bandwidth of 100 kHz-247 MHz, while dissipating 12.6 mW and occupying an area of 0.078 mm2.

253 citations

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TL;DR: A “smart” microcontroller-based power management system with online power stage efficiency optimization and maximum power point tracking (MPPT) is presented, experimentally evaluated using a new, more accurate four-quadrant rectenna model and circuit realization.

Abstract: For many years, wireless RF power transmission has been investigated as a viable method of power delivery in a wide array of applications, from high-power space solar power satellites to low-power wireless sensors. However, until recently, efficient application at the low sub-milliwatt power levels has not been realized due to limitations in available control circuitry. This paper presents a “smart” microcontroller-based power management system with online power stage efficiency optimization and maximum power point tracking (MPPT). The system is experimentally evaluated using a new, more accurate four-quadrant rectenna model and circuit realization that enables rigorous testing of the power management system for a wide range of rectenna arrays and power characteristics. Hardware results are presented with online optimization over a converter input power range from 10 μW to 1 mW. Results are also shown based on the application of harvesting RF power from a nearby cellular tower, where the power management system collects up to seven times more energy when compared to a direct battery connection.

212 citations

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TL;DR: In this paper, the DC behavior of subthreshold CMOS logic is analyzed in a closed form for the first time in the literature and previously proposed rule of thumbs to evaluate minimum voltage are theoretically justified.

Abstract: In this paper, the DC behavior of subthreshold CMOS logic is analyzed in a closed form for the first time in the literature. To this aim, simplified large-signal and small-signal models of MOS transistors in subthreshold region are first developed. After replacing transistors with these equivalent models, analysis of the main DC parameters of CMOS logic gates is presented. In particular, the change in the DC characteristics shape due to operation at ultra-low voltages is analyzed in detail, evaluating analytically the degradation in the logic swing, the symmetry and the steepness of the transition region, as well as the change in the unity-gain points position. The resulting expressions permit to gain an insight into the basic dependence of DC behavior on design and device parameters. The noise margin is explicitly evaluated and modeled with a very simple expression. Interestingly, analysis shows that the noise margin deviates from the ideal half-swing value by an amount that linearly depends on the logarithm of the pn -ratio. Analysis permits to evaluate the minimum supply voltage that ensures correct operation of CMOS logic (i.e., positive noise margin). Previously proposed rule of thumbs to evaluate minimum voltage are also theoretically justified. Moreover, the impact of pMOS/nMOS unbalancing on DC characteristics is analyzed from a design perspective. Considerations on the impact of process/voltage/temperature variations are also introduced. Results are validated through extensive simulations in a 65-nm CMOS technology.

176 citations

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TL;DR: A new approach employing local negative feedback is introduced between the parallel CG and CS stages, leading to an LNA with higher gain and lower noise figure (NF) compared with the conventional CG-CS LNA, particularly under low power and voltage constraints.

Abstract: A wideband noise-cancelling low-noise amplifier (LNA) without the use of inductors is designed for low-voltage and low-power applications. Based on the common-gate-common-source (CG-CS) topology, a new approach employing local negative feedback is introduced between the parallel CG and CS stages. The moderate gain at the source of the cascode transistor in the CS stage is utilized to boost the transconductance of the CG transistor. This leads to an LNA with higher gain and lower noise figure (NF) compared with the conventional CG-CS LNA, particularly under low power and voltage constraints. By adjusting the local open-loop gain, the NF can be optimized by distributing the power consumption among transistors and resistors based on their contribution to the NF. The optimal value of the local open-loop gain can be obtained by taking into account the effect of phase shift at high frequency. The linearity is improved by employing two types of distortion-cancelling techniques. Fabricated in a 0.13-μm RF CMOS process, the LNA achieves a voltage gain of 19 dB and an NF of 2.8-3.4 dB over a 3-dB bandwidth of 0.2-3.8 GHz. It consumes 5.7 mA from a 1-V supply and occupies an active area of only 0.025 mm2.

168 citations

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TL;DR: In this paper, circuit theoretic multiport models for radio communication systems are developed and an in-depth analysis is provided on the impact of impedance matching, antenna mutual coupling, and different sources of noise on the performance of the communication system.

Abstract: Electromagnetic field theory provides the physics of radio communications, while information theory approaches the problem from a purely mathematical point of view. While there is a law of conservation of energy in physics, there is no such law in information theory. Consequently, when, in information theory, reference is made (as it frequently is) to terms like energy, power, noise, or antennas, it is by no means guaranteed that their use is consistent with the physics of the communication system. Circuit theoretic multiport concepts can help in bridging the gap between the physics of electromagnetic fields and the mathematical world of information theory, so that important terms like energy or antenna are indeed used consistently through all layers of abstraction. In this paper, we develop circuit theoretic multiport models for radio communication systems. To demonstrate the utility of the circuit theoretic approach, an in-depth analysis is provided on the impact of impedance matching, antenna mutual coupling, and different sources of noise on the performance of the communication system. Interesting insights are developed about the role of impedance matching and the noise properties of the receive amplifiers, as well as the way array gain and channel capacity scale with the number of antennas in different circumstances. One particularly interesting result is that, with arrays of lossless antennas that receive isotropic background noise, efficient multistreaming can be achieved no matter how densely the antennas are packed.

165 citations

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TL;DR: Two simple yet effective data- processing techniques are presented that can well tolerate significant cell-to-cell interference at the system level and essentially originate from two signal-processing techniques being widely used in digital communication systems to compensate communication-channel intersymbol interference.

Abstract: With the appealing storage-density advantage, multilevel-per-cell (MLC) NAND Flash memory that stores more than 1 bit in each memory cell now largely dominates the global Flash memory market. However, due to the inherent smaller noise margin, the MLC NAND Flash memory is more subject to various device/circuit variability and noise, particularly as the industry is pushing the limit of technology scaling and a more aggressive use of MLC storage. Cell-to-cell interference has been well recognized as a major noise source responsible for raw-memory-storage reliability degradation. Leveraging the fact that cell-to-cell interference is a deterministic data-dependent process and can be mathematically described with a simple formula, we present two simple yet effective data-processing techniques that can well tolerate significant cell-to-cell interference at the system level. These two techniques essentially originate from two signal-processing techniques being widely used in digital communication systems to compensate communication-channel intersymbol interference. The effectiveness of these two techniques have been well demonstrated through computer simulations and analysis under an information theoretical framework, and the involved design tradeoffs are discussed in detail.

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TL;DR: In this article, a wide variety of voltage mixers and samplers are implemented with similar circuits employing switches, resistors, and capacitors, and they are decomposed into a polyphase multipath combination of single-ended or differential switched-series-RC kernels.

Abstract: A wide variety of voltage mixers and samplers are implemented with similar circuits employing switches, resistors, and capacitors. Restrictions on duty cycle, bandwidth, or output frequency are commonly used to obtain an analytical expression for the response of these circuits. This paper derives unified expressions without these restrictions. To this end, the circuits are decomposed into a polyphase multipath combination of single-ended or differential switched-series-RC kernels. Linear periodically time-variant network theory is used to find the harmonic transfer functions of the kernels and the effect of polyphase multipath combining. From the resulting transfer functions, the conversion gain, output noise, and noise figure can be calculated for arbitrary duty cycle, bandwidth, and output frequency. Applied to a circuit, the equations provide a mathematical basis for a clear distinction between a “mixing” and a “sampling” operating region while also covering the design space “in between.” Circuit simulations and a comparison with mixers published in literature are performed to support the analysis.

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ams AG

^{1}TL;DR: The application field for this oscillator is the clock generation of low-power wake-up functions for battery-operated systems and a detailed analysis of the oscillator, including the temperature performance, is derived and verified with experimental results.

Abstract: This paper presents the design of a low-voltage ultralow-power relaxation oscillator without external components. The application field for this oscillator is the clock generation of low-power wake-up functions for battery-operated systems. A detailed analysis of the oscillator, including the temperature performance, is derived and verified with experimental results. The oscillator operates at a typical frequency of 3.3 kHz and consumes 11 nW from a 1-V supply at room temperature, and a temperature drift of less than 500 ppm/°C is achieved over the temperature range of -20°C to 80°C. An efficient design implementation has resulted in a cell area of 0.1 mm2 in a standard 0.35- μm digital CMOS technology.

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TL;DR: A novel adaptive strategy for consensus and synchronization of complex networks inspired by bistable phenomena that are observed in a variety of mechanical systems is presented, that involves the topology of the network itself rather than its coupling gains.

Abstract: In this paper, we present a novel adaptive strategy for consensus and synchronization of complex networks. The strategy is inspired by bistable phenomena that are observed in a variety of mechanical systems. The novelty is that the adaptation involves the topology of the network itself rather than its coupling gains. In particular, we model the evolution of each coupling gain as a second order dynamical system that is subject to the action of a double-well potential. Through a new mechanism, termed as edge snapping, an unweighted network topology emerges at steady state. We assess the stability properties of the proposed scheme through analytical methods and numerical investigations. We conduct an extensive numerical study of the topological properties of the emerging network to elucidate the correlation between the initial conditions of the nodes' dynamics and the network structure.

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TL;DR: This work analyzes the negative-gm LC model and presents a simple equation that quantifies output noise resulting from phase fluctuations, and derives an expression for output Noise resulting from amplitude fluctuations.

Abstract: Recent work by Bank, and Mazzanti and Andreani has offered a general result concerning phase noise in nearly-sinusoidal inductance-capacitance (LC) oscillators; namely that the noise factor of such oscillators (under certain achievable conditions) is largely independent of the specific operation of individual transistors in the active circuitry. Both use the impulse sensitivity function (ISF). In this work, we show how the same result can be obtained by generalizing the phasor-based analysis. Indeed, as applied to nearly-sinusoidal LC oscillators, we show how the two approaches are equivalent. We analyze the negative-gm LC model and present a simple equation that quantifies output noise resulting from phase fluctuations. We also derive an expression for output noise resulting from amplitude fluctuations. Further, we extend the analysis to consider the voltage-biased LC oscillator and fully differential CMOS LC oscillator, for which the Bank's general result does not apply. Thus we quantify the concept of loaded Q.

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TL;DR: Since the leakage power increases much faster than the dynamic power at each new technology generation, LPA attacks are a serious threat to the information security of cryptographic circuits in sub-100-nm technologies.

Abstract: In this paper, a novel class of power analysis attacks to cryptographic circuits is presented. These attacks aim at recovering the secret key of a cryptographic core from measurements of its static (leakage) power. These attacks exploit the dependence of the leakage current of CMOS integrated circuits on their inputs (including the secret key of the cryptographic algorithm that they implement), as opposite to traditional power analysis attacks that are focused on the dynamic power. For this reason, this novel class of attacks is named ?leakage power analysis? (LPA). Since the leakage power increases much faster than the dynamic power at each new technology generation, LPA attacks are a serious threat to the information security of cryptographic circuits in sub-100-nm technologies. For the first time in the literature, a well-defined procedure to perform LPA attacks that is based on a solid theoretical background is presented. Advantages and measurement issues are also analyzed in comparison with traditional power analysis attacks based on dynamic power measurements. Examples are provided for various circuits, and an experimental attack to a register is performed for the first time. An analytical model of the LPA attack result is also provided to better understand the effectiveness of this technique. The impact of technology scaling is explicitly addressed by means of a simple analytical model and Monte Carlo simulations. Simulations on a 65- and 90-nm technology and experimental results are presented to justify the assumptions and validate the leakage power models that are adopted.

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TL;DR: Two new 4-moduli sets are introduced for developing efficient large dynamic range (DR) residue number systems (RNS) and efficient reverse converters for the proposed moduli sets based onNew CRTs are presented.

Abstract: In this paper, we introduce two new 4-moduli sets {2n-1, 2n, 2n+1, 22n+1-1} and {2n-1, 2n+1, 22n, 22n+1} for developing efficient large dynamic range (DR) residue number systems (RNS). These moduli sets consist of simple and well-formed moduli which can result in efficient implementation of the reverse converter as well as internal RNS arithmetic circuits. The moduli set {2n-1, 2n, 2n+1, 22n+1-1} has 5n-bit DR and it can result in a fast RNS arithmetic unit, while the 6n-bit DR moduli set {2n-1, 2n+1, 22n, 22n+1} is a conversion friendly moduli set which can lead to a high-speed and low-cost reverse converter design. Next, efficient reverse converters for the proposed moduli sets based on new Chinese remainder theorems (New CRTs) are presented. The converter for the moduli set {2n-1, 2n, 2n+1, 22n+1-1} is derived by New CRT-II with better performance compared to the reverse converter for the latest introduced 5 n-bit DR moduli set {2n-1, 2n, 2n+1, 2n-1-1, 2n+1-1}. Also, New CRT-I is used to achieve a high-performance reverse converter for the moduli set {2n-1, 2n+1, 22n, 22n+1}. This converter has less conversion delay and lower hardware requirements than the reverse converter for a recently suggested 6n-bit DR moduli set {2n-1, 2n+1, 22n-2, 22n+1-3} .

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TL;DR: In this article, the transimpedance limit describes the maximum transimpingance that a TIA can attain for a given bandwidth and technology, and the analysis includes a discussion of the conditions under which the limit is realizable.

Abstract: The transimpedance limit describes the maximum transimpedance that a transimpedance amplifier (TIA) can attain for a given bandwidth and technology. We analyze and compare this limit for a wide variety of TIA topologies thus exposing their relative merits. The topologies considered are the shunt-feedback TIA with single and multistage amplifier, the shunt-feedback TIA with feedback capacitor, the shunt-feedback TIA followed by a post amplifier, the shunt-feedback TIA with a current amplifier, the common-base/gate feedforward TIA, the shunt-feedback TIA with a common-base/gate input stage, and the shunt-feedback TIA with a regulated-cascode input stage. The analysis includes a discussion of the conditions under which the limit is realizable.

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TL;DR: Comparisons between adders based on full adders from the prior art and the ULPFA version demonstrate that the development outperforms the static CMOS and the CPL full adder, particularly in terms of power consumption and PDP by at least a factor of two.

Abstract: In this paper, we first propose a new structure of a hybrid full adder, namely, the branch-based logic and pass-transistor (BBL-PT) cell, which we implemented by combining branch-based logic and pass-transistor logic. Evolution of the proposed cell from its original version to an ultralow-power (ULP) cell is described. Quantitative comparisons of the optimized version, namely, the ULP full adder (ULPFA), are carried out versus the BBL-PT full adder and its counterparts in two well-known and commonly used logic styles, i.e., conventional static CMOS logic and complementary pass logic (CPL), in a 0.13-μm PD SOI CMOS with a supply voltage of 1.2 V, demonstrating power delay product (PDP) and static power performance that are more than four times better than CPL design. This could lead to tremendous benefit for multiplier application. The implementation of an 8-bit ripple carry adder based on the ULPFA is finally described, and comparisons between adders based on full adders from the prior art and our ULPFA version demonstrate that our development outperforms the static CMOS and the CPL full adders, particularly in terms of power consumption and PDP by at least a factor of two.

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TL;DR: A new (differential) entropy estimator for complex random variables by approximating the entropy estimate using a numerically computed maximum entropy bound, and a new complex independent component analysis algorithm, complex ICA by entropy-bound minimization (complex ICA-EBM), is introduced.

Abstract: We first present a new (differential) entropy estimator for complex random variables by approximating the entropy estimate using a numerically computed maximum entropy bound. The associated maximum entropy distributions belong to the class of weighted linear combinations and elliptical distributions, and together, they provide a rich array of bivariate distributions for density matching. Next, we introduce a new complex independent component analysis (ICA) algorithm, complex ICA by entropy-bound minimization (complex ICA-EBM), using this new entropy estimator and a line search optimization procedure. We present simulation results to demonstrate the superior separation performance and computational efficiency of complex ICA-EBM in separation of complex sources that come from a wide range of bivariate distributions.

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TL;DR: A built-in resistance compensator (BRC) technique is presented to speed up the charging time of a lithium-ion battery and the period of the CC stage can be extended to 40% of that of the original design.

Abstract: A built-in resistance compensator (BRC) technique is presented to speed up the charging time of a lithium-ion battery. A smooth control circuit (SCC) is proposed to ensure the stable transition from the constant-current (CC) to the constant-voltage (CV) stage. Due to the external parasitic resistance of the Li-ion battery-pack system, the charger circuit switches from the CC to the CV stage without fully charging the cell. The BRC technique dynamically estimates the external resistance to extend the CC stage. The experimental results show that the period of the CC stage can be extended to 40% of that of the original design. The charging time is effectively reduced.

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TL;DR: The global synchronization of a network whose isolate dynamics is of a particular form is studied and an extra condition on the ratio of the total activation time of self-synchronizing and nonsynchronizing subnetworks is needed to achieve synchronization of the entire switched network.

Abstract: This paper studies the local and global exponential synchronization of a complex dynamical network with switching topology and time-varying coupling delays. By using stability theory of switched systems and the network topology, the synchronization of such a network under some special switching signals is investigated. Firstly, under the assumption that all subnetworks are self-synchronizing, a delay-dependent sufficient condition is given in terms of linear matrix inequalities, which guarantees the solvability of the local synchronization problem under an average dwell time scheme. Then this result is extended to the situation that not all subnetworks are self-synchronizing. For the latter case, in addition to average dwell time, an extra condition on the ratio of the total activation time of self-synchronizing and nonsynchronizing subnetworks is needed to achieve synchronization of the entire switched network. The global synchronization of a network whose isolate dynamics is of a particular form is also studied. Three different examples of delayed dynamical networks with switching topology are given, which demonstrate the effectiveness of obtained results.

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TL;DR: The optimal compensation function, that minimizes the mean square error, is obtained in this paper in closed-form for the first time.

Abstract: Truncated multipliers compute the n most-significant bits of the n × n bits product. This paper focuses on variable-correction truncated multipliers, where some partial-products are discarded, to reduce complexity, and a suitable compensation function is added to partly compensate the introduced error. The optimal compensation function, that minimizes the mean square error, is obtained in this paper in closed-form for the first time. A sub optimal compensation function, best suited for hardware implementation, is introduced. Efficient multipliers implementation based on sub-optimal function is discussed. Proposed truncated multipliers are extensively compared with previously proposed circuits. Experimental results, for a 0.18 μm technology, are also presented.

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TL;DR: It is shown that the look-up-table (LUT)-multiplier-based approach, where the memory elements store all the possible values of products of the filter coefficients could be an area-efficient alternative to DA-based design of FIR filter with the same throughput of implementation.

Abstract: Distributed arithmetic (DA)-based computation is popular for its potential for efficient memory-based implementation of finite impulse response (FIR) filter where the filter outputs are computed as inner-product of input-sample vectors and filter-coefficient vector. In this paper, however, we show that the look-up-table (LUT)-multiplier-based approach, where the memory elements store all the possible values of products of the filter coefficients could be an area-efficient alternative to DA-based design of FIR filter with the same throughput of implementation. By operand and inner-product decompositions, respectively, we have designed the conventional LUT-multiplier-based and DA-based structures for FIR filter of equivalent throughput, where the LUT-multiplier-based design involves nearly the same memory and the same number of adders, and less number of input register at the cost of slightly higher adder-widths than the other. Moreover, we present two new approaches to LUT-based multiplication, which could be used to reduce the memory size to half of the conventional LUT-based multiplication. Besides, we present a modified transposed form FIR filter, where a single segmented memory-core with only one pair of decoders are used to minimize the combinational area. The proposed LUT-based FIR filter is found to involve nearly half the memory-space and $(1/N)$ times the complexity of decoders and input-registers, at the cost of marginal increase in the width of the adders, and additional $\sim(4N\times W)$ AND-OR-INVERT gates and $\sim(2N\times W)$ NOR gates. We have synthesized the DA-based design and LUT-multiplier based design of 16-tap FIR filters by Synopsys Design Compiler using TSMC 90 nm library, and find that the proposed LUT-multiplier-based design involves nearly 15% less area than the DA-based design for the same throughput and lower latency of implementation.

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TL;DR: Extensive simulation results verify that the proposed high-precision low-voltage adaptively biased low-dropout regulator with extended loop bandwidth achieves high loop bandwidth, fast line and load transient responses, high power supply rejection, and low output impedance.

Abstract: A high-precision low-voltage adaptively biased (AB) low-dropout regulator (LDR) with extended loop bandwidth is proposed. The multistage output-capacitor-free LDR is stabilized by Miller compensation and Q-reduction techniques to reduce the required minimum load current. Adaptive biasing is achieved by using direct current feedback from a simple current mirror. The dynamics of both the main feedback loop (MFL) and the adaptive biasing loop are thoroughly analyzed. Tradeoffs between the adaptive biasing factor and the MFL stability are discussed. The AB LDR is designed using a standard 0.35- ?m CMOS technology ( Vtn ? 0.52 V and Vtp ? -0.72 V). The output is 1.0 V, which delivers a maximum current of 100 mA. The minimum input voltage is 1.2 V, and the minimum load current required is reduced to 50 ?A . Extensive simulation results verify that the proposed LDR achieves high loop bandwidth, fast line and load transient responses, high power supply rejection, and low output impedance.

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TL;DR: A low-complexity message-passing algorithm, called Split-Row Threshold, is used to implement low-density parity-check (LDPC) decoders with reduced layout routing congestion and achieves improvements in area, throughput, and energy efficiency compared to a MinSum Normalized implementation.

Abstract: A low-complexity message-passing algorithm, called Split-Row Threshold, is used to implement low-density parity-check (LDPC) decoders with reduced layout routing congestion. Five LDPC decoders that are compatible with the 10GBASE-T standard are implemented using MinSum Normalized and MinSum Split-Row Threshold algorithms. All decoders are built using a standard cell design flow and include all steps through the generation of GDS II layout. An Spn = 16 decoder achieves improvements in area, throughput, and energy efficiency of 4.1 times, 3.3 times, and 4.8 times, respectively, compared to a MinSum Normalized implementation. Postlayout results show that a fully parallel Spn = 16 decoder in 65-nm CMOS operates at 195 MHz at 1.3 V with an average throughput of 92.8 Gbits/s with early termination enabled. Low-power operation at 0.7 V gives a worst case throughput of 6.5 Gbits/s-just above the 10GBASE-T requirement-and an estimated average power of 62 mW, resulting in 9.5 pj/bit. At 0.7 V with early termination enabled, the throughput is 16.6 Gbits/s, and the energy is 3.7 pJ/bit, which is 5.8× lower than the previously reported lowest energy per bit. The decoder area is 4.84 mm2 with a final postlayout area utilization of 97%.

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TL;DR: A comparative system-level overview is given of alternative class-D amplifier architectures and topological alternatives such as open-loop versus feedback and fixed-carrier versus self-oscillating are analyzed and compared in terms of relevant characteristics.

Abstract: A comparative system-level overview is given of alternative class-D amplifier architectures. The theory behind pulsewidth modulation and different modulation schemes is discussed. Topological alternatives such as open-loop versus feedback and fixed-carrier versus self-oscillating are analyzed and compared in terms of relevant characteristics, such as distortion, power supply rejection, efficiency, and electromagnetic interference. The combination of digital-to-analog conversion and class-D amplifiers is discussed. Experimental results of an integrated circuit based on a simple architecture that combines the benefits of digital input with an analog feedback loop are presented.

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TL;DR: A 40-Gb/s transimpedance amplifier (TIA) is proposed using multistage inductive-series peaking for low group-delay variation and demonstrates a transimpingance figure of merit of 200.7 Ω/pJ.

Abstract: A 40-Gb/s transimpedance amplifier (TIA) is proposed using multistage inductive-series peaking for low group-delay variation. A transimpedance limit for multistage TIAs is derived, and a bandwidth-enhancement technique using inductive-series π -networks is analyzed. A design method for low group delay constrained to 3-dB bandwidth enhancement is suggested. The TIA is implemented in a 0.13-μm CMOS process and achieves a 3-dB bandwidth of 29 GHz. The transimpedance gain is 50 dB·Ω , and the transimpedance group-delay variation is less than 16 ps over the 3-dB bandwidth. The chip occupies an area of 0.4 mm2, including the pads, and consumes 45.7 mW from a 1.5-V supply. The measured TIA demonstrates a transimpedance figure of merit of 200.7 Ω/pJ.

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TL;DR: Techniques for adaptive control of impedance-matching L networks are presented, which provide automatic compensation of antenna mismatch and renders calibration and elaborate software computation superfluous and allows for autonomous operation of adaptive antenna- matching modules.

Abstract: The link quality of mobile phones suffers from antenna mismatch due to fluctuating body effects. Techniques for adaptive control of impedance-matching L networks are presented, which provide automatic compensation of antenna mismatch. To secure reliable convergence, a cascade of two control loops is proposed for independent control of the real and imaginary parts of impedance. A secondary feedback path is used to enforce operation into a stable region when needed. These techniques exploit the basic properties of tunable series and parallel LC networks. A generic quadrature detector that offers a power-independent orthogonal reading of the complex impedance value is presented, which is used for direct control of variable capacitors. This approach renders calibration and elaborate software computation superfluous and allows for autonomous operation of adaptive antenna-matching modules.

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TL;DR: A new low power and improved speed TSPC 2/3 prescaler is proposed which is silicon verified and capable of operating up to 5 GHz and ideally, a 67% reduction of power consumption is achieved when compared under the same technology at supply voltage of 1.8 V.

Abstract: In this paper the power consumption and operating frequency of true single phase clock (TSPC) and extended true single phase clock (E-TSPC) frequency prescalers are investigated. Based on this study a new low power and improved speed TSPC 2/3 prescaler is proposed which is silicon verified. Compared with the existing TSPC architectures the proposed 2/3 prescaler is capable of operating up to 5 GHz and ideally, a 67% reduction of power consumption is achieved when compared under the same technology at supply voltage of 1.8 V. This extremely low power consumption is achieved by radically decreasing the sizes of transistors, reducing the number of switching stages and blocking the power supply to one of the D flip-flops (DFF) during Divide-by-2 operation. A divide-by-32/33 dual modulus prescaler implemented with this 2/3 prescaler using a chartered 0.18 ?m CMOS technology is capable of operating up to 4.5 GHz with a power consumption of 1.4 mW.