Showing papers in "IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing in 1996"

Weighted median filters: a tutorial

Abstract: Weighted Median (WM) filters have the robustness and edge preserving capability of the classical median filter and resemble linear FIR filters in certain properties. Furthermore, WM filters belong to the broad class of nonlinear filters called stack filters. This enables the use of the tools developed for the latter class in characterizing and analyzing the behavior and properties of WM filters, e.g. noise attenuation capability. The fact that WM filters are threshold functions allows the use of neural network training methods to obtain adaptive WM filters. In this tutorial paper we trace the development of the theory of WM filtering from its beginnings in the median filter to the recently developed theory of optimal weighted median filtering. Applications discussed include: idempotent weighted median filters for speech processing, adaptive weighted median and optimal weighted median filters for image and image sequence restoration, weighted medians as robust predictors in DPCM coding and Quincunx coding, and weighted median filters in scan rate conversion in normal TV and HDTV systems.

Subexpression sharing in filters using canonic signed digit multipliers

Abstract: A common way of implementing constant multiplication is by a series of shift and add operations. As is well known, if the multiplier is represented in Canonical Signed Digit (CSD) form, then the number of additions (or subtractions) used will be a minimum. This paper examines methods for optimizing the design of CSD multipliers, and in particular the gains that can be made by sharing subexpressions. In the case where several multipliers are present in a network of operators, for instance in an FIR filter, the savings achieved by identifying common subexpressions can be as much as 50% of the total number of operators. The asymptotic frequency of the most common subexpression is analyzed mathematically, and it is shown that sharing the two most common subexpressions can be expected to lead to a 33% saving of the number of additions.

A level-crossing sampling scheme for A/D conversion

Abstract: A sampling scheme that is based on multiple level-crossings is presented. This scheme generates samples of the input signal that are nonuniformly spaced in time by recording the time instants at which the signal crosses any of the fixed quantization levels. The nonuniform sample sequence is transformed to uniform samples by polynomial interpolation. The resolution is further increased by employing decimation. Various trade-offs involved in terms of speed, resolution and hardware complexity are discussed.

Area-time-power tradeoffs in parallel adders

Abstract: In this paper, several classes of parallel, synchronous adders are surveyed based on their power, delay and area characteristics. The adders studied include the linear time ripple carry and Manchester carry chain adders, the square-root time carry skip and carry select adders, the logarithmic time carry lookahead adder and its variations, and the constant time signed-digit and carry-save adders. Most of the research in the last few decades has concentrated on reducing the delay of addition. With the rising popularity of portable computers, however, the emphasis is on both high speed and low power operation. In this paper we adopt a uniform static CMOS layout methodology whereby short circuit power mininization is used as the optimization criterion. The relative merits of the different adders are evaluated by performing a detailed transistor-level simulation of the adders using HSPICE. Among the two's complement adders, a variation of the carry lookahead adder, called ELM, was found to have the best power-delay product. Based on the results of our experiments, a large adder design space is formulated from which an architect can choose an adder with the desired characteristics.

Area-efficient multipliers for digital signal processing applications

Abstract: An area-efficient parallel sign-magnitude multiplier that receives two N-bit numbers and produces an N-bit product, referred to as a truncated multiplier, is described. The quantization of the product to N bits is achieved by omitting about half the adder cells needed to add the partial products but in order to keep the quantization error to a minimum, probabilistic biases are obtained and are then fed to the inputs of the retained adder cells. The truncated multiplier requires approximately 50% of the area of a standard parallel multiplier. The paper then shows that this design strategy can also be applied for the design of two's-complement multipliers. The paper concludes with the application of the truncated multiplier for the implementation of a digital filter and it is shown that the signal-to-noise ratio of the digital filter using a truncated multiplier is better than that using a standard multiplier.

The design of log-domain filters based on the operational simulation of LC ladders

Abstract: A technique for the design of log-domain filters is introduced which is based on the operational simulation of LC ladders. The method is used to design a fifth-order Chebyshev and elliptic filter. HSPICE simulation results and experimental results are shown with emphasis on frequency behavior and linearity. The filters showed good correlation between the original filter specifications and the measured frequency response. They proved to be easily tunable and could be operated up to 1 MHz or one tenth of the f/sub T/ of the slowest transistor. Total harmonic distortion and intermodulation distortion was measured with results up to -47 and -55 dB, respectively.

A novel CMOS current conveyor realization with an electronically tunable current mode filter suitable for VLSI

Abstract: A novel CMOS realization of the second generation current conveyor is given. A circuit which compensates the voltage offset due to channel length modulation effect is then developed. The CCII is then used to realize a new electronically tunable low-pass-band-pass filter suitable for VLSI. Simulation results taking the second-order effects into account indicate the excellent performance of both the CCII circuit and the filter over a wide dynamic range.

Low voltage integrators for high-frequency CMOS filters using current mode techniques

Abstract: Low voltage CMOS fully differential integrators for high frequency continuous-time filters using current-mode techniques are presented. Current mode techniques are employed to avoid the use of the floating differential pair, in order to achieve operation at lower supply voltage levels. These high frequency integrators feature good supply noise rejection and power efficiency. Simulated and experimental results are presented verifying theoretical results. An example 10 MHz, 6 pole filter fabricated in 2 /spl mu/m CMOS consumes only 0.7 mW/pole and requires only a single 3.3 V supply voltage.

Oversampling parallel delta-sigma modulator A/D conversion

Abstract: Conventional delta-sigma analog-to-digital converters (/spl Delta//spl Sigma/ADC's) are widely used in low-bandwidth applications such as high-fidelity audio processing because they offer high-precision conversion yet are amenable to implementation using fine-line VLSI processes optimized for digital circuitry. However, their oversampling requirement so far has prevented their widespread application to higher bandwidth applications such as video processing. This paper extends a recently developed delta-sigma ADC architecture called the pi-delta-sigma ADC (/spl Pi//spl Delta//spl Sigma/ADC) that consists of multiple /spl Delta//spl Sigma/ modulator channels operating in parallel without time-interleaving. The extension developed in this paper allows for oversampling to be combined with parallelism such that an M-channel system with an oversampling ratio of N can achieve a conversion performance close to that of a conventional /spl Delta//spl Sigma/ADC with an oversampling ratio of M/spl times/N. Thus, for a given conversion precision, the architecture offers relaxed oversampling relative to conventional /spl Delta//spl Sigma/ADCs in return for increased analog circuit area. Moreover, as will be shown, the /spl Pi//spl Delta//spl Sigma/ADC retains much of the robustness of conventional /spl Delta//spl Sigma/ADC's with respect to nonideal circuit behavior.

FIR approximation of fractional sample delay systems

Abstract: This brief examines the approximation of fractional delays by FIR systems using various techniques which have previously been reported in the literature. In particular, the equivalence of the time-domain Lagrangian interpolation, the frequency-domain maximally flat error criterion and the window method is shown, provided maximal flatness is specified at /spl omega//sub 0/=0 and the window used is a scaled binomial function. The first of these has been known before, the second equivalence is new.

A frequency response, harmonic distortion, and intermodulation distortion test for BIST of a sigma-delta ADC

Abstract: Built-In-Self-Test (BIST) for VLSI systems is desirable for production-line testing and in-the-field diagnostics. This brief discusses a Mixed Analog-Digital BIST (MADBIST) for a frequency response test, a harmonic distortion test and an intermodulation distortion test of an analog-to-digital converter. The MADBIST strategy for the frequency response, harmonic distortion, and intermodulation distortion tests of the ADC is introduced, accuracy issues are discussed, and preliminary experimental results are presented.

The nonuniform discrete Fourier transform and its applications in filter design. II. 2-D

Abstract: For part I see ibid., vol. 43, no. 6, p. 422-33 (1996). The concept of the nonuniform discrete Fourier transform (NDFT) is extended to two dimensions to provide a basic framework for nonuniform sampling of 2-D sequences in the frequency domain. The 2-D NDFT of a sequence of size N/sub 1//spl times/N/sub 2/ is defined as samples of its 2-D z-transform evaluated at N/sub 1/N/sub 2/ distinct points located in the 4-D (z/sub 1/, z/sub 2/) space. These points are chosen appropriately so that the inverse transform exists. We discuss two special cases in which the choice of the sampling points is constrained so that the 2-D NDFT matrix is guaranteed to be nonsingular, and the number of operations required for computing its inverse is reduced, The 2-D NDFT is applied to nonuniform frequency sampling design of 2-D finite-impulse-response (FIR) filters. Nonseparable filters with good passband shapes and low peak ripples are obtained. This is illustrated by design examples, in which 2-D filters with various shapes are designed and compared with those obtained by other existing methods.

Analog fault diagnosis based on ramping power supply current signature clusters

Abstract: Measurement of power supply currents was found to be very useful for testing CMOS IC's because of its potential to detect a large class of manufacturing defects. However, this technique was used mainly for fault detection and was confined to digital circuits. In this paper, we present a suited methodology for fault diagnosis of analog circuits based on the observation of power supply currents. In the proposed technique, fault signature dictionaries are generated from the currents in the power supply bus. To obtain signatures rich in information for efficient diagnosis, the transistors in the circuit are forced to operate in all possible regions of operation by using a ramp signal at the supply instead of the conventional constant DC signal or ground voltage. The signatures are then clustered into different groups using a Kohonen neural network classifier. This technique has the potential to detect and diagnose single and multiple shorts as well as open circuits. The theoretical and experimental results of the proposed technique are verified using a CMOS Operational Transconductance Amplifier (OTA) circuit.

Structure generation of current-mode two integrator loop dual output-OTA grounded capacitor filters

Abstract: A variety of new current-mode continuous-time two integrator loop filter architectures incorporating dual output operational transconductance amplifiers (DO-OTA) and capacitors (C) are generated. These DO-OTA-C configurations consist of 2-6 DO-OTAs, depending on the structure and only 2 grounded capacitors. They are convenient for integration, suitable for high frequency, multifunctional, electronically tunable, of low sensitivity, simple in structure and easy to design. The selection of the filter structure and effects of DO-OTA nonidealities are discussed.

Overlapped block digital filtering

Abstract: Block digital filtering has been suggested to increase the parallelism of computation and to reduce the computational complexity of digital filtering systems. In this paper the block processing concept is generalized by considering overlapped input and/or output blocks. As an overlapped block digital filter is, in general, a shift-varying system, the conditions for its shift-invariant operation have been developed. These conditions have been exploited to derive computationally efficient shift-invariant block structures. Two types of fast FIR filtering algorithms using the overlapped block filter structures are derived. One is based on the adaptation of fast short-length linear convolution algorithms and the other is based on DFT algorithms. These algorithms not only reduce the computational complexity of filtering operations but also offer modular and parallel structures. Finite wordlength effects of FIR filters implemented using the overlapped block filter structure are also investigated.

Efficient implementation of an I-Q GMSK modulator

Abstract: An efficient implementation of GMSK modulators achieved by taking advantage of symmetry properties of the premodulation filter is described. The design bypasses typical processing steps such as modulating waveform ROM lookup, integration, and sine/cosine ROM lookup, and therefore does not introduce the related errors. A design for a cordless telephony IC with a bit rate of 72 kbps and 64 samples per symbol was implemented using only simple logic and 128/spl times/6 bits of ROM plus 2 simple 6b+sign DACs.

Complex behavior in digital filters with overflow nonlinearity: analytical results

Abstract: In this paper we present more analytical results about the complex behavior of a second order digital filter with overflow nonlinearity. We explore the parameter space to obtain a taxonomy of the different behaviors that occurs. In particular, we give a complete description of the chaotic behavior of the map F (which models the second order digital filter) in the parameter space (a,b). We prove that in the region R~/sub 5/ (the closure of R/sub 5/, where R/sub 5/={(a,b):b -1}) F is not chaotic; in the region |b| 1, if (a,b) are integers and b=-2(a-1), then F is an exact map. In addition, we obtain some results concerning the fractal behavior of the map F. We find an estimate of the Hausdorff dimension of the generalized hyperbolic attractor. We obtain results regarding the symbolic dynamics of F. For example, we prove that the set of points with aperiodic admissible sequences in the case |a|<2 and b=-1 is uncountable.

Fault observability analysis of analog circuits in frequency domain

Abstract: We study the testability of analog circuits in the frequency domain by introducing the analog fault observability concept. The proposed algorithm indicates the set of adequate test frequencies and test nodes to increase fault observability. This approach combines a structural testing methodology with functionality verification to increase the test effectiveness and consequently the design manufacturability and reliability. We analyze the case of single fault, double, and multiple faults. Concepts such as fault masking, fault dominance, fault equivalence, and non observable fault in analog circuits are defined and then used to evaluate testability. The theoretical aspect is based on the sensitivity approach.

A CMOS analog circuit for Gaussian functions

Abstract: A simple CMOS analog circuit that performs the Gaussian function for classification applications is introduced. Combining the exponential characteristics of MOS transistors in weak inversion and the square characteristics in strong inversion the function is built. Design constraints and mismatch effects are discussed, as well as the layout optimization. The circuit has been designed in a SOI technology and manufactured. Good experimental results are obtained which shows that the circuit is suitable to be included as a building block of an IC to perform classification tasks or other possible applications.

High performance CMOS current comparator design

Abstract: The paper describes some design aspects in the implementation of CMOS current comparators. More specifically, techniques for offset and charge-injection compensations are discussed in detail, and some basic topologies for compensated current comparators are presented and compared by SPICE simulations. Moreover, a novel compensated fully differential current comparator is proposed which achieves a very high performance. It provides a sensitivity as low as 20 nA and a switching time better than 30 ns with a 0.5 /spl mu/A input step current while dissipating 45 /spl mu/W.

Optimality conditions for truncated Kautz series

Abstract: Kautz functions constitute a complete orthonormal basis for square-summable functions both on a continuous as well as a discrete semi-infinite axis. A special case of the Kautz functions are the well-known Laguerre functions. The Kautz functions can be used as series expansions for causal impulse responses. Convergence of such series depends on the parameters in the Kautz functions. The conditions for the optimal parameters in a truncated Kautz series are derived.

A new hardware-efficient architecture for programmable FIR filters

Abstract: Although much research has been done on efficient high-speed filter architectures, much of this work has focused on filters with fixed coefficients, such as Canonical Signed Digit coefficient filter architectures, multiplierless designs, or memory-based designs. In this paper, we focus on digit-serial, high-speed architectures with programmable coefficients. To achieve high performance goals, we consider both of algorithm level and architecture implementation level of FIR filters. In algorithm level, we reformulate the FIR formulation in bit-level and take the associative property of the addition in both the digit-serial multiplications and filter formulations. In architecture level, we considered issues to implement the reformulated results efficiently. The issues include addition implementation, data flow arrangements, and treatment of sign-extensions. Based on the above considerations, we can obtain a filter architecture with accumulation-free tap structure and properties of short latency, flexible pipelinability and high speed. Comparing the cost and performance with previous designs, we find that the proposed architecture reduces the hardware cost of a programmable FIR filter to only half that of previous designs without sacrificing performance.

CAD tools for data converter design: an overview

Abstract: This paper presents an overview of the recent advances in modeling, simulation and structured synthesis that are pushing ahead the capabilities and efficiency of CAD tools for integrated data converter design. First, a hierarchical design methodology and a common framework with standardized interfaces are shown to be essential to create a design environment that is flexible enough to cover a wide range of specifications and applications. The different approaches for data converter modeling and simulation are then reviewed and compared, ranging from purely electrical simulators to state-of-the-art behavioral analog-digital simulators. In particular, it is shown how behavioral models of data converters are emerging as a powerful solution for complex system simulations with highly reduced computational requirements. Next, the key steps in the automatic synthesis of data converters are discussed, and state-of-the-art synthesis systems are compared and illustrated with some practical design examples. Finally, the progress in tools for testing and design for testability of data converters is described.

A fast convergence algorithm for adaptive FIR filters under computational constraint for adaptive tap-position control

Abstract: This paper proposes a fast convergence algorithm for adaptive FIR filters with tap-position control. The proposed algorithm consists of two stages: flat-delay estimation and constrained tap-position control. In the flat-delay estimation, the scattered coefficients are allowed to change their positions to achieve fast and correct flat-delay estimation. For constrained tap-position control, special attention is paid to a limit in computational power imposed by the hardware. By dividing a first-in-first-out queue into two parts, which store indexes to inactive taps with no assigned coefficient, fast convergence is achieved even when computation per sampling period for tap-position control is limited. Simulation results show that under the same computational limit as the conventional algorithm, the proposed algorithm reduces the convergence time by as much as 60%. The convergence speed remains unchanged for different computational limits. This algorithm is promising for echo cancellation in satellite links and in data transmission with modems.

CMOS class-AB current mirrors for precision current-mode analog-signal-processing elements

Abstract: CMOS class-AB current mirrors for high-precision current-mode analog-signal-processing elements are described. The class-AB configuration allows us to reduce the offset error caused by device mismatch, the nonlinearity distortion, and power consumption. The offset error due to the device mismatch is greatly reduced by the reduction of the bias current. The class-AB current-mirror has less sensitivity to the mismatch since the bias current relative to the signal current can be reduced. The excellent precision is confirmed by Monte Carlo simulation and SPICE based on 1 /spl mu/m CMOS LSI parameters.

Small-signal circuit analysis and sensitivity computations with the PVL algorithm

Abstract: We describe the application of the PVL algorithm to the small-signal analysis of circuits, including sensitivity computations. The PVL algorithm is based on the efficient computation of the Pade approximation of the network transfer function via the Lanczos process. The numerical stability of the algorithm permits the computation of the Pade approximation to any accuracy over a certain frequency range. We extend the algorithm to compute sensitivities of network transfer functions, their poles, and their zeros, with respect to arbitrary circuit parameters, with minimal additional computational cost. We demonstrate the implementation of our algorithm on circuit examples.

Exchange algorithms for the design of linear phase FIR filters and differentiators having flat monotonic passbands and equiripple stopbands

Abstract: The authors describe a modification of a technique proposed by Vaidyanathan (1985) for the design of filters having flat passbands and equiripple stopbands. The modification ensures that the passband is monotonic and does so without the use of concavity constraints. Another modification described in this brief adapts the method of Vaidyanathan to the design of low-pass differentiators having a specified degree of tangency at /spl omega/=0.

A hybrid digital signal processing-neural network CDMA multiuser detection scheme

Abstract: We present a new hybrid digital signal processing-neural network two-step multiuser detection scheme whose small computational complexity makes it attractive for real-time CDMA multiuser detection. An investigation on the nature of the local minima of the Optimal Multiuser Detector's (OMD) objective function leads to the development of an efficient algorithmic stage that can reduce significantly the size of the OMD optimization problem. This stage may then be followed by a Hopfield neural network employed to solve a smaller size residual problem of the same form. The performance of the hybrid detector is evaluated via simulations and it is shown to exceed that of other suboptimal receivers at a much lower computational cost in both synchronous and asynchronous CDMA transmission cases.

Adaptive filtering using filter banks

Abstract: This paper derives a theory for adaptive filters which operate on filter bank outputs, here called filter bank adaptive filters (FBAFs). It is shown how the FBAFs are a generalization of transform domain adaptive filters and adaptive filters based on structural subband decompositions. The minimum mean-square error performance and convergence properties of FBAFs are determined as a function of filter bank used. A parametrization for a class of FIR perfect reconstruction filter banks is derived which is used to design FBAF's having optimal error performance given prior knowledge of the application. Simulations are performed to illustrate the derived theory and demonstrate the improved error performance of the FBAFs relative to the LMS algorithm, when prior knowledge is incorporated.

Invariant image analysis based on Radon transform and SVD

Abstract: A Radon-based invariant image analysis method is introduced. The linearity, shift, rotation, and scaling properties of the Radon transform are utilized to achieve invariant features to translation, rotation, and scaling. The singular values of a matrix, constructed by row-stacking of projections, are used to construct the invariant feature vector. This feature vector will be used as input to a classifier, which is here, the back-propagation neural network followed by a maximum-output-selector. A performance function is introduced to evaluate the performance of the recognition system. This performance function can also be used to indicate how closely the pattern matches the decision template. The effectiveness of this method is illustrated by a simulation example and it is compared with the method of Zernike moments.