Showing papers in "IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing in 2002"

Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates

Abstract: Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. In this paper, we propose a technique to build a total of 41 new 10-transistor full adders using novel XOR and XNOR gates in combination with existing ones. We have done over 10,000 HSPICE simulation runs of all the different adders in different input patterns, frequencies, and load capacitances. Almost all those new adders consume less power in high frequencies, while three new adders consistently consume on average 10% less power and have higher speed compared with the previous 10-transistor full adder and the conventional 28-transistor CMOS adder. One draw back of the new adders is the threshold-voltage loss of the pass transistors.

Design of high-speed multiplierless filters using a nonrecursive signed common subexpression algorithm

Abstract: In this work, a new algorithm called nonrecursive signed common subexpression elimination (NR-SCSE) is discussed, and several applications in the area of multiplierless finite-impulse response (FIR) filters are developed. While the recursive utilization of a common subexpression generates a high logic depth into the digital structure, the NR-SCSE algorithm allows the designer to overcome this problem by using each subexpression once. The paper presents a complete description of the algorithm, and a comparison with two other well-known options: the graph synthesis, and the classical common subexpression elimination technique. Main results show that the NR-SCSE implementations of several benchmark circuits offer the best relation between occupied area and logic depth respect to the previous values published in the technical literature.

Speed-power-accuracy tradeoff in high-speed CMOS ADCs

Abstract: In this paper the fundamental tradeoff between speed, power, and accuracy for high-speed analog-to-digital converters (ADCs) is reviewed with respect to technology scaling. The never-ending story of complementary metal-oxide-semiconductor (CMOS) technology trends toward smaller transistor dimensions has resulted to date in deep submicron transistors with lower supply voltages. Supply voltage scaling and mismatch scaling trends are discussed and it is shown that in future technologies the power consumption of matching-dominated high-speed ADCs will increase to achieve the same accuracy and speed. Also, a comparison is made between slew-rate dominated circuits and settling dominated circuits. Finally, a comparison with published high-speed ADCs is presented using the figure of merit.

Improved switched tuning of differential CMOS VCOs

Abstract: Varactors for continuous frequency tuning are typically used in LC-oscillators. However, they have some drawbacks for large tuning ranges, such as high tuning sensitivity causing high sensitivity to noise and disturbances on the control voltage. Furthermore, large metal-oxide-semiconductor (MOS) varactors have high conversion of harmless amplitude noise into harmful phase noise. To reduce these problems a small varactor can be used in combination with MOS-transistors that switch fixed capacitors in and out of the oscillator. The limitations due to the imperfect complementary metal-oxide-semiconductor (CMOS) switches are investigated, and an improved structure for use with the popular differential CMOS LC-oscillator is presented.

Design of low-phase-noise CMOS ring oscillators

Abstract: This paper presents a framework for modeling the phase noise in complementary metal-oxide-semiconductor (CMOS) ring oscillators. The analysis considers both linear and nonlinear operations, and it includes both device noise and digital switching noise coupled through the power supply and substrate. In this paper, we show that fast rail-to-rail switching is required in order to achieve low phase noise. Further, flicker noise from the bias circuit can potentially dominate the phase noise at low offset frequencies. We define the effective Q factor for ring oscillators with large and nonlinear voltage swings and predict its increase for CMOS processes with smaller feature sizes. Our phase-noise analysis is validated via simulation and measurement results for ring oscillators fabricated in a number of CMOS processes.

Analysis of power recycling techniques for RF and microwave outphasing power amplifiers

Abstract: A power recycling technique has been analyzed for efficiency-enhanced radio-frequency (RF) and microwave outphasing power amplifiers for mobile wireless communications. By use of a simple power recycling network, a considerable portion of the wasted power can be recovered back to the power supply, and the enhancement of the overall power efficiency can be achieved without sacrificing the high-linearity performance of the amplifier system. An analysis and calculations have been conducted to optimize the recycling network for maximum power efficiency. The results predict a significant improvement on the overall power efficiency of the amplifier system for various modulations.

Analysis of jitter in phase-locked loops

Abstract: Jitter in clock signals is analyzed, linking noise in free-running oscillators to short-term and long-term time-domain behavior of phase-locked loops. Particular attention is given to comparing the impact of 1/f noise and white noise in oscillators and frequency dividers on jitter in phase-locked loops of first- and second-order. Theoretical analysis is supported by results obtained using mixed-signal behavior simulation.

On the design and implementation of FIR and IIR digital filters with variable frequency characteristics

Abstract: This paper studies the design and implementation of finite-impulse response (FIR) and infinite-impulse response (IIR) variable digital filters (VDFs), whose frequency characteristics can be controlled continuously by some control or tuning parameters. A least squares (LS) approach is proposed for the design of FIR VDFs by expressing the impulse response of the filter as a linear combination of basis functions. It is shown that the optimal LS solution can be obtained by solving a system of linear equations. By choosing the basis functions as piecewise polynomials, VDFs with larger tuning range than that of ordinary polynomial based approach results. The proposed VDF can be efficiently implemented using the familiar Farrow structure. Making use of the FIR VDF so obtained, an Eigensystem Realization Algorithm (ERA)-based model reduction technique is proposed to approximate the FIR VDF by a stable IIR VDF with lower system order. The advantages of the model reduction approach are: 1) it is computational simple which only requires the computation of the singular value decomposition of a Hankel matrix; 2) the IIR VDF obtained is guaranteed to be stable; and 3) the frequency response such as the phase response of the FIR prototype is well preserved. Apart from the above advantages, the proposed IIR VDF does not suffer from undesirable transient response during parameter tuning found in other approaches based on direct tuning of filter parameters. For frequency selective VDFs, about 40% of the multiplications can be saved using the IIR VDFs. The implementation of the proposed FIR VDF using sum-of-powers-of-two (SOPOT) coefficient and the multiplier block (MB) technique are also studied. Results show that about two-third of the additions in implementing the multiplication of the SOPOT coefficients can be saved using the multiplier block, which leads to significant savings in hardware complexity.

AM-to-PM conversion in varactor-tuned oscillators

Abstract: This brief deals with AM-to-PM noise conversion due to varactors and nonlinear capacitances. The effect increases the sensitivity of oscillators to substrate and power supply noise and sets a serious limitation to the phase noise performance of these stages when they are embedded in complete transceivers. A rigorous approach to the quantitative estimate of the conversion factor and a closed-form expression are derived. The conversion due to typical varactor structures available in integrated technology is discussed.

Maximally flat low-pass digital differentiator

Abstract: This paper describes the design of type III and type IV linear-phase finite-impulse response (FIR) low-pass digital differentiators according to the maximally flat criterion. We introduce a two-term recursive formula that enables the simple stable computation of the impulse response coefficients. The same recursive formula is valid for both Type III and Type IV solutions.

Implementation of steerable spatiotemporal image filters on the focal plane

Abstract: This paper presents an architectural overview of a pseudogeneral image processor (GIP) chip for realizing steerable spatial and temporal filters at the focal-plane. The convolution of the image with programmable kernels is realized with area-efficient and real-time circuits. The chip's architecture allows photoreceptor cells to be small and densely packed by performing all analog computations on the read-out, away from the array. The size, configuration, and coefficients of the kernels can be varied on the fly. In addition to the raw intensity image, the chip outputs four processed images in parallel. The convolution is implemented with a digitally programmable analog processor, resulting in very low-power consumption at high-computation rates. A 16/spl times/16 pixels prototype of the GIP has been fabricated in a standard 1.2-/spl mu/m CMOS process and its spatiotemporal capabilities have been successfully tested. The chip exhibits 1 GOPS/mW at 20 kft/s while computing four spatiotemporal convolutions in parallel.

Low-jitter clock multiplication: a comparison between PLLs and DLLs

Abstract: This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume more power per cell than their counterparts in the DLL. We can show that this effect is stronger than the notorious jitter accumulation effect that occurs in the voltage-controlled oscillator (VCO) of a PLL. First, an analysis of the stochastic-output jitter of the architectures, due to the most important noise sources, is presented. Then, another important source of jitter in a DLL-based clock multiplier is treated, namely the stochastic mismatch in the delay cells which compose the DLL voltage-controlled delay line (VCDL). An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. A circuit design technique, called impedance level scaling, is then presented which allows the designer to optimize the noise and mismatch behavior of a circuit, independently from other specifications such as speed and linearity. Applying this technique on a delay cell design yields a direct tradeoff between noise induced jitter and power usage, and between stochastic mismatch induced jitter and power usage.

Impact of technology scaling on CMOS logic styles

Abstract: In this paper, the main challenges of technology scaling are reviewed in depth Five popular logic families namely; conventional CMOS, complementary pass logic, Domino, differential cascode voltage switch logic, and current mode logic are presented, highlighting their advantages and drawbacks The behavior of each logic style in deep submicrometer technologies is analyzed and predicted for future technology generations To verify the qualitative analysis, simulations were performed on the basic logic gates, full adder and a 16-bit carry look ahead adder The circuits were implemented in 08-, 06-, 035-, and 025-/spl mu/m CMOS technologies, and optimized for minimum energy-delay product

Design of highly linear tunable CMOS OTA for continuous-time filters

Abstract: An analytical method based on the standard square-law metal-oxide-semiconductor (MOS) modeling for the design of highly linear, fully differential complementary metal-oxide-semiconductor (CMOS) operational transconductance amplifier (OTA) is presented. The proposed circuit implementation combines a cross-coupled quad cell and a source-coupled differential pair, as well as the current mirror technique in the output stage. As a result, improved linearity of the developed OTA over the large tuning range is obtained. SPICE simulations show that for 0.5-/spl mu/m HP AMOS14TB process (MOSIS) with a 2.5 V power supply, total harmonic distortion (THD) at 2.5V/sub pp/ is less than 0.5%. The dynamic range is equal to 76 dB at power consumption 5.7 mW. The alternative OTA structures are also discussed and compared to the basic version; for this circuit THD at 2.5V/sub pp/ is less than 0.2%, however, the circuit is much more sensitive to the transistor mismatch. As an example, the OTA is used to design a third-order elliptic lowpass filter in the high-frequency range. The cutoff frequency of the filter is tunable in the range of 4.6-29.6 MHz.

The design of hybrid carry-lookahead/carry-select adders

Abstract: In this paper, we present a general architecture for designing hybrid carry-lookahead/carry-select adders. Several previous adders in the literature are all special cases of this general architecture. They differ in the way Boolean functions for the carries are implemented. Based on the general architecture, we propose a new implementation of high-speed 56-bit hybrid adder. The new adder directly implements group carry propagates and group carry generators without individual carry generator/propagate signals. Moreover, the group carry generator/propagate signals are complemented to gain speed. The new implementation can be in static CMOS or dynamic logic style. The critical path length of our new design is about 2/3 of the critical path lengths of previous adders; therefore, higher speed can be gained.

An integrated optical transient sensor

Abstract: The implementation of a compact continuous-time optical transient sensor with commercial CMOS technology is presented. In its basic version, this sensor consists of a photodiode, five transistors and a capacitor. The proposed circuit produces several output signals in parallel. These include a sustained, logarithmically compressed measure of the incoming irradiance, half-wave rectified and thresholded contrast-encoding measures of positive and negative irradiance transients, and a signal that shows a combination of the sustained and the bidirectional transient response. The particular implementation reported in this work responds to abrupt irradiance changes with contrasts down to less than 1% for positive transients and 25% for negative transients. Circuit modifications leading to more symmetric contrast thresholds around 5% are also described. Due to their compactness these transient sensors are suitable for implementation in monolithic one- or two-dimensional imaging arrays. Such arrays may be used to sense local brightness changes of an image projected onto the circuit plane, which typically correspond to moving contours.

High-speed /spl Sigma//spl Delta/ modulators with reduced timing jitter sensitivity

Abstract: As higher and higher frequency signals are sampled, clock jitter limits the achievable signal-to-noise ratio (SNR) in an analog-to-digital converter (ADC). This clock jitter limit is reviewed for upfront sampled ADCs and continuous-time (CT) sigma-delta modulators (/spl Sigma//spl Delta/Ms). A pulse-shaped feedback digital-to-analog converter (DAC) is proposed to mitigate the jitter-imposed SNR limit in CT /spl Sigma//spl Delta/Ms. An intuitive analysis that compares the pulse-shaped DAC to conventional DACs is presented. This analysis as well as a more rigorous analysis shows that the pulse-shaped feedback /spl Sigma//spl Delta/M has potential for significant SNR improvement over conventional CT /spl Sigma//spl Delta/Ms as well as any upfront sampled system. For typical jitter, phase and amplitude noise numbers, SNR improvement is on the order of 17 dB over a conventional CT /spl Sigma//spl Delta/M and 8 dB over an upfront sampled ADC for a 1-GHz input.

A micropower low-distortion digital pulsewidth modulator for a digital class D amplifier

Abstract: We describe the design of a micropower digital pulsewidth modulator (PWM) for a hearing instrument class D amplifier. The PWM embodies a novel delta-compensation (/spl delta/C) sampling process and a novel pulse generator. The /spl delta/C process is sampled at the same low rate as reported algorithmic sampling processes and it features a similar low total harmonic distortion (THD). Its arithmetic computation is however, substantially simplified. We analytically derive the double Fourier series expression for the /spl delta/C process and show that the THD is low. The pulse generator is based on a hybrid 9-b counter 3-b tapped-delay-line. We investigate the compromise between the different design parameters that affect its power dissipation and THD. The complete proposed PWM features a simple circuit implementation (small IC area), micropower low voltage operation (/spl sim/22.1 /spl mu/W at 1.1 V), low sampling rate (48 kHz) and low harmonic distortion (/spl sim/0.2%), thereby rendering it suitable for a practical digital hearing instrument. We verify our design by means of computer simulations and on the basis of experimental measurements.

Improved design criteria of gain-boosted CMOS OTA with high-speed optimizations

Abstract: A comprehensive study on gain-boosted regulated cascode operational transconductance amplifiers (OTA) is discussed. These amplifiers are usually good for power optimized high-speed designs. However, location of an additional pole-zero pair in the transfer function makes the transient response much slower than expected. A new design is proposed along with the systematic approach which get rid of this pole-zero pair and deliberately puts a pair of complex poles to make the design faster.

Integrated echo and noise canceler for hands-free applications

Abstract: An integrated acoustic echo and noise canceler is proposed for hands-free telephony applications. The proposed system includes a computationally efficient double-talk detection (DTD) method and a residual echo cancellation algorithm. The DTD method uses two cross-correlation coefficients and is robust in adverse conditions. In the residual echo cancellation approach, a linear prediction error filter removes the short-term correlation of the residual echo and the resulting whitened residual echo is canceled by a noise-reduction filter. The proposed system was implemented using a general purpose digital signal processor (DSP) with 16-b arithmetic.

An HDR CMOS image sensor with spiking pixels, pixel-level ADC, and linear characteristics

Abstract: A high dynamic range (HDR) CMOS image sensor architecture based on spiking pixel cells and its first implementation, a linear 128-pixel sensor, is presented. The pulse rate of the pixel cell is proportional to the local light intensity. The pixel cell features a pixel-level analog-to-digital (A/D) conversion by pulse counting. It allows one to tradeoff conversion precision versus frame rate. Sample sensor chips have been manufactured using a 0.8-/spl mu/m double metal CMOS technology, and the test results confirming the feasibility of the chosen approach are reported.

Necessary and sufficient conditions for mismatch shaping in a general class of multibit DACs

Abstract: Multibit digital-to-analog converters (DACs) are often constructed by combining several 1-bit DACs of equal or different weights in parallel. In such DACs, component mismatches give rise to signal dependent error that can be viewed as additive DAC noise. In some cases these DACs use dynamic element matching techniques to decorrelate the DAC mismatch noise from the input sequence and suppress its power in certain frequency bands. Such DACs are referred to as mismatch-shaping DACs and have been used widely as enabling components in state-of-the-art /spl Delta//spl Sigma/ data converters. Several different mismatch-shaping DAC topologies have been presented, but theoretical analyses have been scarce and no general unifying theory has been presented in the previously published literature. This paper presents such a unifying theory in the form of necessary and sufficient conditions for a multibit DAC to be a mismatch-shaping DAC and applies the conditions to evaluate the DAC noise generated by several of the previously published mismatch-shaping DACs and qualitatively compare their behavior.

Analog VLSI neural network with digital perturbative learning

Abstract: Two feed-forward neural-network hardware implementations are presented. The first uses analog synapses and neurons with a digital serial weight bus. The chip is trained in loop with the computer performing control and weight updates. By training with the chip in the loop, it is possible to learn around circuit offsets. The second neural network also uses a computer for the global control operations, but all of the local operations are performed on chip. The weights are implemented digitally, and counters are used to adjust them. A parallel perturbative weight update algorithm is used. The chip uses multiple, locally generated, pseudorandom bit streams to perturb all of the weights in parallel. If the perturbation causes the error function to decrease, the weight change is kept; otherwise, it is discarded. Test results from a very large scale integration (VLSI) prototype are shown of both networks successfully learning digital functions such as AND and XOR.

Simultaneous voltage scaling and gate sizing for low-power design

Abstract: This paper presents a new approach using simultaneous voltage-scaling and gate-sizing for low power without violating the timing constraints. We provide the problem formulation in this application, and propose algorithms for single voltage-scaling, single gate-sizing, and their simultaneous manipulation. We target a globally optimal solution by showing how the power optimization is related to the maximum-weighted-independent-set (MWIS) problem. Experimental results on a set of benchmark circuits show that the simultaneous voltage-scaling and gate-sizing generates maximum power reduction. The average power savings range from 23% to 57% over all tested circuits, depending upon the circuit topology, underlying gate library and specific supply voltages.

A GSM/EDGE/WCDMA modulator with on-chip D/A converter for base stations

Abstract: A global system for mobile communication (GSM)/enhanced data rates for GSM evolution (EDGE)/wideband code division multiple access (WCDMA) modulator with a 14-bit on-chip digital-to-analog (D/A) converter is presented. The modulator consists of several digital signal processing building blocks, including a programmable pulse shaping filter, interpolation filters, resampler, co-ordinate rotation digital computer (CORDIC) rotator, programmable output power level controller and ramping unit, and x/sinx filter. The precompensation filter, which compensates the sinc droop above the Nyquist frequency, makes it possible to use WCDMA signal images for up-conversion. The new programmable up/down unit allows power ramping on a time-slot basis as specified for GSM, EDGE and time division duplex (TDD)-WCDMA. The multistandard modulator meets the spectral, phase and error vector magnitude (EVM) specifications. The die area of the chip is 22.09 mm/sup 2/ in 0.35-/spl mu/m CMOS technology. Power consumption is 1.7 W at 3.3 V with 110 MHz.

Multirate /spl Sigma//spl Delta/ modulators

Abstract: New high-speed /spl Sigma//spl Delta/ analog to digital converters (ADCs) are required for xDSL and RF receivers. As sampling frequency is upper limited by the amplifier bandwidth and power consumption, these high-speed, low-power converters operate with a small oversampling ratio. Usually, they are high-order cascade structures with a multibit quantizer in the last stage. All these approaches use a unique sampling frequency. This paper shows that multirating is a useful technique to reduce power consumption in high speed /spl Sigma//spl Delta/ modulators. To this end, two different multirate /spl Sigma//spl Delta/ modulators are proposed. The first one uses a low sampling frequency in the first integrator(s) of a single loop structure, while the second one uses a low oversampling frequency in the first stage(s) of a cascade converter.

Spectral analysis of time-domain phase jitter measurements

Abstract: A simplified overview of time-domain jitter measurements is presented in this paper. The relationship between the time-domain jitter measurements and the power spectrum of the phase jitter is described using fundamental Fourier properties and basic random variables analysis. This leads to a unifying analysis and the results are in agreement with commonly accepted understanding of jitter accumulation in oscillators. The presented analysis also provides the basis for comparing different jitter measurements.

Automatic calibration of modulated frequency synthesizers

Abstract: This paper describes a new approach to the automatic calibration of modulated phase-locked loop (PLL) frequency synthesizers. The new calibration approach tunes the response of the PLL while the synthesizer is in service and compensates for process and temperature variation. The availability of this new calibration method allows the use of precompensation techniques to achieve high data rate modulation of sigma-delta (/spl Sigma/-/spl Delta/) frequency synthesizers. The calibration method can be applied to Gaussian frequency shift keying (GFSK), Gaussian minimum shift keying (GMSK) modulation, and also M-ary FSK modulation. A low-frequency board level prototype has been constructed to validate the calibration approach.

A buffer-based baseband analog front end for CMOS bluetooth receivers

Abstract: A CMOS low-power baseband analog front end (BAFE) for an integrated bluetooth receiver is presented. The BAFE is designed using a new fully differential buffer (FDB) circuit that can effectively implement filters with gain/filtering interleaved operations. The BAFE utilizes five FDB circuits to implement a sixth-order low noise high linear prefilter, a sixth-order MOS-C tunable filter and a variable gain amplifier (VGA). The distribution of gain and filtering between the various blocks simplifies the design of the VGA stages and allows a good compromise between the input referred noise and the overall linearity. The analog front end is fabricated using a regular 1.2-/spl mu/m CMOS process and occupies an area of 1.7 mm /spl times/ 1.7 mm. Measurements results indicate that the total standby current consumption is less than 2.4 mA while providing a gain control range from 12-30 dB in 6-dB step. The input referred noise is less than 42 nV//spl radic/(Hz) and the out-of-band IIP3 of more than 12 dBm.

A low-voltage design approach for class AB current-mode circuits

Abstract: An approach for designing analog current-mode circuits with very-low supply voltage requirements is described and applied to the implementation of basic complementary metal-oxide-semiconductor (CMOS) building blocks. The method is based on a biasing circuit exploiting poly resistors and auxiliary differential amplifiers which restricts supply requirements to one threshold voltage plus three saturation voltages. As design examples, a complementary current mirror, a current operational amplifier, and a transconductor are implemented adopting the proposed technique. SPICE simulations using a 0.5-/spl mu/m process are provided which closely confirm the expected overall good performance of these circuits especially in terms of low-voltage capability and speed.