IEEE Transactions on Circuits and Systems Ii-express Briefs 

About: IEEE Transactions on Circuits and Systems Ii-express Briefs is an academic journal published by Institute of Electrical and Electronics Engineers. The journal publishes majorly in the area(s): Computer science & CMOS. It has an ISSN identifier of 1549-7747. Over the lifetime, 6307 publications have been published receiving 127728 citations. The journal is also known as: IEEE transactions on circuits and systems. & Express briefs.

State feedback controller design of networked control systems

Abstract: This paper is concerned with the controller design of networked control systems (NCS). A new model of the NCSs is provided under consideration of both the network-induced delay and the data packet dropout in the transmission. In terms of the given model, a controller design method is proposed based on a delay-dependent approach. The feedback gain of a memoryless controller and the maximum allowable value of the network-induced delay can be derived by solving a set of linear matrix inequalities. Two examples are given to show the effectiveness of our method.

MAGIC—Memristor-Aided Logic

Abstract: Memristors are passive components with a varying resistance that depends on the previous voltage applied across the device. While memristors are naturally used as memory, memristors can also be used for other applications, including logic circuits. In this brief, a memristor-only logic family, i.e., memristor-aided logic (MAGIC), is presented. In each MAGIC logic gate, memristors serve as an input with previously stored data, and an additional memristor serves as an output. The topology of a MAGIC nor gate is similar to the structure of a common memristor-based crossbar memory array. A MAGIC nor gate can therefore be placed within memory, providing opportunities for novel non-von Neumann computer architectures. Other MAGIC gates also exist (e.g., and , or , not , and nand ) and are described in this brief.

VTEAM: A General Model for Voltage-Controlled Memristors

Abstract: Memristors are novel electrical devices used for a variety of applications, including memory, logic circuits, and neuromorphic systems. Memristive technologies are attractive due to their nonvolatility, scalability, and compatibility with CMOS. Numerous physical experiments have shown the existence of a threshold voltage in some physical memristors. Additionally, as shown in this brief, some applications require voltage-controlled memristors to operate properly. In this brief, a Voltage ThrEshold Adaptive Memristor (VTEAM) model is proposed to describe the behavior of voltage-controlled memristors. The VTEAM model extends the previously proposed ThrEshold Adaptive Memristor (TEAM) model, which describes current-controlled memristors. The VTEAM model has similar advantages as the TEAM model, i.e., it is simple, general, and flexible, and can characterize different voltage-controlled memristors. The VTEAM model is accurate (below 1.5% in terms of the relative root-mean-square error) and computationally efficient as compared with existing memristor models and experimental results describing different memristive technologies.

Controller Synthesis for Positive Linear Systems With Bounded Controls

Abstract: This brief solves some synthesis problems for a class of linear systems for which the state takes nonnegative values whenever the initial conditions are nonnegative. In particular, the synthesis of state-feedback controllers is solved in terms of linear programming problem, including the requirement of positiveness of the controller and its extension to uncertain plants. In addition, the synthesis problem with nonsymmetrical bounds on the stabilizing control is treated

1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS

Abstract: We propose and demonstrate a 20-ps time-to-digital converter (TDC) realized in 90-nm digital CMOS. It is used as a phase/frequency detector and charge pump replacement in an all-digital phase-locked loop for a fully-compliant Global System for Mobile Communications (GSM) transceiver. The TDC core is based on a pseudodifferential digital architecture that makes it insensitive to nMOS and pMOS transistor mismatches. The time conversion resolution is equal to an inverter propagation delay, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with the estimation accuracy better than 1%. It additionally serves as a CMOS process strength estimator for analog circuits in this large system-on-chip. Measured integral nonlinearity is 0.7 least significant bits. The TDC consumes 5.3 mA raw and 1.3 mA with power management from a 1.3-V supply.