Showing papers in "IEEE Transactions on Circuits and Systems Ii-express Briefs in 2006"

1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS

Abstract: We propose and demonstrate a 20-ps time-to-digital converter (TDC) realized in 90-nm digital CMOS. It is used as a phase/frequency detector and charge pump replacement in an all-digital phase-locked loop for a fully-compliant Global System for Mobile Communications (GSM) transceiver. The TDC core is based on a pseudodifferential digital architecture that makes it insensitive to nMOS and pMOS transistor mismatches. The time conversion resolution is equal to an inverter propagation delay, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with the estimation accuracy better than 1%. It additionally serves as a CMOS process strength estimator for analog circuits in this large system-on-chip. Measured integral nonlinearity is 0.7 least significant bits. The TDC consumes 5.3 mA raw and 1.3 mA with power management from a 1.3-V supply.

Kickback noise reduction techniques for CMOS latched comparators

Abstract: The latched comparator is a building block of virtually all analog-to-digital converter architectures. It uses a positive feedback mechanism to regenerate the analog input signal into a full-scale digital level. The large voltage variations in the internal nodes are coupled to the input, disturbing the input voltage-this is usually called kickback noise. This brief reviews existing solutions to minimize the kickback noise and proposes two new ones. HSPICE simulations of comparators implemented in a 0.18-/spl mu/m technology demonstrate their effectiveness.

Global synchronization and asymptotic stability of complex dynamical networks

Abstract: Global synchronization and asymptotic stability of complex dynamical networks are investigated in this paper. Based on a reference state, a sufficient condition for global synchronization and stability is derived. Unlike other approaches where only local results were obtained, the complex network is not linearized in this paper. Instead, the sufficient condition for the global synchronization and asymptotical stability is obtained here by introducing a reference state with the Lyapunov stability theorem rather than the Lyapunov exponents, and this condition is simply given in terms of the network coupling matrix therefore is very convenient to use. Furthermore, the developed technique is applied to networks consisting of nodes with unknown but bounded nonlinear functions. A typical example of a complex network with chaotic nodes is finally used to verify the theoretical results and the effectiveness of the proposed synchronization scheme

Can threshold networks be trained directly

Abstract: Neural networks with threshold activation functions are highly desirable because of the ease of hardware implementation. However, the popular gradient-based learning algorithms cannot be directly used to train these networks as the threshold functions are nondifferentiable. Methods available in the literature mainly focus on approximating the threshold activation functions by using sigmoid functions. In this paper, we show theoretically that the recently developed extreme learning machine (ELM) algorithm can be used to train the neural networks with threshold functions directly instead of approximating them with sigmoid functions. Experimental results based on real-world benchmark regression problems demonstrate that the generalization performance obtained by ELM is better than other algorithms used in threshold networks. Also, the ELM method does not need control variables (manually tuned parameters) and is much faster.

Integrated Low-Loss CMOS Active Rectifier for Wirelessly Powered Devices

Abstract: A low-loss CMOS full-wave active rectifier is presented. It consists of two dynamically biased and symmetrically matched active diodes each realized by an nMOS switch driven by a 2-ns voltage comparator with reverse-current control. With a load of 1.8-kOmega, the rectified dc voltage is 3.22 V and 1.2 V for a 13.56 MHz ac sinusoidal input voltage of 3.5 V and 1.5 V respectively. It is fabricated in a 0.35-mum CMOS process with an active area of 0.0055 mm 2, with no low-threshold devices and on-chip passive components

Realization of a Constant Phase Element and Its Performance Study in a Differentiator Circuit

Abstract: A simple method for fabricating a constant phase element (CPE) has been discussed. Dependence of the phase angle on several physical parameters have also been elaborated. Finally, a fractional-order differentiator circuit has been constructed using the CPE, and its performance has been compared with the simulated results

Delay-dependent exponential stability of delayed neural networks with time-varying delay

Abstract: In this brief, free-weighting matrices are employed to express the relationship between the terms in the Leibniz-Newton formula; and based on that relationship, a new delay-dependent exponential-stability criterion is derived for delayed neural networks with a time-varying delay. Two numerical examples demonstrate the improvement this method provides over existing ones.

A high efficiency, soft switching DC-DC converter with adaptive current-ripple control for portable applications

Abstract: A novel control scheme for improving the power efficiency of low-voltage dc-dc converters for battery-powered, portable applications is presented. In such applications, light-load efficiency is crucial for extending battery life, since mobile devices operate in stand-by mode for most of the time. The proposed technique adaptively reduces the inductor current ripple with decreasing load current while soft switching the converter to also reduce switching losses, thereby significantly improving light-load efficiency and therefore extending the operation life of battery-powered devices. A load-dependent, mode-hopping strategy is employed to maintain high efficiency over a wide load range. Hysteretic (sliding-mode) control with user programmable hysteresis is implemented to adaptively regulate the current ripple and therefore optimize conduction and switching losses. Experimental results show that for a 1-A, 5- to 1.8-V buck regulator, the proposed technique achieved 5% power efficiency improvement (from 72% to 77%) at 100 mA of load current and a 1.5% improvement (from 84% to 85.5%) at 300 mA, which constitute light-load efficiency improvements, when compared to the best reported, state-of-the-art techniques. As a result, the battery life in a typical digital signal processing microprocessor application is improved by 7%, which demonstrates the effectiveness of the proposed solution.

A new LMI condition for delay-dependent asymptotic stability of delayed Hopfield neural networks

Abstract: In this paper, a new delay-dependent asymptotic stability condition for delayed Hopfield neural networks is given in terms of a linear matrix inequality, which is less conservative than existing ones in the literature. This condition guarantees the existence of a unique equilibrium point and its global asymptotic stability of a given delayed Hopfield neural network. Examples are provided to show the reduced conservatism of the proposed condition.

An Analysis of Latch Comparator Offset Due to Load Capacitor Mismatch

Abstract: This brief analyzes the effect of load capacitor mismatch on the offset of a regenerative latch comparator. Two analytical models are presented and compared with HSpice simulations. Our results indicate that in a typical 0.18-mum CMOS latch, a capacitive imbalance of only 1 fF can lead to offsets of several tens of millivolts

Multilevel Routing With Redundant Via Insertion

Abstract: This brief presents an improved multilevel full-chip routing system which integrates the redundant via placement in the routing flow for yield and reliability enhancement. The system features a pre-coarsening stage which is equipped with fast congestion-driven L-pattern global router followed by detailed router. The L-pattern global routing benefits to the reduction of vias and thus relieves the burden of redundant via addition. In addition, a rvia-driven maze routing algorithm is also integrated in the system to improve the insertion of redundant vias. Finally a redundant via placement heuristic is adopted to enhance the completion rate. We have tested the system on a set of commonly used benchmark circuits and compared the results with a previous multilevel routing system. Besides much enhancement obtained in the aspect of redundant via placement, the system also obtains high routing completion rate, minimized total wire length and total number of vias in satisfactory runtime

An LMI approach to exponential stability analysis of neural networks with time-varying delay

Abstract: This paper focuses on the problem of delay- dependent stability analysis of neural networks with variable delay. Two types of variable delay are considered: one is differentiable and has bounded derivative; the other one is continuous and may vary very fast. By introducing a new type of Lyapunov-Krasovskii functional, new delay-dependent sufficient conditions for exponential stability of delayed neural networks are derived in terms of linear matrix inequalities. We also obtain delay-independent stability criteria. These criteria can be tested numerically and very efficiently using interior point algorithms. Two examples are presented which show our results are less conservative than the existing stability criteria.

Nonlinear feedback control of chaos in permanent magnet synchronous motor

Abstract: Permanent magnet synchronous motor (PMSM) will demonstrate chaotic phenomena when its parameters fall into a certain area. The performance of PMSM will degrade because of chaos. Therefore, chaos should be suppressed or eliminated. According to the features of this practical plant, the drawbacks of existing control methods are analyzed, and the nonlinear feedback control method is suggested to control the chaos in PMSM. The nonlinear feedback principle is developed using the direct axis and the quadrature axis stator voltage as manipulated variables. The control target will become a unique asymptotically stable equilibrium under the nonlinear feedback principle, by this way, the controlled states can reach the target and the control objective can be implemented. This method can be physically realized using nonlinear state feedback. The control forces can be put into effect at any time. The target of the method may be any point in the strange attractor. The influence of the model error and the measurement noise upon the control performance is studied via simulations. Simulation results show the effectiveness of this method under the presence of the model error and the measurement noise

Accurate, Compact, and Power-Efficient Li-Ion Battery Charger Circuit

Abstract: A novel, accurate, compact, and power-efficient lithium-ion (Li-Ion) battery charger designed to yield maximum capacity, cycle life, and therefore runtime is presented and experimentally verified. The proposed charger uses a diode to smoothly (i.e., continuously) transition between two high-gain linear feedback loops and control a single power MOS device, automatically charging the battery with constant current and then constant voltage. An adaptive power-efficient charging scheme in the form of a cascaded switching regulator supply ensures the voltage across the charging power-intensive pMOS remains low, thereby reducing its power losses and yielding up to 27% better overall power efficiency. An 83% power-efficient printed circuit board prototype was built and used to charge several Li-Ion batteries to within plusmn0.43% of their optimum full-charge voltage and therefore within a negligibly small fraction of their full capacity

A Low-Power Digit-Based Reconfigurable FIR Filter

Abstract: In this brief, we present a digit-reconfigurable finite-impulse response (FIR) filter architecture with a very fine granularity. It provides a flexible yet compact and low-power solution to FIR filters with a wide range of precision and tap length. Based on the proposed architecture, an 8-digit reconfigurable FIR filter chip is implemented in a single-poly quadruple-metal 0.35-mum CMOS technology. Measurement results show that the fabricated chip operates up to 86 MHz when the filter draws 16.5 mW of power from a 2.5-V power supply

A free but efficient low-voltage class-AB two-stage operational amplifier

Abstract: A simple and efficient low-voltage two-stage operational amplifier with Class-AB output stage is introduced. It has a large effective output current boosting factor (/spl sim/50) and close to a factor 2 bandwidth enhancement. This is achieved at the expense of minimum increase in circuit complexity and no additional static power dissipation. Experimental verification of the characteristics of the proposed circuit is provided.

Observer Design for Lipschitz Nonlinear Systems: The Discrete-Time Case

Abstract: This brief deals with observer design for a class of discrete-time nonlinear systems, namely, linear systems with Lipschitz nonlinearities. Perhaps one of the main features, with respect to the existing results, is the use of new particular Lyapunov functions to deduce nonconservative conditions for asymptotic convergence of the state estimation errors. The established sufficient conditions are expressed in terms of linear matrix inequalities, which are easily and numerically tractable by standard software algorithms. By means of simple transformations, a reduced-order version is established where the observer gain is computed in an optimal manner. Performances of the proposed approach are illustrated through simulation and experimental results; one of them concerns synchronization of chaotic nonlinear models

Full-order and reduced-order observers for Lipschitz descriptor systems: the unified LMI approach

Abstract: This brief considers a new observer design for a class of continuous-time descriptor systems with Lipschitz constraint. Both types of full-order and reduced-order observers are constructed by a unified linear matrix inequality (LMI) approach. Under the sufficient condition in the form of LMI, the errors are guaranteed to be exponentially convergent. An illustrative example is presented to show the effectiveness of the proposed approach.

An Improved H α Filter Design for Systems With Time-Varying Interval Delay

Abstract: This brief is concerned with Hinfin filter design for systems with time-varying interval delay (i.e., the time delay is varying in an interval). An appropriate type of Lyapunov functionals is proposed to investigate the delay-dependent Hinfin filter design problem. Improved delay-dependent results are presented by taking into account the interval range. Finally, a numerical example is given to demonstrate the effectiveness and the benefits of the proposed method

Bias compensation based recursive least-squares identification algorithm for MISO systems

Abstract: For multi-input single-output output-error systems, the least-squares (LS) estimates are biased. In order to obtain the unbiased estimates, we present a recursive LS identification algorithm based on a bias compensation technique. The basic idea is to eliminate the estimation bias by adding a correction term in the LS estimates, and further to derive a bias compensation based recursive LS algorithm. Finally, we test the proposed algorithms by simulation and show their effectiveness.

A New Approach for the Design of Wideband Digital Integrator and Differentiator

Abstract: This brief presents a general theory of the Newton-Cotes digital integrators which is derived by applying the z-transform technique to the closed-form Newton-Cotes integration formula. Based on this developed theory, a new wideband third-order trapezoidal digital integrator is found to be a class of trapezoidal digital integrators. The novel wideband third-order trapezoidal integrator accurately approximates the ideal integrator over the whole Nyquist frequency range and compares favourably with existing integrators. Based on the designed wideband third-order trapezoidal integrator, a new wideband digital differentiator is designed, which approximates the ideal differentiator reasonably well over the whole Nyquist frequency range and compares favourably with existing differentiators. The low orders and high accuracies of the novel wideband trapezoidal integrator and the new wideband differentiator make them attractive for real-time applications

Capacitive Inter-Chip Data and Power Transfer for 3-D VLSI

Abstract: We report on inter-chip bidirectional communication and power transfer between two stacked chips. The experimental prototype system components were fabricated in a 0.5-mum silicon-on-sapphire CMOS technology. Bi-directional communication between the two chips is experimentally measured at 1Hz-15 MHz. The circuits on the floating top chip are powered with capacitively coupled energy using a charge pump. This is the first demonstration of simultaneous nongalvanic power and data transfer between chips in a stack. The potential use in 3-D VLSI is aimed at reducing costs and complexity that are associated with galvanic inter-chip vias in 3-D integration

Reversed Temperature-Dependent Propagation Delay Characteristics in Nanometer CMOS Circuits

Abstract: The supply voltage to threshold voltage ratio is reduced with each new technology generation. The gate overdrive variation with temperature plays an increasingly important role in determining the speed characteristics of CMOS integrated circuits. The temperature-dependent propagation delay characteristics, as shown in this brief, will experience a complete reversal in the near future. Contrary to the older technology generations, the speed of circuits in a 45-nm CMOS technology is enhanced when the temperature is increased at the nominal supply voltage. Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable operation under temperature fluctuations. A design methodology based on optimizing the supply voltage for temperature-variation-insensitive circuit performance is proposed in this brief. The optimum supply voltage is 45% to 53% lower than the nominal supply voltage in a 180-nm CMOS technology. Alternatively, the optimum supply voltage is 15% to 35% higher than the nominal supply voltage in a 45-nm CMOS technology. The speed and energy tradeoffs in the supply voltage optimization technique are also presented

A Simple Subthreshold CMOS Voltage Reference Circuit With Channel- Length Modulation Compensation

Abstract: This brief presents a simple reference circuit with channel-length modulation compensation to generate a reference voltage of 221 mV using subthreshold of MOSFETs at supply voltage of 0.85 V with power consumption of 3.3 muW at room temperature using TSMC 0.18-mum technology. The proposed circuit occupied in less than 0.0238 mm 2 achieves the reference voltage variation of 2 mV/V for supply voltage from 0.9 to 2.5V and about 6 mV of temperature variation in the range from -20degC to 120 degC. The agreement of simulation and measurement data is demonstrated

On the Optimum Constructions of Composite Field for the AES Algorithm

Abstract: In the hardware implementations of the Advanced Encryption Standard (AES) algorithm, employing composite field arithmetic not only reduces the complexity but also enables deep subpipelining such that higher speed can be achieved. In addition, it is more efficient to employ composite field arithmetic only in the SubBytes transformation of the AES algorithm. Composite fields can be constructed by using different irreducible polynomials. Nevertheless, how the different constructions affect the complexity of the composite implementation of the SubBytes has not been analyzed in prior works. This brief presents 16 ways to construct the composite field GF(((22)2)2) for the AES algorithm. Analytical results are provided for the effects of the irreducible polynomial coefficients on the complexity of each involved subfield operation. In addition, for each construction, there exist eight isomorphic mappings that map the elements in GF(28) to those in composite fields. The complexities of these mappings vary. An efficient algorithm is proposed in this brief to find all isomorphic mappings. Based on the complexities of both the subfield operations and the isomorphic mappings, the optimum constructions of the composite field for the AES algorithm are selected to minimize gate count and critical path

Markov Chains-Based Derivation of the Phase Detector Gain in Bang-Bang PLLs

Abstract: Due to the presence of a binary phase detector (BPD) in the loop, bang-bang phase-locked loops (BBPLLs) are hard nonlinear systems. Since the BPD is usually also the only nonlinear element in the loop, in practical applications, BBPLLs are commonly analyzed by first linearizing the BPD and then using the traditional mathematical techniques for linear systems. To the author's knowledge, in the literature, the gain of the linearized BPD (Kbpd) is determined neglecting the effect of the BBPLL dynamics on the effective jitter seen by the BPD. In this brief, we develop an approach to the determination of Kbpd which takes into consideration also this effect. The approach is based on modeling the dynamics of a BBPLL as a Markov chain. This approach gives new insights into the behavior of the BBPLL and leads to an expression for the Kbpd, which is more general than the one currently known in literature

New Curvature-Compensation Technique for CMOS Bandgap Reference With Sub-1-V Operation

Abstract: A new sub-1-V curvature-compensated CMOS bandgap reference, which utilizes the temperature-dependent currents generated from the parasitic n-p-n and p-n-p bipolar junction transistor devices in the CMOS process, is presented. The new proposed sub-1-V curvature-compensated CMOS bandgap reference has been successfully verified in a standard 0.25-mum CMOS process. The experimental results have confirmed that, with the minimum supply voltage of 0.9 V, the output reference voltage at 536 mV has a temperature coefficient of 19.5 ppm/degC from 0 degC to 100 degC. With a 0.9-V supply voltage, the measured power noise rejection ratio is -25.5 dB at 10 kHz

Delay-Dependent Robust $H_{\infty}$ Filtering for Uncertain Discrete-Time Systems With Time-Varying Delay Based on a Finite Sum Inequality

Abstract: This brief is concerned with delay-dependent robust Hinfin filtering for uncertain discrete-time systems with time-varying delay. The uncertainty is of convex polytopic type. By establishing a finite sum inequality based on quadratic terms, a new delay-dependent bounded real lemma (BRL) is derived. In combination with a parameter-dependent Lyapunov-Krasovskii functional, which allows the Lyapunov-Krasovskii matrices to be vertex dependent, the obtained BRL is modified into a new version to suit for convex polytopic uncertainties. Neither model transformation nor bounding technique for cross terms is involved. Based on the new BRL, the designed filter is provided in terms of a linear matrix inequality (LMI), which is easily solved by Matlab LMI toolbox. A numerical example is given to illustrate the effectiveness of the proposed method

Bandwidth Mismatch and Its Correction in Time-Interleaved Analog-to-Digital Converters

Abstract: The sample-and-hold amplifier in each channel of a time-interleaved analog-to-digital converter system has finite bandwidth, and these bandwidths may be mismatched. This paper analyzes the effect of such mismatches. Correction for bandwidth mismatch in the digital domain is described and demonstrated

High-Performance Repetitive Control of PWM DC-AC Converters With Real-Time Phase-Lead FIR Filter

Abstract: The significance of phase-lead compensation is revealed for repetitive control systems in terms of tracking accuracy and transient. A real-time noncausal phase-lead FIR filter is proposed to improve the performance of add-on repetitive controlled constant-voltage constant-frequency PWM dc-ac converters. The experiment results show that nearly perfect tracking, low total harmonics distortion, and satisfactory transient are achieved in the proposed repetitive-controlled PWM converter under both linear load and rectifier load