Showing papers in "IEEE Transactions on Circuits and Systems Ii-express Briefs in 2007"
TL;DR: The synthesis of state-feedback controllers is solved in terms of linear programming problem, including the requirement of positiveness of the controller and its extension to uncertain plants.
Abstract: This brief solves some synthesis problems for a class of linear systems for which the state takes nonnegative values whenever the initial conditions are nonnegative. In particular, the synthesis of state-feedback controllers is solved in terms of linear programming problem, including the requirement of positiveness of the controller and its extension to uncertain plants. In addition, the synthesis problem with nonsymmetrical bounds on the stabilizing control is treated
424 citations
TL;DR: A high slew-rate amplifier with push-pull output driving capability is proposed to enable an ultra-low quiescent current (Iq ~ 1muA) low-dropout (LDO) regulator with improved transient responses to improve stability of LDO regulators without using any on-chip and off-chip compensation capacitors.
Abstract: A high slew-rate amplifier with push-pull output driving capability is proposed to enable an ultra-low quiescent current (Iq ~ 1muA) low-dropout (LDO) regulator with improved transient responses. The proposed amplifier eliminates the tradeoff between small Iq and large slew-rate that is imposed by the tail-current in conventional amplifier design. Push-pull output stage is introduced to enhance the output driving ability. Small dropout voltage (Vbo) with large-size pass transistor and ultra-low Iq can thus be used to minimize power loss of LDO regulator without transient-response degradation. The proposed amplifier helps to improve stability of LDO regulators without using any on-chip and off-chip compensation capacitors. This is beneficial to chip-level power management requiring high-area efficiency. An LDO regulator with the proposed amplifier has been implemented in a 0.18- mum standard CMOS process and occupies 0.09 mm2. The LDO regulator can deliver 50-mA load current at 1-V input and ~ 100-mV VDO . It only consumes 1.2 muA Iq and is able to recover within ~ 4 mus even under the worst case scenario.
221 citations
TL;DR: This brief presents a highly integrated wirelessly powered battery charging circuit for miniature lithium (Li)-ion rechargeable batteries used in medical implant applications that employs a new control loop that relaxes comparator resolution requirements, provides simultaneous operation of constant-current and constant-voltage loops, and eliminates the external current sense resistor from the charging path.
Abstract: This brief presents a highly integrated wirelessly powered battery charging circuit for miniature lithium (Li)-ion rechargeable batteries used in medical implant applications. An inductive link and integrated Schottky barrier rectifying diodes are used to extract the DC signal from a power carrier while providing low forward voltage drop for improved efficiency. The battery charger employs a new control loop that relaxes comparator resolution requirements, provides simultaneous operation of constant-current and constant-voltage loops, and eliminates the external current sense resistor from the charging path. The accuracy of the end-of-charge (EOC) detection is primarily determined by the voltage drop across matched resistors and current-sources and the offset voltage of the sense comparator. Experimental results in 0.6-mum 3M-2P CMOS technology indicate that plusmn1.3% (or plusmn20 muA) EOC accuracy can be obtained under worst case conditions for a comparator offset voltage of plusmn5 mV. The circuit measures roughly 1.74 mm2 and dissipates 8.4 mW in the charging phase while delivering a load current of 1.5 mA at 4.1 V (or 6.15 mW) for an efficiency of 73%.
215 citations
TL;DR: An exponential stability criterion given in terms of a set of linear matrix inequalities, together with a simpler sufficient condition determined by three scalar inequalities, is presented to solve the exponential stabilization problem for a class of nonlinear systems.
Abstract: This brief studies the exponential stabilization problem for a class of nonlinear systems by means of periodically intermittent control. An exponential stability criterion given in terms of a set of linear matrix inequalities, together with a simpler sufficient condition determined by three scalar inequalities, is presented. A suboptimal intermittent controller is designed with respect to the general cost function under the assumption that the control period and control width are fixed and known. Numerical simulations are presented to verify the theoretical results.
210 citations
TL;DR: Experimental results have confirmed that, at a minimum supply voltage of 600 mV, lower than the threshold voltage, the topology presents almost rail-to-rail input and output swings and consumes only 550 nW.
Abstract: An ultra-low-voltage ultra-low-power CMOS Miller operational transconductance amplifier (OTA) with rail-to-rail input/output swing is presented The topology is based on combining bulk-driven differential pair and dc level shifters, with the transistors work in weak inversion The improved Miller OTA has been successfully verified in a standard 035-mum CMOS process Experimental results have confirmed that, at a minimum supply voltage of 600 mV, lower than the threshold voltage, the topology presents almost rail-to-rail input and output swings and consumes only 550 nW
186 citations
TL;DR: A two-stage ultra-wide-band CMOS low-noise amplifier (LNA) presented, with the common-gate configuration employed as the input stage, the broad-band input matching is obtained and the noise does not rise rapidly at higher frequency.
Abstract: A two-stage ultra-wide-band CMOS low-noise amplifier (LNA) is presented. With the common-gate configuration employed as the input stage, the broad-band input matching is obtained and the noise does not rise rapidly at higher frequency. By combining the common-gate and common-source stages, the broad-band characteristic and small area are achieved by using two inductors. This LNA has been fabricated in a 0.18-mum CMOS process. The measured power gain is 11.2-12.4 dB and noise figure is 4.4-6.5 dB with -3-dB bandwidth of 0.4-10 GHz. The measured IIP3 is -6 dBm at 6 GHz. It consumes 12 mW from a 1.8-V supply voltage and occupies only 0.42 mm2
166 citations
TL;DR: The proposed 7T SRAM cell reduces the activity factor of discharging the bit line pair to perform a write operation, and Experimental results using HSPICE simulation shows that the write power saving is at least 49%.
Abstract: On-chip cache consumes a large percentage of the whole chip area and expected to increase in advanced technologies. Charging/discharging large bit lines capacitance represents a large portion of power consumption during a write operation. We propose a novel write mechanism which depends only on one of the two bit lines to perform a write operation. Therefore, the proposed 7T SRAM cell reduces the activity factor of discharging the bit line pair to perform a write operation. Experimental results using HSPICE simulation shows that the write power saving is at least 49%. Both read delay and static noise margin are maintained after carefully sizing the cell transistors
155 citations
TL;DR: The design procedure is based on the analogy between a type-II second-order analog PLL and an all-digital PLL, which inherits the frequency response and stability characteristics of the analog prototype PLL.
Abstract: In this brief, a systematic design procedure for a second-order all-digital phase-locked loop (PLL) is proposed. The design procedure is based on the analogy between a type-II second-order analog PLL and an all-digital PLL. The all-digital PLL design inherits the frequency response and stability characteristics of the analog prototype PLL
153 citations
TL;DR: Experimental results show that the proposed video watermarking scheme can robustly survive transcoding process and strong common signal processing attacks, such as bit-rate reduction, Gaussian filtering and contrast enhancement.
Abstract: A robust video watermarking scheme of the state-of-the-art video coding standard H.264/AVC is proposed in this brief. 2-D 8-bit watermarks such as detailed company trademarks or logos can be used as inconvertible watermark for copyright protection. A grayscale watermark pattern is first modified to accommodate the H.264/AVC computational constraints, and then embedded into video data in the compressed domain. With the proposed method, the video watermarking scheme can achieve high robustness and good visual quality without increasing the overall bit-rate. Experimental results show that our algorithm can robustly survive transcoding process and strong common signal processing attacks, such as bit-rate reduction, Gaussian filtering and contrast enhancement
142 citations
TL;DR: This work presents a novel formulation of the decoding algorithm that strongly simplifies internal communication requirements and enables the development of decoders supporting generally defined LDPC codes, and the resulting architecture is tailored to decode both IEEE 802.11n and IEEE802.16eLDPC codes.
Abstract: Low-density parity-check codes (LDPC) are among the most powerful error correcting tools today available. For this reason they became very popular in several applications such as the digital satellite broadcasting system (DVB-S2), wireless local area network (IEEE 802.11n) and metropolitan area network (802.16e). Whereas several code-specific decoders have been proposed in the literature, the implementation of a high performance yet flexible LDPC decoder still is a challenging topic. This work presents a novel formulation of the decoding algorithm that strongly simplifies internal communication requirements and enables the development of decoders supporting generally defined LDPC codes. The resulting architecture is tailored to decode both IEEE 802.11n and IEEE 802.16e LDPC codes, as well as any other code of comparable complexity. The implementation cost deriving from the full flexibility offered by the proposed approach is also evaluated.
139 citations
TL;DR: A transformer-based resonator is proposed to be used to build a dual-mode oscillator, e.g., a system capable of oscillating at two different frequencies without recurring to switched inductors, switched capacitors, or varactors.
Abstract: In this brief, we propose to use a transformer-based resonator to build a dual-mode oscillator, e.g., a system capable of oscillating at two different frequencies without recurring to switched inductors, switched capacitors, or varactors. The behavior of the resonator configured as a one-port and a two-port network is studied analytically, and the dependence of the quality factor on the design parameters is thoroughly explored. These results, combined with the use of traditional frequency tuning techniques, are applied to the design of a wide-band voltage-controlled oscillator (VCO) that covers the frequency range 3.6-7.8 GHz. The performance of the designed VCO, implemented in a digital 0.13-mum CMOS technology, has been studied by transistor-level and 2.5D electromagnetic simulation (Agilent Momentum). A typical phase noise performance at 1-MHz offset of -104 dBc/Hz has been predicted, while the power consumption ranges from 1 to 8 mW, depending on the VCO configuration
TL;DR: The described method uses ambiguity set concept and evolutionary computations to determine the optimal set of analog test points and the efficiency of the technique is compared with a method based on entropy index.
Abstract: A new approach to an optimal analog test points selection is proposed. The described method uses ambiguity set concept and evolutionary computations to determine the optimal set of analog test points. After a brief introduction to analog testing and genetic algorithms, the proposed strategy is explained. The presented evolutionary approach is illustrated by a practical example of analog circuit and by a series of hypothetical circuits. The efficiency of the technique is compared with a method based on entropy index, and the obtained results are discussed
TL;DR: In this brief, the design of a low-power inductorless wideband low-noise amplifier (LNA) for worldwide interoperability for microwave access covering the frequency range from 0.1 to 3.8 GHz using 0.13-mum CMOS is described.
Abstract: In this brief, the design of a low-power inductorless wideband low-noise amplifier (LNA) for worldwide interoperability for microwave access covering the frequency range from 0.1 to 3.8 GHz using 0.13-mum CMOS is described. The core consumes 1.9 mW from a 1.2-V supply. The chip performance achieves S11 below -10 dB across the entire band and a minimum noise figure of 2.55 dB. The simulated third-order input intercept point is -2.7 dBm. The voltage gain reaches a peak of 11.2 dB in-band with an upper 3-dB frequency of 3.8 GHz, which can be extended to reach 6.2 GHz using shunt inductive peaking. A figure of merit is devised to compare the proposed designs to recently published wideband CMOS LNAs
TL;DR: Novel techniques used in the all-digital PLL to achieve an ultra-fast frequency acquisition of <50 mus while maintaining excellent phase noise and spurious performance during transmission and reception are presented.
Abstract: A fully digital frequency synthesizer for RF wireless applications has recently been proposed At its foundation lies a digitally controlled oscillator with sufficiently fine frequency resolution to avoid analog tuning The conventional phase/frequency detector, charge pump and RC loop filter are replaced by a time-to-digital converter and a simple digital loop filter When implemented in highly scaled digital CMOS processes, the proposed architecture is more advantageous over conventional charge-pump-based phase-locked loops (PLLs) since it exploits signal processing capabilities of digital circuits and avoids relying on the fine voltage resolution of analog circuits In this brief, we present novel techniques used in the all-digital PLL to achieve an ultra-fast frequency acquisition of <50 mus while maintaining excellent phase noise and spurious performance during transmission and reception This approach has been validated and incorporated in commercial single-chip Bluetooth and Global System for Mobile Communications radios realized in deep-submicrometer CMOS
TL;DR: Three RNS-to-binary converters are proposed for a new powers-of-two related three-moduli set: one using mixed radix conversion and the other two using Chinese remainder theorem.
Abstract: In this brief, the design of residue number system (RNS) to binary converters for a new powers-of-two related three-moduli set {2n+1 - 1, 2n, 2n - 1} is considered. This moduli set uses moduli of uniform word length (n to n + 1 bits). It is derived from a previously investigated four-moduli set {2n - 1, 2n, 2n + 1, 2n +1 - 1}. Three RNS-to-binary converters are proposed for this moduli set: one using mixed radix conversion and the other two using Chinese remainder theorem. Detailed architectures of the three converters as well as comparison with some earlier proposed converters for three-moduli sets with uniform word length and the four-moduli set {2n - 1, 2n, 2n + 1, 2n+1 - 1} are presented.
TL;DR: Lower bounds for problems related to realizing multiplication by constants with shifts, adders, and subtracters are presented and have applications in proving the optimality of solutions obtained by heuristics.
Abstract: Lower bounds for problems related to realizing multiplication by constants with shifts, adders, and subtracters are presented. These lower bounds are straightforwardly calculated and have applications in proving the optimality of solutions obtained by heuristics.
TL;DR: This brief presents a method of deploying RF switch-mode power amplification for varying envelope signals in a novel configuration of a low-pass DeltaSigma modulator using a phase modulated clock combined with a simple AND-gate.
Abstract: This brief presents a method of deploying RF switch-mode power amplification for varying envelope signals. Thereby the power amplifier can be operated as a switch with a high power efficiency as the result. The key idea is to transmit either a full RF period or none at all in such a way that the correct modulated RF signal is obtained after filtering. This is accomplished in a novel configuration of a low-pass DeltaSigma modulator using a phase modulated clock combined with a simple AND-gate. The designed modulator is easy to implement, displays very good linearity and offers time domain signals that promote the power efficiency of the power amplifier. The working principle is described through theory and simulations, and validation is done via measurements on a prototype of the modulator. Measurements on the prototype show that the presented modulator modulates a UMTS signal with more than 10-dB margin to the spectrum mask and EVM below 0.85% RMS (req<17.5%). Delta-sigma, power amplifier (PA), RF, switch mode, transmitter architecture, varying envelope.
TL;DR: New criteria for the uniqueness and global robust exponential stability are established for the equilibrium point of interval recurrent neural networks with multiple time-varying delays via a decomposition method and analysis technique.
Abstract: New criteria for the uniqueness and global robust exponential stability are established for the equilibrium point of interval recurrent neural networks with multiple time-varying delays via a decomposition method and analysis technique. Results are presented in the form of linear matrix inequality, which can be solved efficiently. Two numerical examples are employed to show the effectiveness of the present results.
TL;DR: A new three inputs and single output voltage-mode universal biquadratic filter with high-input and low-output impedance using three plus-type differential difference current conveyors, two grounded capacitors and two grounded resistors is presented.
Abstract: A new three inputs and single output voltage-mode universal biquadratic filter with high-input and low-output impedance using three plus-type differential difference current conveyors, two grounded capacitors and two grounded resistors is presented. The proposed circuit offers the following features: realization of all the standard filter functions, that is, high-pass, bandpass, low-pass, notch, and all-pass filters, no requirements for component matching conditions, the use of only grounded capacitors and resistors, high-input and low-output impedance and low active and passive sensitivities.
TL;DR: A stochastic nonlinear model for genetic regulatory networks with SUM regulatory functions is considered, based on the Lyapunov method and the Lur'e system approach, and sufficient conditions for the Stochastic stability of the genetic networks with disturbance attenuation are derived.
Abstract: Gene regulation is an intrinsically noisy process, which is subject to intracellular and extracellular noise perturbations and environment fluctuations. In this brief, we consider a stochastic nonlinear model for genetic regulatory networks with SUM regulatory functions. Based on the Lyapunov method and the Lur'e system approach, sufficient conditions for the stochastic stability of the genetic networks with disturbance attenuation are derived. The case with time delays owing to the slow processes of transcription, translation, and translocation is also studied. All the results are presented in terms of linear matrix inequalities (LMIs).
TL;DR: An on-chip ultra-high-voltage charge pump circuit realized with the polysilicon diodes in the low- voltage bulk CMOS process is proposed in this work.
Abstract: An on-chip ultra-high-voltage charge pump circuit realized with the polysilicon diodes in the low-voltage bulk CMOS process is proposed in this work. Because the polysilicon diodes are fully isolated from the silicon substrate, the output voltage of the charge pump circuit is not limited by the junction breakdown voltage of MOSFETs. The polysilicon diodes can be implemented in the standard CMOS processes without extra process steps. The proposed ultra-high-voltage charge pump circuit has been fabricated in a 0.25-mum 2.5-V standard CMOS process. The output voltage of the four-stage charge pump circuit with 2.5-V power-supply voltage (VDD=2.5 V) can be pumped up to 28.08 V, which is much higher than the n-well/p-substrate breakdown voltage (~18.9 V) in a 0.25-mum 2.5-V bulk CMOS process
TL;DR: A new unified systolic array is proposed that efficiently implements addition, subtraction, multiplication and division over GF(p) by using a high-performance elliptic curve cryptographic processor, which features a syStolic arithmetic unit.
Abstract: This brief presents a high-performance elliptic curve cryptographic processor for general curves over GF(p), which features a systolic arithmetic unit. We propose a new unified systolic array that efficiently implements addition, subtraction, multiplication and division over GF(p). At the system level, the control dependencies in the operation sequence and the mismatched communication between the systolic array and the separate storage would stall the pipeline in the systolic array. These pipeline stalls are successfully avoided by using two optimization methods. Synthesized in 0.13-mum standard-cell technology, the processor requires 1.01 ms to compute a 256-bit scalar multiplication for general curves over GF(p)
TL;DR: The gradient algorithm for updating the weights of the delayed neural networks is stable to any bounded uncertainties and the conditions for passivity, asymptotic stability and uniform stability are established.
Abstract: In this brief, the identification problem for time-delay nonlinear system is discussed. We use a delayed dynamic neural network to do on-line identification. This neural network has dynamic series-parallel structure. The stability conditions of on-line identification are derived by Lyapunov-Krasovskii approach, which are described by linear matrix inequality. The conditions for passivity, asymptotic stability and uniform stability are established in some senses. We conclude that the gradient algorithm for updating the weights of the delayed neural networks is stable to any bounded uncertainties
TL;DR: An linear matrix inequality (LMI)-based approach for designing linear static output feedback impulsive control laws to globally asymptotically synchronize Lur'e chaotic systems is derived.
Abstract: In this brief, we consider impulsive control for master-slave synchronization schemes that consist of identical chaotic Lur'e systems. Impulsive control laws are investigated which make use of linear static measurement feedback, instead of full state feedback. A less conservative sufficient condition than existing results for global asymptotic impulsive synchronization is presented, in which synchronization is proven for the error between the full state vectors. And then an linear matrix inequality (LMI)-based approach for designing linear static output feedback impulsive control laws to globally asymptotically synchronize Lur'e chaotic systems is derived. With the help of the LMI solvers, we can easily obtain the linear output feedback impulsive controller and the bound of the impulsive interval for global asymptotic synchronization. The method is illustrated on Chua's circuit.
TL;DR: An interference cancellation technique is described for improving the dynamic range of receivers and a feedforward approach is used to attenuate large interferers before the down-conversion mixer in a receiver.
Abstract: An interference cancellation technique is described for improving the dynamic range of receivers. A feedforward approach is used to attenuate large interferers before the down-conversion mixer in a receiver. This is accomplished with no measurable impact on the in-band noise performance. Techniques to cancel interference within a narrowband and also in multiple bands are described. Simulation results and measurements from a discrete prototype system are used to validate the approach.
TL;DR: A novel frequency compensation technique for three-stage operational transconductance amplifiers that exploits a voltage buffer and a nulling resistor to achieve a double pole-zero cancellation, occurring beyond the gain-bandwidth product.
Abstract: This brief introduces and develops a novel frequency compensation technique for three-stage operational transconductance amplifiers. The new compensation topology exploits a voltage buffer and a nulling resistor to achieve a double pole-zero cancellation, occurring beyond the gain-bandwidth product. To verify the effectiveness of the compensation scheme, an amplifier has been fabricated in a standard 0.5-mum CMOS process. Experimental measurements are found to be in good agreement with the theoretical analysis and show an improvement in small-signal and large-signal performances
TL;DR: This brief is concerned with robust Kalman filtering for linear discrete-time systems with both instantaneous and single delayed measurements where the norm-bounded parameter uncertainties enter into the system matrix of the state space model.
Abstract: This brief is concerned with robust Kalman filtering for linear discrete-time systems with both instantaneous and single delayed measurements. The norm-bounded parameter uncertainties enter into the system matrix of the state space model. A new approach through the re-organization of measurements is proposed to improve the efficiency of computation. A sufficient condition for the existence of a robust Kalman filter is derived. The performance is clearly demonstrated through analytical results and simulation experiments.
TL;DR: A retinal vessel segmentation method based on cellular neural networks (CNNs) is proposed, which is based on linear space-invariant 3times3 templates and can be realized using existing chip prototypes like the ACE16K.
Abstract: A retinal vessel segmentation method based on cellular neural networks (CNNs) is proposed. The CNN design is characterized by a virtual template expansion obtained through a multistep operation. It is based on linear space-invariant 3times3 templates and can be realized using existing chip prototypes like the ACE16K. The proposed design is capable of performing vessel segmentation within a short computation time. It was tested on a publicly available database of color images of the retina, using receiver operating characteristic curves. The simulation results show good performance comparable with that of the best existing methods
TL;DR: In this brief, multi-path delay commutator structures are utilized to improve the throughput rate of radix-2 andRadix-4 FFT computation by a factor of 2 to 4.
Abstract: In this brief, multi-path delay commutator structures are utilized to improve the throughput rate of radix-2 and radix-4 FFT computation by a factor of 2 to 4. Latency can also be reduced by a factor of 2 to 3. Compared with previous radix-2 and radix-4 FFT structures, the proposed high-throughput FFT with doubled throughput rate requires similar or even less hardware cost. Although split radix FFT design is more hardware efficient, the regular structure of proposed FFT structures are attractive for high throughput FFT design.
TL;DR: A novel ultra-low-power digitally controlled oscillator (DCO) with cell-based design for system-on-chip (SoC) applications is presented, based on the proposed segmental delay line (SDL) and hysteresis delay cell (HDC), which can be saved by 70% and 86.2% in coarse-tuning and fine- Tuning stages, respectively, as compared with conventional approaches.
Abstract: In this paper, a novel ultra-low-power digitally controlled oscillator (DCO) with cell-based design for system-on-chip (SoC) applications is presented. Based on the proposed segmental delay line (SDL) and hysteresis delay cell (HDC), the power consumption can be saved by 70% and 86.2% in coarse-tuning and fine-tuning stages, respectively, as compared with conventional approaches. Besides, the proposed DCO employs a cascade-stage structure to achieve high resolution and wide range at the same time. Measurement results show that power consumption of the proposed DCO can be improved to 140 muW (@200 MHz) with 1.47-ps resolution. In addition, the proposed DCO can be implemented with standard cells, making it easily portable to different processes and very suitable for SoC applications.