Showing papers in "IEEE Transactions on Circuits and Systems Ii-express Briefs in 2008"

Stability Analysis of a Class of Nonlinear Fractional-Order Systems

Abstract: In this paper, a stability theorem of nonlinear fractional-order differential equations is proven theoretically by using the Gronwall-Bellman lemma. According to this theorem, the linear state feedback controller is introduced for stabilizing a class of nonlinear fractional-order systems. And, a new criterion is derived for designing the controller gains for stabilization, in which control parameters can be selected via the pole placement technique of the linear fractional-order control theory. Finally, the theoretical results are further substantiated by simulation results of the fractional-order chaotic Lorenz system with desired design requirements.

Adaptive Feedback Synchronization of a General Complex Dynamical Network With Delayed Nodes

Abstract: In the past decade, complex networks have attracted much attention from various fields of sciences and engineering. Synchronization is a typical collective behavior of complex networks that has been extensively investigated in recent years. To reveal the dynamical mechanism of synchronization in complex networks with time delays, a general complex dynamical network with delayed nodes is further studied. Based on a suitable model, we investigate the adaptive feedback synchronization and obtain several novel criteria for globally exponentially asymptotic synchronization. In particular, our hypotheses and the proposed adaptive controllers for network synchronization are very simple and can be readily applied in practical applications. Finally, numerical simulations are provided to illustrate the effectiveness of the proposed synchronization criteria.

Frequency-Selective I/Q Mismatch Calibration of Wideband Direct-Conversion Transmitters

Abstract: The current trend in building low-cost yet flexible radio transceivers is to use the so-called direct-conversion principle, which is based on complex (I/Q) up- and down conversions. Such transceivers are, however, sensitive to mismatches between the I and Q branches. These mismatches are unavoidable in any practical implementation, and result in finite attenuation of the mirror frequencies. In addition to the mirror-frequency interference problem, I/Q mismatches can severely compromise the performance of power amplifier linearization techniques based on pre-distortion. The effects of these impairments are becoming more pronounced as higher order modulated waveforms and/or more wideband multichannel signals are used. This brief focuses on digital-signal-processor-based I/Q mismatch calibration in wideband direct-conversion transmitters, assuming the challenging case of frequency-dependent I/Q mismatch. First, a novel widely linear (WL) calibration structure is introduced, suitable for frequency-dependent calibration. Then, two alternative principles for calibration parameter estimation are proposed. The first estimation approach stems from second-order statistics of complex communication signals, while the second technique is based on WL least-squares model fitting. Both estimators are shown by simulations to yield very good calibration performance. The obtainable performance is further assessed using laboratory RF signal measurements.

A Novel Architecture of Delta-Sigma Modulator Enabling All-Digital Multiband Multistandard RF Transmitters Design

Abstract: This paper proposes a new architecture of delta-sigma (DS) modulator suitable for RF digital transmitter design. This novel architecture considerably reduces the speed requirements of the digital signal processing block. The novelty lies in the implementation of a specific fully digital up-conversion in combination with a low-pass DS modulator to produce high-frequency digital-like signals, which can be used to drive highly efficient switching-mode power amplifiers. The proposed architecture is suitable for reconfigurable all-digital, multistandard and multiband wireless transmitters. The novel transmitter architecture has been validated using simulation and implemented on a field-programmable gate array development board for two different signals, code division multiple access and orthogonal frequency division multiplex.

Global Asymptotical Synchronization of Chaotic Lur'e Systems Using Sampled Data: A Linear Matrix Inequality Approach

Abstract: Sampled-data feedback control for master-slave synchronization schemes that consist of identical chaotic Lur'e systems is studied. Sufficient conditions for global asymptotic synchronization of such chaotic Lur'e systems are obtained using the free-weighting matrix approach and expressed in terms of linear matrix inequalities (LMIs). With the help of the LMI solvers, the sampled-data feedback control law can easily be obtained to globally asymptotically synchronize Lur'e chaotic systems. The effectiveness of the proposed method is finally illustrated via numerical simulations of chaotic Chua's circuits.

Using Transmission Line Outage Data to Estimate Cascading Failure Propagation in an Electric Power System

Abstract: We study cascading transmission line outages recorded over nine years in an electric power system with approximately 200 lines. The average amount of propagation of the line outages is estimated from the data. The distribution of the total number of line outages is predicted from the propagation and the initial outages using a Galton-Watson branching process model of cascading failure.

Improved Delay-Dependent $H_{\infty }$ Filtering Design for Discrete-Time Polytopic Linear Delay Systems

Abstract: This brief revisits the problem of delay-dependent robust Hinfin filtering design for discrete-time polytopic linear systems with interval-like time-varying delay. Under the condition whether the unknown parameters can be measured online or not, a parameter-dependent or a parameter-independent filter is respectively developed which guarantees the asymptotic stability of the resulting filtering error system with robust Hinfin performance gamma. It is shown that by using a new linearization technique incorporating a bounding technique, a unified framework can be developed such that the full-order and reduced-order, the parameter-dependent and parameter-independent filters can be obtained by solving a set of linear matrix inequalities. Finally, a numerical example is provided to illustrate the effectiveness and merits of the proposed approach.

UWB Echo Signal Detection With Ultra-Low Rate Sampling Based on Compressed Sensing

Abstract: A major challenge in ultra-wide-band (UWB) signal processing is the requirement for very high sampling rate. The recently emerging compressed sensing (CS) theory makes processing UWB signal at a low sampling rate possible if the signal has a sparse representation in a certain space. Based on the CS theory, a system for sampling UWB echo signal at a rate much lower than Nyquist rate and performing signal detection is proposed in this paper. First, an approach of constructing basis functions according to matching rules is proposed to achieve sparse signal representation because the sparse representation of signal is the most important precondition for the use of CS theory. Second, based on the matching basis functions and using analog-to-information converter, a UWB signal detection system is designed in the framework of the CS theory. With this system, a UWB signal, such as a linear frequency-modulated signal in radar system, can be sampled at about 10% of Nyquist rate, but still can be reconstructed and detected with overwhelming probability. The simulation results show that the proposed method is effective for sampling and detecting UWB signal directly even without a very high-frequency analog-to-digital converter.

Optimal Filtering for Systems With Multiple Packet Dropouts

Abstract: This paper is concerned with the optimal filtering problem for discrete-time stochastic linear systems with multiple packet dropouts, where the number of consecutive packet dropouts is limited by a known upper bound. Without resorting to state augmentation, the system is converted to one with measurement delays and a moving average (MV) colored measurement noise. An unbiased optimal filter is developed in the linear least-mean-square sense. Its solution depends on the recursion of a Riccati equation and a Lyapunov equation. A numerical example shows the effectiveness of the proposed filter.

A Wide-Band CMOS LC VCO With Linearized Coarse Tuning Characteristics

Abstract: A pseudo-exponential capacitor bank structure is proposed to implement a wide-band CMOS LC voltage-controlled oscillator (VCO) with linearized coarse tuning characteristics. An octave bandwidth VCO employing the proposed 6-bit pseudo-exponential capacitor bank structure has been realized in 0.18-mum CMOS. Compared to a conventional VCO employing a binary weighted capacitor bank, the proposed VCO has considerably reduced the variations of the VCO gain (K VCO) and the frequency step per a capacitor bank code (f step/code) by 2.7 and 2.1 times, respectively, across the tuning range of 924-1850 MHz. Measurement results have also shown that the VCO provides the phase noise of - 127.1 dBc/Hz at 1-MHz offset for 1.752-GHz output frequency while dissipating 6 mA from a 1.8-V supply.

Fault Tolerance Analysis for Switched Systems Via Global Passivity

Abstract: In this brief, we introduce the passivity theory into the fault tolerance analysis for switched systems. We propose a ldquoglobal passivityrdquo concept which means that the total energy stored by the switched system is less than the total energy supplied from the outside. The individual passivity of each mode is not required, and the stability of the system can be achieved via the global energy dissipativity in the presence of faults. We further provide a ldquoperiodic fault tolerant passivityrdquo to check the fault tolerance easily. The obtained results are extended to feedback interconnected systems. A switched RLC circuit example is taken to illustrate the efficiency of the proposed results.

Constrained Control of Positive Discrete-Time Systems With Delays

Abstract: This brief addresses the control problem of linear time-invariant discrete-time systems with delays. The control is under positivity constraint, which means that the resulting closed-loop systems are not only stable, but also positive. The contribution lies in three aspects. First, a necessary and sufficient condition is established for the existence of such controllers for discrete-time delayed systems. Second, a sufficient condition is provided under the additional constraint of bounded control, which means that the control inputs and the states of the closed-loop systems are bounded. Third, sufficient conditions are proposed for discrete-time delayed systems with uncertainties, whether or not bounded control is considered. All the results are formulated as linear programming problems, hence easy to be verified. And the controllers are explicitly constructed if existent.

Improvement of State Feedback Controller Design for Networked Control Systems

Abstract: A new method is proposed to improve the state feedback controller design for networked control systems (NCSs) taking both network-induced time delay and packet dropout into account in this paper. An appropriate Lyapunov functional is introduced to establish the improved sufficient stabilizability conditions for NCSs with memoryless state feedback controller by considering an additional useful term when estimating the upper bound of the derivative of Lyapunov functional and introducing new free weight matrices. Based on this less conservative existence condition, a networked controller design method is derived, which is equivalent to the solvability of a set of linear matrix inequalities. Numerical example is given to demonstrate the effectiveness and benefits of the proposed method.

Concurrent Dual-Band Class-F Load Coupling Network for Applications at 1.7 and 2.14 GHz

Abstract: Highly efficient multiband power amplifiers (PAs) are key elements for the development of future multistandard multiband communication terminals and cognitive radios. This paper reports the design of a multiharmonic dual-band Class-F power amplifier for applications at wireless communication frequencies based on a switchless multiharmonic multiband load coupling network topology. The proposed output network topology is able to precisely synthesize Class-F impedance conditions with up to three harmonics at two distinct nonharmonic frequencies without the need of switches or electronically tunable elements. The proposed topology was used to design a Class-F PA in hybrid technology for the frequency bands at 1.7 and 2.14 GHz. Optimum impedances for maximum efficiency of the used GaAs MESFET for the two bands were determined by multiharmonic load-pull measurements and synthesized by the proposed switchless dual-band Class-F network. With a dual-band input matching network, the fabricated PA achieves 44.0% and 61.3% drain efficiency for an output power of more than 32.8 dbm and 34.4 dbm at 1.7 and 2.14 GHz, respectively. To the best knowledge of the authors, this is the first concurrent multiharmonic dual-band PA reported in open literature.

Power Waves and Conjugate Matching

Abstract: The concept of power waves gives more natural relations between incident and reflected power in a microwave network than the typically used traveling waves. The reflection coefficient for power waves directly describes the reflection of power whereas the reflection coefficient of traveling waves describes the reflection of the waves themselves. In this brief, new physical reasoning of power waves is given starting from the principle of conjugate matching. In addition, a new formula for the reference impedances for a two-port system is given such that the system is simultaneously conjugate matched for both ports.

A Neutral-Type Delayed Projection Neural Network for Solving Nonlinear Variational Inequalities

Abstract: A neutral-type delayed projection neural network is proposed to deal with nonlinear variational inequalities. Compared with the existing delayed neural networks for linear variational inequalities, the proposed approach apparently has the larger application domain. By the theory of functional differential equation, a delay-dependent sufficient stability condition is derived. This stability condition is easily checked, and can guarantee that the proposed neural network is convergent to the solution of nonlinear variational inequality problem exponentially, which improves the existing stability criteria for the neutral-type delayed neural network. Moreover, many related problems, such as the projection equation and optimization problems, can also be dealt with by the proposed method. Finally, simulation examples are given to illustrate the satisfactory performance of the proposed method.

A Constant Frequency Output-Ripple-Voltage-Based Buck Converter Without Using Large ESR Capacitor

Abstract: A constant frequency output-ripple-voltage based CMOS current-mode dc-dc buck converter, providing fast load transient response and reference-tracking speed, is proposed in this paper. Unlike V2 control output-ripple-voltage based buck converter, the proposed buck converter can achieve fast and stable load transient response without relying on ESR value of output capacitor. In addition, the proposed converter has faster reference-tracking speed than V2 the control counterparts by about 25 times.

A Current-Mode Comparator for Digital Calibration of Amorphous Silicon AMOLED Displays

Abstract: We present a digital calibration driving scheme for stabilizing the uniformity of large area amorphous silicon active-matrix organic light emitting diode displays. A current-mode analog-to-digital converter (ADC) is used to extract the differential aging of the individual pixels. For the ADC, a configurable current comparator is designed that employs the output buffer of the source driver to reduce the die area. The comparator and pixel circuit were fabricated in 0.8-mum high-voltage CMOS and amorphous silicon technologies, respectively. Analysis and measurement results show a calibration refresh time of 2 s for a high-definition display (1920 times RGB times 1080). Moreover, the pixel current is highly stable despite a 5-V shift in the threshold voltage of the thin-film transistor driver.

Attack Vulnerability of Complex Communication Networks

Abstract: The Internet has been studied as a typical example of real-world complex networks. In this brief, we study the traffic performance of the Internet when it encounters a random or intentional attack. Different from previous approaches, the congestion control protocols are considered so that the bandwidth can be reallocated among flows. In this way, cascading breakdown is less likely to happen. The flow rates are adjusted when a node is attacked and out of function. Consequently, the traffic utility and the utilization ratio of bandwidth are affected. We compare the real Internet data with the classic random graph and scale-free network models. The simulated results also show that the ldquorobust yet fragilerdquo property previously observed in the study of cascading failures in the scale-free networks is still valid in this scenario.

Generation of $n\times m$ -Wing Lorenz-Like Attractors From a Modified Shimizu–Morioka Model

Abstract: This paper explores the generation of n- and n times m-wing Lorenz-type attractors from a modified Shimizu-Morioka system. The basic idea is to increase the number of index-2 equilibrium points by introducing a multisegment quadratic function and a stair function in the 2-D state-space of the system. The design is verified by both simulation and experiment, where multiwing attractors over a grid can be clearly observed.

An Active-Frequency Compensation Scheme for CMOS Low-Dropout Regulators With Transient-Response Improvement

Abstract: An active-frequency compensation circuit for low- dropout regulators (LDOs) is presented. Compared with the conventional compensation scheme, the proposed circuit can greatly boost the effective current multiplication factor by at least one order of magnitude without increasing any power consumption. Hence, the proposed circuit can generate an internal lower frequency zero and push parasitic poles toward extremely high frequency such that the loop bandwidth can be extended drastically. The required on-chip capacitance is reduced to 0.4 pF, comparing to 5 pF in the conventional compensation scheme. The slew rate at the gate drive of the LDO is also improved by the proposed error amplifier. Implemented in a 0.35 mum 2P4M CMOS process, the LDO with the proposed active-frequency compensation circuit consumes 27 muA ground current at 150-mA maximum output current with a dropout voltage of 200 mV. Experimental results show that the proposed LDO structure has achieved only 10% settling time of the conventional compensation scheme.

Block-Interlaced LDPC Decoders With Reduced Interconnect Complexity

Abstract: Two design techniques are proposed for high-throughput low-density parity-check (LDPC) decoders. A broadcasting technique mitigates routing congestion by reducing the total global wirelength. An interlacing technique increases the decoder throughput by processing two consecutive frames simultaneously. The brief discusses how these techniques can be used for both fully parallel and partially parallel LDPC decoders. For fully parallel decoders with code lengths in the range of a few thousand bits, the half-broadcasting technique reduces the total global wirelength by about 26% without any hardware overhead. The block interlacing scheme is applied to the design of two fully parallel decoders, increasing the throughput by 60% and 71% at the cost of 5.5% and 9.5% gate count overhead, respectively.

An Efficient VLSI Architecture for Normal I/O Order Pipeline FFT Design

Abstract: In this paper, an efficient VLSI architecture of a pipeline fast Fourier transform (FFT) processor capable of producing the normal output order sequence is presented. A new FFT design based on the decimated dual-path delay feed-forward data commutator unit by splitting the input stream into two half-word streams is first proposed. The resulting architecture can achieve full hardware efficiency such that the required number of adders can be reduced by half. Next, in order to generate the normal output order sequence, this paper also presents a sequence conversion method by integrating the conversion function into the last-stage data commutator module.

Design of 60- and 77-GHz Narrow-Bandpass Filters in CMOS Technology

Abstract: This paper investigates the design and implementation of millimeter-wave narrow-bandpass filters in a standard 0.18- m CMOS technology. Filters with a measured 10% 3-dB bandwidth at 60 and 77 GHz are realized in a thin-film microstrip structure by using the lowest metallization layer as a ground plane. The impact of dissipation losses of the filters is also examined. It is found that the metallization losses in the coupled-line filter as well as the ground plane are the main reasons for the insertion loss.

Stability Analysis of 2-D Discrete Systems Described by the Fornasini–Marchesini Second Model With State Saturation

Abstract: A criterion for the global asymptotic stability of 2D discrete systems described by the Fornasini-Marchesini second local state-space model employing state saturation arithmetic is presented. An example shows the effectiveness of the present criterion.

A Low-Noise CMOS Distributed Amplifier for Ultra-Wide-Band Applications

Abstract: To employ the distributed amplification technique for the design of ultra-wide-band low-noise amplifiers, the poor noise performance of the conventional distributed amplifiers (DAs) needs to be improved. In this work, the terminating resistor of the gate transmission line, a main contributor to the overall DA's noise figure, is replaced with a resistive-inductive network. The proposed terminating network creates an intentional mismatch to reduce the noise contribution of the terminating network. The degraded input matching at low frequencies can be tolerated for ultra-wide-band applications as they need to operate above 3 GHz. Implemented in a 0.13 mum CMOS process, the proposed DA achieves a flat gain of 12 dB with an average noise figure of 3.3 dB over the 3- to 9.4-GHz band, the best reported noise performance for a CMOS DA in the literature. The amplifier dissipates 30 mW from two 0.6-V and 1-V dc power supplies.

Reconfigurable Frequency Response Masking Filters for Software Radio Channelization

Abstract: Low complexity and reconfigurability are two key requirements of channel filters in a software defined radio receiver. A new reconfigurable architecture based on frequency response masking (FRM) technique for the implementation of channel filters is proposed in this paper. Our architecture offers reconfigurability at filter and architecture levels, in addition to the inherent low complexity offered by the FRM technique. The proposed reconfigurable filter has been synthesized on 0.18- CMOS technology and implemented and tested on Virtex-II 2v3000ff1152-4 field-programmable gate array. Synthesis results show that the proposed channel filter offers average area and power reductions of 53.6% and 57.6%, respectively ,with average improvement in speed of 47.6% compared to other reconfigurable filters in literature.

An Automatic Antenna Tuning System Using Only RF Signal Amplitudes

Abstract: The operating environment of mobile phones fluctuates continuously, due to changing handling conditions and nearby objects. The resulting fluctuations in antenna impedance cause both a decrease in link quality and a higher standing wave ratio, that requires more robust and hence less efficient power amplifier implementations. In this paper, an automatic antenna tuner system for handheld applications is presented that uses two series reactances combined with three simple RF peak detectors to sense both reactive and real impedance mismatches. The control loop only requires low-frequency electronics which makes it low cost, low power and relatively easy to integrate. Measurements on a demonstrator system show correct behaviour for voltage standing-wave ratio up to 10.

Excess Loop Delay Compensation in Continuous-Time Delta-Sigma Modulators

Abstract: We present a simple, intuitive technique to compensate the loop filter transfer function for excess delay in low-pass continuous-time DeltaSigma modulators. Conventional methods of finding the appropriate filter coefficients to account for loop delay work in the z-domain, leading to cumbersome algebra. We show that the same objective can be accomplished entirely in the continuous-time domain, resulting in a procedure that lends itself to hand calculations, even for high order modulators. We derive closed-form expressions for the loop filter coefficients in modulators using nonreturn-to-zero and return-to-zero digital-to-analog converters. Simulation results confirming the theory are given.

A Background Sample-Time Error Calibration Technique Using Random Data for Wide-Band High-Resolution Time-Interleaved ADCs

Abstract: Sample-time error among the channels of a time-interleaved analog-to-digital converter (ADC) is the main reason for significant degradation of the effective resolution of the high-speed time-interleaved ADC. A calibration technique for sample-time mismatches has been proposed and implemented at a low level of complexity. The calibration method uses random data and is especially suitable for ADCs used in digital data communication systems. An 800-MS/s four-channel, time-interleaved ADC system has been implemented to evaluate the performance of the technique. The experimental results show that the spurious-free dynamic range of the ADC system is improved to 58.1 dB at 350 MHz. The ADC system achieves a signal-to-noise and distortion ratio of 59.6 dB at 5 MHz and 50.1 dB at 350 MHz after calibration.