Showing papers in "IEEE Transactions on Circuits and Systems Ii-express Briefs in 2013"

A Simple Model of Double-Loop Hysteresis Behavior in Memristive Elements

Abstract: This brief investigates the double-loop hysteresis behavior in memristive elements. Here, we propose a very simple dimensionless equation to model the double-loop behavior and then show how physical voltage- and current-controlled memristor models can be derived. Furthermore, we introduce the incremental/decremental positive/negative memristance/transmemristance and present circuit emulators which are capable of emulating these devices. Experimental results are given.

Reference-Modulated DCSK: A Novel Chaotic Communication Scheme

Abstract: In this brief, a reference-modulated differential chaos shift keying (DCSK) (RM-DCSK) is proposed for reliable and high-data-rate chaotic communication with low cost. In this scheme, the chaotic wavelet sent in either the first or second slot of each frame not only carries one bit of data but also serves as the message bearer of the data bit transmitted in its following time slot. Without any extra cost in decoding complexity, RM-DCSK can achieve doubled attainable bit rate and improved communication security in comparison to DCSK. The bit error rate (BER) performance of this new scheme is derived based on Gaussian approximation. Moreover, relevant simulation results in the additive white Gaussian noise channel are also given and compared with those of correlation delay shift keying (CDSK), DCSK, frequency-modulated DCSK, and high-efficiency DCSK schemes, which shows that the BER performance of our system is always superior to that of CDSK and it can even outperform DCSK under certain Eb/N0 levels or with large spreading factors.

$l_{2} - l_{\infty}$ Elimination of Overflow Oscillations in 2-D Digital Filters Described by Roesser Model With External Interference

Abstract: Two-dimensional (2-D) digital filters can be corrupted by external interferences, but no stability criteria have yet been established This brief proposes a new l2 - l∞ stability criterion for the absence of limit cycles in 2-D digital filters that are described by Roesser model with external interference Our new criterion ensures the attenuation of the effect of external interference on 2-D digital filters to a prescribed level This criterion also guarantees the asymptotic stability result without external interference The proposed criterion is represented in terms of linear matrix inequality, which can be verified by using existing numerical packages We use an illustrative example to demonstrate the effectiveness of the proposed criterion

A Capacitorless LDO Regulator With Fast Feedback Technique and Low-Quiescent Current Error Amplifier

Abstract: This brief presents an ultralow quiescent class-AB error amplifier (ERR AMP) of low dropout (LDO) and a slew-rate (SR) enhancement circuit to minimize compensation capacitance and speed up transient response designed in the 0.11-μm 1-poly 6-metal CMOS process. In order to increase the current capability with a low standby quiescent current under large-signal operation, the proposed scheme has a class-AB-operation operational transconductance amplifier (OTA) that acts as an ERR AMP. As a result, the new OTA achieved a higher dc gain and faster settling time than conventional OTAs, demonstrating a dc gain improvement of 15.8 dB and a settling time six times faster than that of a conventional OTA. The proposed additional SR enhancement circuit improved the response based on voltage-spike detection when the voltage dramatically changed at the output node.

FPGA-Based 40.9-Gbits/s Masked AES With Area Optimization for Storage Area Network

Abstract: In order to protect “data-at-rest” in storage area networks from the risk of differential power analysis attacks without degrading performance, a high-throughput masked advanced encryption standard (AES) engine is proposed. However, this engine usually adopts the unrolling technique which requires extremely large field programmable gate array (FPGA) resources. In this brief, we aim to optimize the area for a masked AES with an unrolled structure. We achieve this by mapping its operations from to as much as possible. We reduce the number of mapping [ to ] and inverse mapping [ to ] operations of the masked SubBytes step from ten to one. In order to be compatible, the masked MixColumns, masked AddRoundKey, and masked ShiftRows including the redundant masking values are carried over . We also use FPGA block RAM (BRAM) to further reduce hardware resources. Compared with a state-of-the-art design, our implementation reduces the overall area by 36.2% (20.5% is contributed by the main method, and 15.7% is contributed by the BRAM optimization). It achieves 40.9-Gbits/s at 4.5-Mbits/s/slice on the Xilinx XC6VLX240T platform. We have attacked the iterative version of this masked AES in hardware. Results show that none of the bytes can be guessed from the masked AES with the collected 10 000 power traces, but 14 out of 16 bytes can be guessed from the unprotected AES with the same number of traces.

Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic

Abstract: This brief presents a novel pipelined architecture for low-power, high-throughput, and low-area implementation of adaptive filter based on distributed arithmetic (DA). The throughput rate of the proposed design is significantly increased by parallel lookup table (LUT) update and concurrent implementation of filtering and weight-update operations. The conventional adder-based shift accumulation for DA-based inner-product computation is replaced by conditional signed carry-save accumulation in order to reduce the sampling period and area complexity. Reduction of power consumption is achieved in the proposed design by using a fast bit clock for carry-save accumulation but a much slower clock for all other operations. It involves the same number of multiplexors, smaller LUT, and nearly half the number of adders compared to the existing DA-based design. From synthesis results, it is found that the proposed design consumes 13% less power and 29% less area-delay product (ADP) over our previous DA-based adaptive filter in average for filter lengths N = 16 and 32. Compared to the best of other existing designs, our proposed architecture provides 9.5 times less power and 4.6 times less ADP.

Design of a Practical Memcapacitor Emulator Without Grounded Restriction

Abstract: This brief aims to design a floating memcapacitor emulator that can be practically applied in electronic circuits. A memritive circuit making use of analog components is proposed and then transformed into a flux-controlled floating memcapacitor emulator, of which the realization is on the basis of four current conveyor chips. To confirm the effectiveness and correctness, this proposed emulator is theoretically analyzed and experimentally tested as connected in an R-C frequency selection network. All the simulation results and experiment waveforms provide conclusive evidences to validate the outstanding performance of this new memcapacitor emulator.

Performing Stateful Logic on Memristor Memory

Abstract: This brief proposes a circuit structure that performs a stateful logic operation on memristor memory based on a nanocrossbar. Through analysis and comparison of multiple schemes, achievable circuit condition is demonstrated, and the feasibility of the duplication operation is proved. The proposed circuit structure provides the memory with the function of in situ logic operation and thus can potentially reduce the amount of memory accessing actions and provide a possible solution to the memory wall problem.

A Low-Noise Four-Stage Voltage-Controlled Ring Oscillator in Deep-Submicrometer CMOS Technology

Abstract: This brief presents a low-voltage and low-noise ring voltage-controlled oscillator (VCO) where the phase noise performance is improved by reducing the total channel thermal noise injected into the output node of the VCO during the transition period of the output voltage swing. Implemented in a 65-nm CMOS technology, the proposed ring VCO operates from 485.7 to 1011.6 MHz. At 645 MHz, the measured phase noise is $-$ 110.8 dBc/Hz at an offset of 1 MHz while dissipating 10 mW from a 1-V supply.

A Study on the Use of Performance Counters to Estimate Power in Microprocessors

Abstract: We present a study on estimating the dynamic power consumption of a processor based on performance counters. Today's processors feature a large number of such counters to monitor various CPU and memory parameters, such as utilization, occupancy, bandwidth, page, cache, and branch buffer hit rates. The use of various sets of performance counters to estimate the power consumed by the processor has been demonstrated in the past. Our goal is to find out whether there exists a subset of counters that can be used to estimate, with sufficient accuracy, the dynamic power consumption of processors with varying microarchitecture. To this end, we consider two recent processor configurations representing two extremes of the performance spectrum, one targeting low power and the other high performance. Our results indicate that only three counters measuring 1) the number of fetched instructions, 2) level-1 cache hits, and 3) dispatch stalls are sufficient to achieve adequate precision. These counters are shown to be effective in predicting the dynamic power consumption across processors of varying resource sizes achieving a prediction accuracy of 95%.

A Normalized Least Mean Squares Algorithm With a Step-Size Scaler Against Impulsive Measurement Noise

Abstract: This brief introduces the concept of a step-size scaler by investigating and modifying the tanh cost function for adaptive filtering with impulsive measurement noise. The step-size scaler instantly scales down the step size of gradient-based adaptive algorithms whenever impulsive measurement noise appears, which eliminates a possibility of updating weight vector estimates based on wrong information due to impulsive noise. The most attractive feature of the step-size scaler is that this is easily applicable to various gradient-based adaptive algorithms. Several representative gradient-based adaptive algorithms are performed without or with the step-size scaler in impulsive-noise environments, which shows the improvement of robustness against impulsive noise.

Guaranteed $H_{\infty}$ Performance State Estimation of Delayed Static Neural Networks

Abstract: This brief studies the guaranteed H∞ performance state estimation problem of delayed static neural networks The single- and double-integral terms in the time derivative of the Lyapunov functional are handled by the reciprocally convex combination and a new integral inequality, respectively A delay-dependent design criterion is established such that the error system is globally exponentially stable with a decay rate and a prescribed H∞ performance is guaranteed The gain matrix and the optimal performance index are obtained via solving a convex optimization problem subject to linear matrix inequalities A numerical example is exploited to demonstrate that much better performance can be achieved by this approach

An Ultralow-Power Fast-Transient Capacitor-Free Low-Dropout Regulator With Assistant Push–Pull Output Stage

Abstract: An output capacitor-free low-dropout regulator (LDO) using a class-AB operational amplifier and an assistant push–pull output stage (APPOS) circuit to enable fast-transient response with ultralow-power dissipation is presented in this brief. The APPOS circuit is proposed to deliver an extra current that is directly proportional to the output current of the class-AB operational amplifier during transient state with an automatic on/off feature. Moreover, the small-signal and large-signal responses of LDO can be separately optimized. As a result, transient performances of LDO are improved significantly without requiring an area-consuming on-chip capacitor anymore. The proposed LDO has been implemented in a standard 0.35- $\mu\hbox{m}$ CMOS process. Experimental results show that the LDO can regulate the output voltage at 1.0 V from a 1.2-V supply voltage for the maximum load current of 100 mA. The output voltage fully recovers within 2.7 $\mu\hbox{s}$ with the load current switching from 100 $\mu\hbox{A}$ to 100 mA at a 1.2- $\mu\hbox{A}$ quiescent current.

Pilot Allocation for Sparse Channel Estimation in MIMO-OFDM Systems

Abstract: The frequency-selective channel-estimation problem in multi-input-multi-output orthogonal frequency division multiplexing (MIMO-OFDM) systems is investigated from the perspective of compressed sensing (CS). By minimizing the mutual coherence of the measurement matrix in CS theory, two pilot allocation methods for the CS-based channel estimation in MIMO-OFDM systems are proposed. Simulation results show that using the pilot patterns designed by the two proposed methods gives a much better performance than using other pilot patterns in terms of the mean square error of the channel estimate as well as the bit error rate of the system. Moreover, the optimal pilot patterns obtained by the proposed second method based on genetic algorithm and shift mechanism could offer a larger performance gain than those by the first method based on minimizing the largest element in the mutual coherence set possessed by pilot patterns for all multiple antenna ports.

Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication/Accumulation

Abstract: Low-cost finite impulse response (FIR) designs are presented using the concept of faithfully rounded truncated multipliers. We jointly consider the optimization of bit width and hardware resources without sacrificing the frequency response and output signal precision. Nonuniform coefficient quantization with proper filter order is proposed to minimize total area cost. Multiple constant multiplication/accumulation in a direct FIR structure is implemented using an improved version of truncated multipliers. Comparisons with previous FIR design approaches show that the proposed designs achieve the best area and power results.

Low-Area and High-Throughput Architecture for an Adaptive Filter Using Distributed Arithmetic

Abstract: A high-performance implementation scheme for a least mean square adaptive filter is presented. The architecture is based on distributed arithmetic in which the partial products of filter coefficients are precomputed and stored in lookup tables (LUTs) and the filtering is done by shift-and-accumulate operations on these partial products. In the case of an adaptive filter, it is required that the filter coefficients be updated and, hence, these LUTs are to be recalculated. A new strategy based on the offset binary coding scheme has been proposed in order to update these LUTs from time to time. Simulation results show that the proposed scheme consumes very less chip area and operates at high throughput for large base unit size k ( = N/m) , where m is an integer and N is the number of filter coefficients. For example, a 128-tap finite-impulse-response adaptive filter with the proposed implementation produces 12 times more throughput (for k = 8) and consumes almost 26% less area when compared to the best of existing architectures.

An In-Place FFT Architecture for Real-Valued Signals

Abstract: This brief presents a novel scalable architecture for in-place fast Fourier transform (IFFT) computation for real-valued signals. The proposed computation is based on a modified radix-2 algorithm, which removes the redundant operations from the flow graph. A new processing element (PE) is proposed using two radix-2 butterflies that can process four inputs in parallel. A novel conflict-free memory-addressing scheme is proposed to ensure the continuous operation of the FFT processor. Furthermore, the addressing scheme is extended to support multiple parallel PEs. The proposed real-FFT processor simultaneously requires fewer computation cycles and lower hardware cost compared to prior work. For example, the proposed design with two PEs reduces the computation cycles by a factor of 2 for a 256-point real fast Fourier transform (RFFT) compared to a prior work while maintaining a lower hardware complexity. The number of computation cycles is reduced proportionately with the increase in the number of PEs.

A Submicrowatt 1.1-MHz CMOS Relaxation Oscillator With Temperature Compensation

Abstract: A 1.1-MHz submicrowatt current-mode relaxation oscillator with temperature compensation is presented. In this oscillator, the current-starving inverters are biased by using the current sources with positive and negative temperature coefficients. It relaxes the temperature variations. This oscillator is fabricated in a 0.18- μm CMOS process, and its area is 0.075 mm2. The power consumption is 0.859 μW, with a supply voltage of 1.8 V, and the calculated figure of merit is 0.78 nW/kHz. The measured output relative frequency variation is less than 3%/V for the supply voltage of 1.2-2.4 V and ±0.5% for the temperature of -20°C-80°C. The average temperature coefficient is 64.3 ppm/°C.

Noise and Sensitivity in RF Envelope Detection Receivers

Abstract: RF envelope detection receivers (RXs) are largely used in low-power and short-range wireless applications because of their low power consumption However, such RXs suffer from poor sensitivity In this brief, the noise characteristic of the RX is analyzed via a nonlinear approach It identifies the noise contributors in the RX and evaluates their impact on the sensitivity The proposed method is extended to the synchronized-switching envelope detection RX, and the analysis is verified by the measurement results

Finite-Horizon $H_{\infty}$ Fault Estimation for Uncertain Linear Discrete Time-Varying Systems With Known Inputs

Abstract: In this brief, the finite-horizon H∞ fault estimation problem is investigated for a class of uncertain linear discrete time-varying systems with known inputs. A new H∞ performance index including the known inputs is put forward in order to better reflect the effect of the known input on the whole fault estimation systems. To cope with the uncertainties, an auxiliary system is constructed with a certain indefinite quadratic form. By recurring to the Krein-space theory, the optimization problem of the associated indefinite quadratic form is solved, and a sufficient condition with much less conservativeness is established for the existence of the desired fault estimator. Then, all the estimator parameters are derived simultaneously in terms of an explicit solution to a matrix equation. Finally, an illustrative numerical example is employed to demonstrate the effectiveness of the proposed fault estimation scheme.

Synchronization of Complex Networks With Impulsive Control and Disconnected Topology

Abstract: Synchronization of complex networks is an important issue in the study of complex networks. Many existing works reveal that complex networks can reach synchronization under the condition of connected topology; however, by introducing the concept of joint connectivity and sequential connectivity, this brief shows us that complex networks can synchronize even if the topology is not connected at any time instant. Strict technical analysis demonstrates the feasibility of this brief.

Pipelined Architectures for Real-Valued FFT and Hermitian-Symmetric IFFT With Real Datapaths

Abstract: This brief presents novel parallel pipelined architectures for the computation of the fast Fourier transform (FFT) of real signals and inverse FFT of Hermitian-symmetric signals using only real datapaths. The real FFT structure is transformed by transferring twiddle factors to subsequent stages, such that each stage in the proposed flow graph contains one column of butterfly units and one column of twiddle factor blocks, and each column of the flow graph contains only N samples. This is a key requirement for the design of architectures that are based on only real datapaths. This structure is then mapped to pipelined architectures. The proposed architectures can be used with any FFT size or level of parallelism, which is a power of two. A systematic method to design architectures for FFTs with different levels of parallelism and radix values is presented. By modifying the FFT flow graph for real-valued samples, this methodology leads to architectures with fewer adders, delays, and interconnections.

A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology

Abstract: This brief presents a bang-bang all-digital phase-locked loop (ADPLL) clock generator for multiprocessor system-on-chip applications in Globalfoundries 28-nm superlow-power CMOS technology. The circuit features a single-shot phase synchronization scheme for instantaneous phase lock after power-up. This feature is used for fast frequency search during lock-in, resulting in less than 1-μs initial lock time and the capability of instantaneous restart. The ADPLL provides a wide range of output clocks from 83 MHz to 2 GHz and exhibits 31-ps accumulated jitter with 3-ps period jitter at 2 GHz. It occupies an area of only 0.00234 mm2 and consumes 0.64 mW from a 1.0-V supply.

An RF–DC Converter with Wide-Dynamic-Range Input Matching for Power Recovery Applications

Abstract: An improved RF-dc converter based on a class-E rectifier with wide-dynamic-range input matching is presented. The input impedance is controlled by two varactor diodes to compensate for impedance changes with RF input power and dc loading conditions. The RF-dc converter achieved a peak efficiency of 60% and an S11 less than - 20 dB over an input RF power range of 12 dB and an operating battery voltage of 2.5-4.2 V at 800 MHz. An analytical model for input impedance and efficiency was developed and shown to match simulation and measurement results.

A 1-mW Solar-Energy-Harvesting Circuit Using an Adaptive MPPT With a SAR and a Counter

Abstract: This brief presents an energy-harvesting system that uses an adaptive maximum power point tracking (MPPT) circuit for 1-mW solar-powered wireless sensor networks. The proposed MPPT circuit exploits a successive approximation register and a counter to solve the tradeoff problem between a fast transient response and a small steady-state oscillation with low-power consumption. The proposed energy-harvesting circuit is fabricated using a 0.35-μm CMOS process. The MPPT circuit reduces the transient response time by 76.6%, dissipates only 110 μW , and shows MPPT efficiency of 99.6%.

Design of an Optimal Layout Polyphase Filter for Millimeter-Wave Quadrature LO Generation

Abstract: The analysis and design of a two-stage passive RC polyphase filter for millimeter-wave quadrature local oscillator generation is presented. The layout parasitics, which significantly deteriorate the filter performance at millimeter-wave frequencies, are identified with the help of impedance variation and transfer function analysis. To alleviate this parasitic degradation, a new optimal layout structure along with parasitic-compensation technique is proposed, which results in a 15-dB improvement in image rejection ratio, as compared with a conventional layout. Using the proposed techniques, more than 35 dB of image rejection over a bandwidth of 7 GHz is demonstrated in an outphasing transmitter at 60 GHz in 40-nm CMOS.

Spatial Memoization: Concurrent Instruction Reuse to Correct Timing Errors in SIMD Architectures

Abstract: This brief proposes a novel technique to alleviate the cost of timing error recovery, building upon the lockstep execution of single-instruction-multiple-data (SIMD) architectures. To support spatial memoization at the instruction level, we propose a single-strong-lane-multiple-weak-lane (SSMW) architecture. Spatial memoization exploits the value locality inside parallel programs, memoizes the result of an error-free execution of an instruction on the SS lane, and concurrently reuses the result to spatially correct errant instructions across MW lanes. Experiment results on Taiwan Semiconductor Manufacturing Company 45-nm technology confirm that this technique avoids the recovery for 62% of the errant instructions on average, for both error-tolerant and error-intolerant general-purpose applications.

VLSI Implementation of a High-Throughput Iterative Fixed-Complexity Sphere Decoder

Abstract: By exchanging soft information between the multiple-input multiple-output (MIMO) detector and the channel decoder, an iterative receiver can significantly improve the performance compared to the noniterative receiver. In this brief, a soft-input soft-output fixed-complexity-sphere-decoding algorithm and its very large scale integration architecture are proposed for the iterative MIMO receiver. The deeply pipelined architecture employs the optimized hybrid enumeration to search for the best child node estimate efficiently. By adding the counter hypotheses in parallel with other candidates, the proposed iterative MIMO detector improves the detection performance significantly with low detection latency. An iterative detector for an 4 × 4 64-quadrature amplitude modulation (QAM) MIMO system based on our proposed architecture is designed and implemented using the 90-nm CMOS technology. The detector can achieve a maximum throughput of 2.2 Gbit/s with an area efficiency of 3.96 Mbit/s/kGE, which is more efficient than other iterative MIMO detectors.

Fast Output Voltage-Regulated PWM Buck Converter With an Adaptive Ramp Amplitude Control

Abstract: This brief presents a pulsewidth modulation buck converter with an adaptive ramp amplitude control. The proposed buck converter can improve the load transient response and the reference tracking speed. A chip was fabricated in a 0.18-μm CMOS technology. Measurement results showed that the overshoot/undershoot at the output during the load transient period was reduced by up to 57% for a 450-mA load current step and that the reference tracking speed was improved by up to 71% for a 1.5-V output voltage change. The measured maximum power conversion efficiency was 92.6% at 3-MHz switching frequency when input and output voltages are 3.3 and 2 V, respectively.

Robust $H_{\infty}$ Synchronization of Coupled Partial Differential Systems With Spatial Coupling Delay

Abstract: This brief discusses the asymptotical synchronization and robust H∞ synchronization for coupled semilinear partial differential systems (PDSs) with time-varying delay in spatial coupling. First, using the Lyapunov-Krasoviskii functional method, sufficient conditions are obtained for the asymptotical synchronization of coupled semi-linear time-delay PDSs and these conditions are presented by linear matrix inequalities (LMIs), which are easy to be solved. The effect of the spatial domain on the asymptotical synchronization of the coupled time-delay PDSs is also presented. Then the robust H∞ synchronization is considered in temporal-spatial domain for the coupled time-delay PDSs with external disturbances. In terms of the technique of completing squares, sufficient conditions are got for the robust H∞ synchronization of time-delay coupled PDSs. Finally, numerical examples of coupled semilinear time-delay PDSs are given to illustrate the correctness of the obtained results.