Showing papers in "IEEE Transactions on Circuits and Systems Ii-express Briefs in 2014"

MAGIC—Memristor-Aided Logic

Abstract: Memristors are passive components with a varying resistance that depends on the previous voltage applied across the device. While memristors are naturally used as memory, memristors can also be used for other applications, including logic circuits. In this brief, a memristor-only logic family, i.e., memristor-aided logic (MAGIC), is presented. In each MAGIC logic gate, memristors serve as an input with previously stored data, and an additional memristor serves as an output. The topology of a MAGIC nor gate is similar to the structure of a common memristor-based crossbar memory array. A MAGIC nor gate can therefore be placed within memory, providing opportunities for novel non-von Neumann computer architectures. Other MAGIC gates also exist (e.g., and , or , not , and nand ) and are described in this brief.

A Floating Analog Memristor Emulator Circuit

Abstract: This brief introduces a new floating memristor emulator circuit based on second-generation current conveyors and passive elements. A mathematical model to characterize the memristor behavior was derived, showing a good accuracy among HSPICE simulations and experimental results. An analysis of the frequency behavior of the memristor is also described, showing that the frequency-dependent pinched hysteresis loop in the current-versus-voltage plane holds up to 20.2 kHz. Theoretical derivations and related results are experimentally validated through implementations from commercially available devices, and the proposed memristor emulator circuit can easily be reproducible at a low cost. Furthermore, the emulator circuit can be used as a teaching aid and for future applications with memristors, such as sensors, cellular neural networks, chaotic systems, programmable analog circuits, and nonvolatile memory devices.

Area–Delay–Power Efficient Carry-Select Adder

Abstract: In this brief, the logic operations involved in conventional carry select adder (CSLA) and binary to excess-1 converter (BEC)-based CSLA are analyzed to study the data dependence and to identify redundant logic operations. We have eliminated all the redundant logic operations present in the conventional CSLA and proposed a new logic formulation for CSLA. In the proposed scheme, the carry select (CS) operation is scheduled before the calculation of final-sum, which is different from the conventional approach. Bit patterns of two anticipating carry words (corresponding to $c_{\rm in} = 0\ \hbox{and}\ 1$ ) and fixed $c_{\rm in}$ bits are used for logic optimization of CS and generation units. An efficient CSLA design is obtained using optimized logic units. The proposed CSLA design involves significantly less area and delay than the recently proposed BEC-based CSLA. Due to the small carry-output delay, the proposed CSLA design is a good candidate for square-root (SQRT) CSLA. A theoretical estimate shows that the proposed SQRT-CSLA involves nearly 35% less area–delay–product (ADP) than the BEC-based SQRT-CSLA, which is best among the existing SQRT-CSLA designs, on average, for different bit-widths. The application-specified integrated circuit (ASIC) synthesis result shows that the BEC-based SQRT-CSLA design involves 48% more ADP and consumes 50% more energy than the proposed SQRT-CSLA, on average, for different bit-widths.

Hardware Architecture for List Successive Cancellation Decoding of Polar Codes

Abstract: This brief presents a hardware architecture and algorithmic improvements for list successive cancellation (SC) decoding of polar codes. More specifically, we show how to completely avoid copying of the likelihoods, which is algorithmically the most cumbersome part of list SC decoding. The hardware architecture was synthesized for a blocklength of N = 1024 bits and list sizes L = 2, 4 using a UMC 90 nm VLSI technology. The resulting decoder can achieve a coded throughput of 181 Mb/s at a frequency of 459 MHz.

Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter

Abstract: This brief presents efficient distributed arithmetic (DA)-based approaches for high-throughput reconfigurable implementation of finite-impulse response (FIR) filters whose filter coefficients change during runtime. Conventionally, for reconfigurable DA-based implementation of FIR filter, the lookup tables (LUTs) are required to be implemented in RAM and the RAM-based LUT is found to be costly for ASIC implementation. Therefore, a shared-LUT design is proposed to realize the DA computation. Instead of using separate registers to store the possible results of partial inner products for DA processing of different bit positions, registers are shared by the DA units for bit slices of different weightage. The proposed design has nearly 68% and 58% less area-delay product and 78% and 59% less energy per sample than the DA-based systolic structure and the carry save adder (CSA)-based structure, respectively, for the ASIC implementation. A distributed-RAM-based design is also proposed for the field-programmable gate array (FPGA) implementation of the reconfigurable FIR filter, which supports up to 91 MHz input sampling frequency and offers 54% and 29% less the number of slices than the systolic structure and the CSA-based structure, respectively, when implemented in the Xilinx Virtex-5 FPGA device (XC5VSX95T-1FF1136).

Distributed ${\cal H}_{\infty}$ Consensus of Higher Order Multiagent Systems With Switching Topologies

Abstract: This brief addresses the distributed ${\cal H}_{\infty}$ consensus problem of multiagent systems with higher order linear dynamics and switching directed topologies. Without assuming that the directed communication topology is fixed or balanced, a class of distributed protocols is constructed and employed to achieve state consensus while guaranteeing a prescribed disturbance rejection objective, with both admissible exogenous disturbances and unknown initial states. By using tools from algebraic graph theory and switched systems theory, it is proven that the distributed ${\cal H}_{\infty}$ consensus in closed-loop multiagent systems with switching directed topologies can be achieved if the feedback gain matrix of the protocol is appropriately designed and the coupling strength among neighboring agents is larger than a derived positive value. Moreover, the consensus rate for the closed-loop nominal multi-agent systems is discussed.

A New Piecewise Linear Hyperchaotic Circuit

Abstract: When the polarity information in diffusionless Lorenz equations is preserved or removed, a new piecewise linear hyperchaotic system results with only signum and absolute-value nonlinearities. Dynamical equations have seven terms without any quadratic or higher order polynomials and, to our knowledge, are the simplest hyperchaotic system. Therefore, a relatively simple hyperchaotic circuit using diodes is constructed. The circuit re- quires no multipliers or inductors, as are present in other hyper- chaotic circuits, and it has not been previously reported.

Energy Efficient MIMO Relay Transmissions via Joint Power Allocations

Abstract: The energy efficient joint source-relay power allocation problem is studied for the multi-input multi-output (MIMO) amplify-and-forward two-hop relaying system, in which the objective of the optimization is the number of the bits per second per hertz per Joule with the guarantee of the minimum spectral efficiency (SE). By assuming perfect channel state information at the transmitter, the MIMO channel is divided into several single-input single-output (SISO) subchannels via singular value decomposition (SVD). The problem is first established as an optimization subject to the minimum SE constraint, in which it is observed that both of the cost function and the constraint are not convex. By employing the high signal-to-noise ratio (SNR) approximation, the problem becomes suddenly a pseudo-convex optimization problem. Yet, the difficulty comes from solving the final Lagrangian equation, which is tackled by our proposed relaxation method according to the Jensen inequality. Finally, the analytical expression is derived for the energy efficient power allocations of the multiple antennas at the source and at the relay. Simulations demonstrate the effectiveness of the proposed method.

Offset-Free Nonlinear MPC for Mismatched Disturbance Attenuation With Application to a Static Var Compensator

Abstract: A generalized nonlinear model predictive control augmented with a disturbance observer is proposed in this brief to solve the disturbance attenuation problem of nonlinear systems with arbitrary disturbance relative degree. It is shown that the disturbances can be removed from the output channels by the proposed method with appropriately designed disturbance compensation gain. The property of nominal performance recovery is retained with the proposed method. The effectiveness of the proposed method is validated by applying it to a static var compensator system.

A Low-Power Subthreshold to Above-Threshold Voltage Level Shifter

Abstract: This brief presents a power-efficient voltage level-shifter architecture that is capable of converting extremely low levels of input voltages to higher levels. In order to avoid the static power dissipation, the proposed structure uses a current generator that turns on only during the transition times, in which the logic level of the input signal is not corresponding to the output logic level. Moreover, the strength of the pull-up device is decreased when the pull-down device is pulling down the output node in order for the circuit to be functional even for the input voltage lower than the threshold voltage of a MOSFET. The operation of the proposed structure is also analytically investigated. Post-layout simulation results of the proposed structure in a 0.18-μm CMOS technology show that at the input low supply voltage of 0.4 V and the high supply voltage of 1.8 V, the level shifter has a propagation delay of 30 ns, a static power dissipation of 130 pW, and an energy per transition of 327 fJ for a 1-MHz input signal.

Finite-Time Containment Control for Second-Order Multiagent Systems Under Directed Topology

Abstract: This brief investigates the finite-time containment control for second-order multiagent systems with multiple dynamic leaders under a fixed directed communication topology. In particular, the studied systems are composed of the multiple dynamic leaders with bounded unknown acceleration inputs and the followers with bounded disturbances. A new continuous nonlinear containment control protocol is constructed via a nonsingular terminal sliding-mode scheme. The proposed protocol can effectively drive the states of the followers to track the convex hull spanned by those of the leaders within the finite time.

A Universal Mutator for Transformations Among Memristor, Memcapacitor, and Meminductor

Abstract: This brief proposes a universal mutator for transformations among memristor, memcapacitor, and meminductor by making use of only three off-the-shelf active devices. The mathematical relations among circuit variables before and after transformation are analyzed in terms of the connection combinations of five circuit elements. The experimental analysis of the transformed elements is discussed to further confirm the validation of this newly proposed transformation mutator. The good agreement between experimental and theoretical analyses verifies the practicability and flexibility of this mutator in realizing all six cases of transformations.

$l_{2}-l_{\infty}$ Suppression of Limit Cycles in Interfered Two-Dimensional Digital Filters: A Fornasini–Marchesini Model Case

Abstract: Recently, Ahn proposed an l 2 -l ∞ stability criterion for interfered two-dimensional (2-D) digital filters described by the Roesser model. However, until now, no criteria for interfered 2-D digital filters in the Fornasini-Marchesini (FM) model have been studied. As a continuation of the results, this brief proposes a new criterion for the l 2 -l ∞ suppression of limit cycles in interfered 2-D digital filters in the FM model. The proposed criterion ensures the asymptotic stability and l 2 -l ∞ performance of 2-D digital filters. The effectiveness of the proposed criterion is demonstrated using numerical examples. The work in this brief and that of the Roesser model provide, as an integrity, systematic results on limit cycle suppression for 2-D digital filters in the l 2 -l ∞ sense.

Boolean Logic Operations and Computing Circuits Based on Memristors

Abstract: This brief contributes to the design of computational and reconfigurable structures that exploit unique threshold-dependent switching response of single memristors and their compositions. A new logic circuit design paradigm, which assumes parallel processing of input signals, is proposed, along with a methodology for the construction of robust programmable composite memristive switches of variable precision. This methodology is applied to the design of memristive computing circuits. A SPICE simulation-based validation of the proposed circuits and systems is provided.

Variable Step-Size Affine Projection Sign Algorithm

Abstract: This brief proposes a novel variable step-size affine projection sign algorithm (APSA), which is characterized by its robustness against impulsive noises. To obtain a step size reasonably, the proposed algorithm investigates the mean-square deviation (MSD) of APSA. Because it is impossible to accurately compute the MSD of APSA, the proposed algorithm derives the upper bound of the MSD using the upper bound of the L1-norm of the measurement noise. The optimal step size is calculated at each iteration by minimizing the upper bound of the MSD, which improves the filter performance, with respect to the convergence rate and the steady-state estimation error. The simulation results demonstrate that the proposed algorithm improves the filter performance in a system-identification scenario in the presence of impulsive noises.

A Subthreshold Symmetric SRAM Cell With High Read Stability

Abstract: This brief introduces a differential eight-transistor static random access memory (SRAM) cell for subthreshold SRAM applications. The symmetric topology offers a smaller area overhead compared with other symmetric cells for the same stability in the read operation. Two transistors isolate the cell storage nodes from the read operation path to maintain the data stability of the cell. This topology improves the data stability at the expense of read operation delay. Thorough postlayout Monte Carlo worst corner simulations in 45-nm CMOS technology are conducted. The proposed cell operates down to 0.35 V with a read noise margin of 74 mV and a write noise margin of 92 mV. Under this condition, the read and write noise margins of the conventional six-transistor (6T) cell are 18 and 27 mV, respectively. The cell area is 1.57× the conventional 6T SRAM cell area in 45-nm design rules.

New Improved Algorithms for Compressive Sensing Based on $\ell_{p}$ Norm

Abstract: A new algorithm for the reconstruction of sparse signals, which is referred to as the lp-regularized least squares ( lp-RLS) algorithm, is proposed. The new algorithm is based on the minimization of a smoothed lp-norm regularized square error with p <; 1 . It uses a conjugate-gradient (CG) optimization method in a sequential minimization strategy that involves a two-parameter continuation technique. An improved version of the new algorithm is also proposed, which entails a bisection technique that optimizes an inherent regularization parameter. Extensive simulation results show that the new algorithm offers improved signal reconstruction performance and requires reduced computational effort relative to several state-of-the-art competing algorithms. The improved version of the lp-RLS algorithm offers better performance than the basic version, although this is achieved at the cost of increased computational effort.

Phase-Separated DCSK: A Simple Delay-Component-Free Solution for Chaotic Communications

Abstract: In this brief, a phase-separated differential chaos shift keying (PS-DCSK) modulation scheme is proposed as a simple delay-component-free version of DCSK modulation. Separated by orthogonal sinusoidal carriers rather than time delay, the reference and information-bearing signals in DCSK are transmitted simultaneously and parallel in the proposed system. As a result, PS-DCSK not only can avoid the difficult-to-implement radio-frequency delay line problem but also can achieve a doubled attainable data rate, enhanced communication security, and equivalent bit-error-rate (BER) performance with respect to DCSK. Finally, analytical expressions for the BER performance of the proposed system are derived and verified by computer simulation results over additive Gaussian white noise and Rayleigh fading channels.

Truly Random Number Generator Based on a Ring Oscillator Utilizing Last Passage Time

Abstract: This brief covers the design and fabrication of a ring oscillator-based truly random number generator (TRNG), which was fabricated in 013- $\mu\hbox{m}$ CMOS technology The randomness originates from the phase noise in a ring oscillator Timing jitter resulting from crossing the threshold multiple times, ie, last passage time (LPT), is exploited Previously, the jitter model was developed and applied to the core delay cell of the slow VCO, part of the ring oscillator, where a slow slew rate phase was introduced to greatly increase phase noise In this brief, the successful design of the entire TRNG was performed This includes designing the circuit to avoid introducing correlation in the TRNG Toward this end, novel timing circuitry is designed to properly control both the beginning and termination of this slow slew rate phase by tapping into the previous stage's output 1/f noise also has to be minimized Furthermore, the entire TRNG is now designed/implemented and fabricated, and experimental results are shown The fabricated ring oscillator was shown to possess a timing jitter of 15 ns Simulation under PVT variations of the entire cell shows that jitter variations are within 30%, showing that the designed control circuit was able to perform under such PVT variations Entropy simulation with power supply variations applied to the TRNG was also run to assess its effectiveness as the biasing condition is changing The randomness of the entire TRNG was assessed by applying the National Institute of Standards and Technology (NIST) tests On those tests recommended by NIST to have longer bit streams, additional test measurements were performed on bit streams with increased length Entropy tests for 20 k, 200 k, and 400 k measured bits were performed, resulting in entropy values all close to 1

Set-Membership NLMS Algorithm With Robust Error Bound

Abstract: A new robust error bound for the set-membership normalized least mean square (SMNLMS-REB) is proposed in this brief. The new robust set-membership error bound leads to improved robustness against impulsive noise and steady-state misalignment relative to those achieved in the set-membership normalized least mean square (SMNLMS) algorithm. Stability analysis shows that the proposed algorithm is stable. Using the individual weight error variance (IWV) analysis method, new expressions for the steady-state mean square deviation (MSD) of the SMNLMS-REB are also obtained. Simulation results on system identification show that the robustness and probability of the update (PU) of the proposed SMNLMS-REB considerably outperform the traditional SMNLMS and other robust set-membership NLMS algorithms in the presence of impulsive noise.

A Practical Implementation of a Floating Memristor-Less Meminductor Emulator

Abstract: A meminductor, a nonlinear two-terminal device with memory and energy storage ability, is generalized on the basis of the conception of a memristor. To date, the meminductor is commonly unavailable; therefore, it is of great significance to build a meminductor emulator in hardware. In this brief, a practical floating flux-controlled meminductor emulator is designed without using a memristor. Moreover, it possesses floating terminals and a variable structure that allow the designers to alter the nonlinear flux-controlled function only via utilization of fewer electronic components. Frequency-dependent current-flux dynamics of this meminductor have been captured in the experiment, which convincingly confirms the validity of this emulator. Finally, the experimental errors existing in the hardware circuit are analyzed. All the analysis results manifest that this newly proposed floating emulator can be operated as a floating meminductor and applied in the analog circuit design.

250-mV Supply Subthreshold CMOS Voltage Reference Using a Low-Voltage Comparator and a Charge-Pump Circuit

Abstract: This brief proposes a subthreshold CMOS voltage reference circuit, which reduces the minimum supply voltage by replacing the analog amplifier in the conventional CMOS voltage reference circuit with a low-voltage comparator, a charge-pump circuit, and a digital control circuit. The subthreshold CMOS voltage reference circuit was fabricated using a 0.11-μm CMOS process. Its core area was 0.013 mm 2 and it consumed 5.35 μW at V DD = 250 mV and f CLK = 1 MHz. Its minimum supply voltage was 242 mV. Ten sample chips generated 193-207-mV reference voltage with 0.4-3.2-mV/100-mV line sensitivity at V DD = 250-400 mV and 58-186 ppm/°C temperature coefficient at 10 °C-90 °C.

An Area-Efficient CMOS Time-to-Digital Converter Based on a Pulse-Shrinking Scheme

Abstract: An area-efficient CMOS time-to-digital converter (TDC) based on a pulse-shrinking scheme with an improved cyclic delay line is proposed to achieve low thermal sensitivity in this brief. First, by only thermally compensating the pulse-shrinking unit rather than all delay cells, a large number of compensated circuits could be removed to reduce costs, and the thermal sensitivity of the TDC was still greatly reduced. Additionally, based on the improved cyclic delay line with identical logic gates, an undesired shift resolution caused by the mismatch between the inhomogeneous gates can be successfully eliminated, and the effective resolution can be completely determined by the pulse-shrinking unit. The proposed circuit was fabricated in a Taiwan Semiconductor Manufacturing Company Limited (TSMC) 0.35- μm CMOS technology and has an extremely small chip area of 0.025 mm2, which is much smaller than the 0.12 mm2 of its predecessor. The effective resolution is approximately 40 ps/LSB (least significant bit), and the corresponding integral nonlinearity errors are all within ±0.6 LSB. The experimental results show that a ±5.5% resolution variation of the proposed TDC was achieved in a 0 °C-100 °C temperature range. The measured power consumption is 1.65 μW at a measurement rate of 10 samples/s.

Pinning Controllability Analysis of Complex Networks With a Distributed Event-Triggered Mechanism

Abstract: Pinning control synchronization of complex networks is a fascinating and hot issue in the field of nonlinear science. However, the existing works are all based on a continuous-time feedback control strategy and assume that each network node can have continuous access to the states of its neighbors. This brief presents a novel distributed event-triggered mechanism for pinning control synchronization of complex networks. The control of nodes is only triggered at their own event time, which effectively reduces the frequency of controller updates compared with continuous-time feedback control. Considering limited communication, the new approach successfully avoids the continuous communication used for calculating the error thresholds in the event-triggered mechanism. In addition, we also develop a new alternative iterative algorithm that can further reduce the consumption of computing and communication resources to some extent. Finally, simulation results show the effectiveness of the proposed approaches and illustrate the correctness of the theoretical results.

Latency Analysis and Architecture Design of Simplified SC Polar Decoders

Abstract: Recently, a low-latency decoding scheme called the simplified successive cancellation (SSC) algorithm has been proposed for polar codes. In this brief, we present the first systematic approach to formally derive the SSC decoding latency for any given polar code. The method to derive the SSC polar decoder architecture for any specific code is also presented. Moreover, the architecture of the precomputation SSC polar decoder is also proposed, which can further reduce the decoding latency. Compared with their SC decoder counterparts, the proposed SSC and precomputation SSC polar decoders can save up to 39.6% decoding latency with the same hardware cost.

An Energy-Efficient Low Frequency-Dependence Switching Technique for SAR ADCs

Abstract: This brief presents a highly energy-efficient switching scheme for successive approximation register (SAR) analog-to-digital converters that achieves a 95% reduction in switching energy over the conventional SAR The switching energy has been calculated by taking into account both the power drawn from reference and the power consumed by the switches themselves The frequency dependence of the switching energy has been studied and the proposed technique presents ways to maintain high energy efficiency over the entire frequency range of operation The results have been verified through behavioral and SPICE simulations

A 0.4-V, 90 $\sim$ 350-MHz PLL With an Active Loop-Filter Charge Pump

Abstract: A 0.4-V phase-locked loop (PLL) that has much improved power efficiency is realized in standard 65-nm CMOS. The PLL employs a novel ultralow-voltage charge pump that compensates current mismatch with an active loop filter and produces significantly reduced reference spurs. Its voltage-controlled oscillator (VCO) is designed with the body-bias technique and includes an automatic frequency calibration circuit that provides low VCO gain and wide tuning range. The PLL output frequency can be tuned from 90 to 350 MHz. At 350-MHz output, the PLL consumes 109 $\mu\hbox{W}$ , which corresponds to the power efficiency of 0.31 mW/GHz.

A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture

Abstract: A new Vernier time-to-digital converter (TDC) architecture using a delay line and a chain of delay latches is proposed. The delay latches replace the functionality of one delay chain and the sample ...

A Digital Timing Mismatch Calibration Technique in Time-Interleaved ADCs

Abstract: A digital calibration scheme is proposed to minimize the timing mismatch in time-interleaved analog-to-digital converters (TIADCs). First, the scheme is to subtract the outputs from adjacent channel ADCs and to utilize the expectations of the absolute value of the subtracted results to represent the actual sampling time interval. The timing mismatch is recognized by comparing these expectations. The obtained information is fed back to adjust variable delay buffers, thus reducing the timing mismatch. The application of this scheme to a 12-bit 1.6 GS/s four-channel TIADC is demonstrated. Simulation results show that with an input signal whose bandwidth is limited to the Nyquist frequency, the proposed timing mismatch calibration scheme is effective and capable of reducing the mismatch to the minimum. Compared with traditional calibration schemes, the proposed scheme is more feasible to implement and consumes less power and chip area.

A 19-nW 0.7-V CMOS Voltage Reference With No Amplifiers and No Clock Circuits

Abstract: This brief provides a novel voltage reference circuit that uses four optimization techniques to effectively save power dissipation: 1) All the amplifiers have been eliminated, but two important voltages are still successfully equalized without using any amplifier; 2) the clock circuits are not required in the proposed design; 3) there is no need for extra biasing circuit; and 4) all the MOS transistors are in the subthreshold region to make the power supply voltage low. Moreover, a trimming circuit has been adopted to ensure the accuracy of the reference voltage. This novel voltage reference circuit has been fabricated with the Semiconductor Manufacturing International Corporation 0.18-μm 1.8-V CMOS process. The measurement results show that the power consumption is only 19 nW, the power supply voltage is only 700 mV, the temperature coefficient is 22.11 ppm/°C under a temperature of -25 °C-+85 °C, and the line sensitivity is as good as 571 μV/V.