Showing papers in "IEEE Transactions on Components and Packaging Technologies in 2002"

Dynamic lithium-ion battery model for system simulation

Abstract: Presents here a complete dynamic model of a lithium ion battery that is suitable for virtual-prototyping of portable battery-powered systems. The model accounts for nonlinear equilibrium potentials, rate- and temperature-dependencies, thermal effects and response to transient power demand. The model is based on publicly available data such as the manufacturers' data sheets. The Sony US18650 is used as an example. The model output agrees both with manufacturer's data and with experimental results. The model can be easily modified to fit data from different batteries and can be extended for wide dynamic ranges of different temperatures and current rates.

Power and life extension of battery-ultracapacitor hybrids

Abstract: The performance of a battery-ultracapacitor hybrid power source under pulsed load conditions is analytically described using simplified models. We show that peak power can be greatly enhanced, internal losses can be considerably reduced, and that discharge life of the battery is extended. Greatest benefits are seen when the load pulse rate is higher than the system eigenfrequency and when the pulse duty is small. Actual benefits are substantial; adding a 23 F ultracapacitor bank (3 /spl times/ 7 PC10 ultracapacitors) in parallel with a typical Li-ion battery of 7.2 V and 1.35 A hr capacity can boost the peak power capacity by 5 times and reduce the power loss by 74%, while minimally impacting system volume and weight, for pulsed loads of 5 A, 1 Hz repetition rate, and 10% duty.

Closed-loop electroosmotic microchannel cooling system for VLSI circuits

Abstract: The increasing heat generation rates in VLSI circuits motivate research on compact cooling technologies with low thermal resistance. This paper develops a closed-loop two-phase microchannel cooling system using electroosmotic pumping for the working fluid. The design, fabrication, and open-loop performance of the heat exchanger and pump are summarized. The silicon heat exchanger, which attaches to the test chip (1 cm/sup 2/), achieves junction-fluid resistance near 0.1 K/W using 40 plasma-etched channels with hydraulic diameter of 100 /spl mu/m. The electroosmotic pump, made of an ultrafine porous glass frit with working volume of 1.4 cm/sup 3/, achieves maximum backpressure and flowrate of 160 kPa and 7 ml/min, respectively, using 1 mM buffered de-ionized water as working fluid. The closed-loop system removes 38 W with pump power of 2 W and junction-ambient thermal resistance near 2.5 K/W. Further research is expected to strongly reduce the thermal resistance for a given heating power by optimizing the saturation temperature, increasing the pump flowrate, eliminating the thermal grease, and optimizing the heat exchanger dimensions.

Current and future miniature refrigeration cooling technologies for high power microelectronics

Abstract: Utilizing refrigeration may provide the only means by which future high-performance electronic chips can be maintained below predicted maximum temperature limits. Widespread application of refrigeration in electronic packaging will remain limited, until the refrigerators can be made sufficiently small so that they can be easily incorporated within the packaging. A review of existing microscale and mesoscale refrigeration systems revealed that only thermoelectric coolers (TECs) are now commercially available in small sizes. However, existing TECs are limited by their maximum cooling power and low efficiencies. A simple model was constructed to analyze the performance of both existing and predicted future TECs, in an electronic packaging environment. Comparison with the cooling provided by an existing high-performance fan shows that they are most effective for heat loads less than approximately 100 W, but that for higher heat loads, fan air cooling actually yields a lower junction temperature. Thermal resistance between the refrigerator and the chip is not as critical as the thermal resistance between the refrigerator and the ambient air.

Measuring partial thermal resistances in a heat-flow path

Abstract: The paper presents techniques of measuring partial steady state thermal resistance values in a heat flow path with the help of thermal transient measurements and the subsequent numerical evaluation The method is based on the further evaluation of the structure functions of the heat flow path After presenting the theoretical background of the evaluation two different practical examples are presented to demonstrate the use of the method The first example presents a series of experiments on how to use the method to detect die attach and/or soldering failures in packaged devices The second example demonstrates that the method can be applied to measure the very small R/sub th/ values of thin conducting layers Various practical solutions are discussed and demonstrated by simulations The chances and the limits of the methodology are discussed in detail in the conclusion section

Silver-indium joints produced at low temperature for high temperature devices

Abstract: A two-step fluxless bonding process adopted to produce high temperature silver-indium joints (80 wt% silver and 20 wt% indium) at relatively low process temperature of 206/spl deg/C has been developed. After annealing the joint continuously for 26 h at 145/spl deg/C, its melting temperature increases to 765-780/spl deg/C, as confirmed by a de-bonding test. The technique thus developed provides a viable alternative to packaging many high temperature devices running at 350/spl deg/C and above. The bonding quality of the Ag-In joints produced was examined using scanning acoustic microscopy. The joint cross-section was also studied using a scanning electron microscope equipped with an energy dispersive X-ray (EDX) spectroscope to find the local microstructure and composition. The results have shown that the joint is nearly void-free and uniform in thickness ranging from 7.2 to 7.8 /spl mu/m. The annealed sample joint, as determined by EDX, is mainly composed of AgIn/sub 2/, Ag/sub 2/In, and AuIn/sub 2/ grains embedded in an Ag-rich Ag-In alloy matrix. During joint formation, the intermetallic compound AgIn/sub 2/, in particular, prevents the indium layer from oxidation, and therefore, no flux is needed. In addition, low process temperatures help to reduce the thermal stresses developed in the bonded structure due to thermal expansion mismatch. Finally, reliability tests were conducted on three sets of annealed joints using a high temperature oven running continuously at 500/spl deg/C for 10, 100, and 1000 h each. Scanning acoustic microscopy (SAM) images on these samples confirmed that the joints have an excellent survivability in a high temperature environment.

Dynamically inserting, operating, and eliminating thermal sensors of FPGA-based systems

Abstract: In this paper, a new thermal monitoring strategy suitable for field programmable logic array (FPGA)-based systems is developed. The main idea is that a fully digital temperature transducer can be dynamically inserted, operated, and eliminated from the circuit under test using run-time reconfiguration. A ring-oscillator together with its auxiliary blocks (basically counting and control stages) is first placed in the design. After the actual temperature of the die is captured, the value is read back via the FPGA configuration port. Then, the sensor is eliminated from the chip in order to release programmable resources and avoid self-heating. All the hardware of the sensor is written in Java, using the JBits API provided by the chip manufacturer. The main advantage of the technique is that the sensor is completely stand-alone, no I/O pads are required, and no permanent use of any FPGA element is done. Additionally, the sensor is small enough to arrange an array of them along the chip. Thus, FPGAs became a new tool for researchers interested in the thermal aspects of integrated circuits.

Design and performance evaluation of a compact thermosyphon

Abstract: Thermosyphons are a promising option for cooling of high heat dissipating electronics. In this paper, the first known implementation of a compact two-phase thermosyphon for cooling of a microprocessor in a commercial desktop computer is presented. The implemented thermosyphon involves four components in a loop: an evaporator with a boiling enhancement structure, a rising tube, a condenser and a falling tube. The performance of the thermosyphon with water and PF5060 as working fluids, and the effect of inclination are studied experimentally under laboratory conditions. Experimental observations are also made at actual operating conditions to monitor the thermal behavior with changes in power output of the microprocessor. The inside cabinet of the desktop computer is also numerically simulated to understand the airside performance of the condenser.

Warpage measurement comparison using shadow Moire and projection Moire methods

Abstract: Microelectronic and photonic packaging are progressing toward integrating more devices with more functions into a smaller confined space, while requiring higher yield and superior reliability. New electronic components, materials, fabrication processes, and configurations are emerging to achieve these goals. As expected, surface flatness is playing a more crucial role in integrated circuits and integrated optics manufacturing. Out-of-plane displacement (warpage) is a global effect of interfacial stress and displacement. It is also the cause of mis-registration and noncontact between components and their substrates. Moire methods offer noncontact, full-field, high-resolution approaches for measuring warpage. In this paper, two types of Moire methods are introduced and analyzed. They carry distinct features and grant more options to measure warpage under various scenarios. It has been shown through system analysis and experimental results that these systems are powerful tools for studying warpage mechanisms. Specifically, they can help to investigate the effects of materials, manufacturing processes, and packaging configurations on warpage.

Three-dimensional x-ray laminography as a tool for detection and characterization of BGA package defects

Abstract: Non-destructive examination of the layers of a built-up substrate was achieved using three-dimensional (3-D) x-ray microlaminography, with successful separation of layers as thin as 8 /spl mu/m. The same technology was used to create reconstructed images of both surface and internal details of inner solder balls in a ball grid array package soldered to a printed circuit board. Microlaminography was also used to identify bond-wire shorts in the plane of the solder resist of a ball grid array assembly, and these were subsequently verified by destructive physical analysis. This plane is 20 /spl mu/m thick and immediately adjoining a plane of copper traces; the success demonstrates the capability of microlaminography to resolve and separate very fine detail internally within IC structures. The limits of capability of this machine were also determined; it was found that a crack of approximately 5 /spl mu/m wide in a copper trace of a BGA was not detected by the machine. As an introduction, the technology and methodology of 3-D x-ray microlaminography are explained. The results from a microlaminography system adapted for failure analysis in integrated circuit packaging are presented. It is shown that such results could not be extracted by two-dimensional (2-D) x-ray or other nondestructive methods.

Thermal challenges in next generation electronic systems - summary of panel presentations and discussions

Abstract: The presentations made, as well as the discussions, in the panels at the workshop, Thermal Challenges in Next Generation Electronic Systems (THERMES), are summarized in this paper. The panels dealt with diverse topics including thermal management roadmaps, microscale cooling systems, numerical modeling from the component to system levels, hardware for future high performance and Internet computing architectures, and transport issues in the manufacturing of electronic packages. The focus of the panels was to identify barriers to further progress in each area that require the attention of the research community.

Dynamics and topology optimization of piezoelectric fans

Abstract: Piezoelectric fans are very low power, small, very low noise, solid-state devices that have recently emerged as viable thermal management solutions for a variety of portable electronics applications including laptop computers, cellular phones and wearable computers. Piezoelectric fans utilize piezoceramic patches bonded onto thin, low frequency flexible blades to drive the fan at its resonance frequency. The resonating, low frequency blade creates a streaming airflow directed at key electronics components. The optimization of a piezoelectric fan with two symmetrically placed piezoelectric patches is investigated through an analytical Bernoulli-Euler model as well as a finite element (FE) model of the composite piezo-beam. The closed form analytical solution is used to demonstrate that different optimal piezoceramic-to-blade length ratios and piezoceramic-to-blade thickness ratios exist for maximizing the electromechanical coupling factor (EMCF), tip deflection and rotation. Such optimization procedures provide simple design guidelines for the development of very-low power, high flow rate piezoelectric fans.

Spreading in the heat sink base: phase change systems or solid metals??

Abstract: Presently, the microelectronics industry needs thermal solutions that are able to dissipate high heat fluxes at low thermal resistance. The majority of original equipment manufacturers (OEMs) within the microelectronics industry would like to achieve this by extending the application of air-cooling technologies since it implies minimal impact to the design of computer systems and is known to be a cost effective solution space. Spreading resistance through the base of the heat sink is one major component of the total thermal resistance from the silicon junction to the local ambient, especially if larger volume heat sinks are to be used. Until now, most of the research has focused on using phase change systems (i.e., vapor chambers) for reducing the spreading resistance of the heat sink base. Since no significant improvements have been achieved, there is a need to determine the envelope of the limitations for phase change-heat spreaders used in processor cooling, and to compare their performance against high thermal conductivity solid metals. Two simple models are presented to address the heat transfer limitations in phase change systems. Using these models, the ratio of phase change spreading resistance over solid metal spreading can be estimated.

Design and optimization of air-cooled heat sinks for sustainable development

Abstract: The development of heat sinks for microelectronic applications, which are compatible with sustainable development, involves the achievement of a subtle balance between a superior thermal design, minimum material consumption, and minimum pumping power. Due to the rapid proliferation of electronic systems, substantial material streams and energy consumption rates are associated with the cooling of computers, as well as other categories of electronic equipment. This presentation explores the potential for the least-energy optimization of natural- and forced-convection cooled rectangular plate heat sinks. The results are evaluated in terms of a heat sink coefficient of performance, relating the cooling capability to the energy invested. Guidelines for "sustainable" heat sink designs are suggested.

Wire bonding to advanced copper, low-K integrated circuits, the metal/dielectric stacks, and materials considerations

Abstract: There are three areas to consider when designing/implementing wire bonding to advanced ULSI damascene-copper chips having copper metallization and low dielectric-constant polymers embedded beneath them (Cu/LoK). These are: 1) the copper-pad top-surface oxidation inhibitor coating - metal/organic/inorganic. (Current work involves evaluating the metal and inorganic options); 2) the low dielectric constant materials available; 3) under-pad metal/polymer stacks and support structures necessary for bondability and reliability. There are also various polymer/metallurgical interactions, resulting in long term packaged-device reliability problems, that can occur as the result of the wire bonding process over low modulus, LoK materials with barriers. These include cracked diffusion barriers, copper diffusion into the LoK polymers, cracking/spalling/crazing of the LoK materials, and bond pad indentation ("cupping"). Low-K polymer materials, with high expansion coefficients and low thermal conductivities, can also increase the stress and further extend any existing damage to barriers. Well designed LoK and the underpad structures should have no negative effect on bonding parameters and be invisible to the bonding process.

Effective elastic modulus of underfill material for flip-chip applications

Abstract: In this paper, a micromechanics model based on the Mori-Tanaka method was developed to estimate the elastic modulus of underfill materials. An explicit expression of the underfill modulus was derived as a function of filler content and the properties of the matrix and the fillers. Predictions of the modulus from this theory were compared with experimentally measured values. Excellent agreement was observed.

Characterization of compact heat sink models in natural convection

Abstract: In this study, an approximate analytical-numerical procedure is used to model natural convection cooling of heat sinks using electronics cooling software. The analysis evolves in two stages: a numerical simulation of the detailed heat sink, and a simulation of a compact model that exhibits similar thermal and flow resistance characteristics to those of the actual heat sink. From the analysis, the thermal resistance of the heat sink is evaluated. Subsequently, the effective thermal conductivity that must be assigned to the compact heat sink is determined using the Nusselt number correlation for free convection over a vertical plate. Due to the algebraic form of the Nusselt number correlation, the effective thermal conductivity is determined in an iterative fashion. The purpose of a compact heat sink is to reduce computational effort while retaining a desired level of accuracy. In this article, the compact modeling scheme is first applied to either an extruded or a pin-fin heat sink in order to validate the procedure under laminar conditions. Subsequently, the same approach is applied to a multichip system consisting of a set of pin-fin heat sinks placed in series. At both individual and system-level models, it is found that the compact approach results in substantial savings in mesh size and computing time. These savings are accompanied by a small acceptable error that is less than 10% relative to the detailed model predictions.

Arc motion and gas flow in current limiting circuit breakers operating with a low contact switching velocity

Abstract: Arc motion in low voltage (240 VAC) high current (10/sup 3/-10/sup 4/A.) current limiting-circuit breakers is dominated by arc root mobility. The mobility is influenced by the gas flow and gas composition in the contact region, but there is little experimental data on these effects. New pressure and spectral data measurement during arc movement are presented using a flexible test apparatus and an arc imaging system. These measurements are used to investigate gas flow characteristics in the arc chamber. The chemical and physical phenomena occurring during the arc motion are discussed. The combination of optical and spectral data provides new insight into the arc motion. The influences of arc chamber material, contact material, and contact opening speed, are investigated to improve arc control for a low contact opening velocity.

In-plane effective thermal conductivity of plain-weave screen laminates

Abstract: A simple-to-fabricate woven mesh, consisting of bonded laminates of two-dimensional plain-weave conductive screens is described. Geometric equations show that these porous matrices can be fabricated to have a wide range of porosity and specific surface area, /spl beta/. A heat transfer model is developed. It shows that the laminates can have a highly anisotropic thermal conductivity vector, with in-plane effective thermal conductivities ranging up to 78.5% of base material values. A technique to measure the laminate in-plane effective thermal diffusivity is described. Measurements of the in-plane effective thermal diffusivity of copper plain-weave laminates are used to benchmark the model.

Effects of build-up printed circuit board thickness on the solder joint reliability of a wafer level chip scale package (WLCSP)

Abstract: The creep analyses of solder-bumped wafer level chip scale package (WLCSP) on build-up printed circuit board (PCB) with microvias subjected to thermal cyclic loading are presented. The emphasis of this study is placed on the effects of the thickness of the PCB with a microvia build-up layer on the solder joint reliability of the WLCSP assembly. The 62Sn-2Ag-36Pb solder joints are assumed to follow the Garofalo-Arrhenius creep constitutive law. The shear stress and creep shear strain hysteresis loops, shear stress range, creep shear strain range, and creep strain energy density range at different locations in the corner solder joint are presented for a better understanding of the thermal-mechanical behaviors of the solder-bumped WLCSP on build-up PCB with microvias. It is found that, due to the large coefficient of thermal expansion of the build-up resin, the effects of thickness of the PCB with microvia build-up layer become much more significant than that without the microvia build-up layer.

Numerical simulation of the drop impact response of a portable electronic product

Abstract: The ability of portable electronic products like cellular phones and personal digital assistants to withstand accidental impacts and shock is a valuable attribute consumers expect and manufacturers desire. Usually, manufacturers conduct expensive experimental drop tests to determine the fragility of such products during the product design cycle. An alternative to conducting drop tests is to perform numerical simulation. This paper examines the feasibility of studying the drop impact response of an electronic pager using a finite element software, ABAQUS/Explicit. Experimental drop test results are then used to compare with that of numerical simulation. Parameters examined include surface strains on pager housing and impact force. Comparisons show good correlation between experimental and numerical results. Finite element computation allows critical impact orientations and drop heights to be identified so that selective experimental drop tests can be performed to determine the actual physical robustness of these products.

Humidity management of outdoor electronic equipment: methods, pitfalls, and recommendations

Abstract: Discusses the basics of the three approaches to mitigation of humidity related failures namely; 1) relative humidity control module (RHCM); 2) absolute humidity control (AHCM); 3) use of potting and coating, as well as conditions and limitations of their applicability. The RHCM approach (or Saturation Limit Control) uses heat dissipation from electronics to maintain an appropriate temperature difference between ambient and the critical surfaces to lower RH in their vicinity and at same time through the use of diffusion plugs ensures a relatively fast humidity equilibration between the enclosure air and ambient to minimize condensation caused by cold fronts and radiation cooling. The AHCM approach relies on minimization of water ingress through selection of appropriate materials and design and at same time uses desiccant to remove the water which made its way into the enclosure. The choice between these schemes depends mostly on thermal considerations. The more expensive and sensitive to errors AHCM scheme has to be used when the energy dissipation is either not high enough or it is highly dependent on the traffic.

Thermal issues in MEMS and microscale systems

Abstract: Transduction mechanisms involving thermal phenomena play a central role in a wide range of microelectromechanical systems (MEMS) applications. An overview of a subset of thermal issues in MEMS technology is presented, including a discussion of traditional and emerging applications for microscale thermal systems. Issues relating to fundamental limitations and opportunities in thermal microsystems are presented. The use of thermal phenomena in three specific microsystems is reviewed, namely microhotplate chemical sensors, microfluidic systems, and electrothermal micromotors. Future directions in microscale and nanoscale thermal systems are presented.

The conceivable accuracy of experimental and numerical thermal analyses of electronic systems

Abstract: In the past decade, we have observed a significant worldwide increase in the use of computational codes to calculate the thermal behavior of electronic systems. The benefits of these 'virtual prototyping tools' are undisputed when it comes to performing parametric studies in early design phases. However, when the objective of the calculation is accuracy, as required for subsequent reliability and performance assessments, the discussion about the level of accuracy that we can expect in practice becomes far from trivial, as will be shown in this paper. A natural question is how accurate numerical simulations are when compared to well-designed experiments in prototypes or final products. Many studies demonstrate amazing agreement, the conclusion often being that 'validation of the numerical model' has been proven. It will be demonstrated that these conclusions are subject to serious doubts. This paper discusses 'every' topic associated with a comparison between numerical and experimental results that is based on first principles, not on fitting parameters until the two results match. The final conclusion is inevitable: the situation when all computations at the system level can be used for accurate temperature prediction is still a long way off.

Electroless nickel bumping of aluminum bondpads. I. Surface pretreatment and activation

Abstract: Electroless nickel bumping of aluminum (Al) bond-pads followed by solder paste printing is seen as one of the lowest cost routes for the bumping of wafers prior to flip-chip assembly. However, the electroless nickel bumping of Al bondpads is not straightforward and a number of activation steps are necessary to enable the nickel deposit to form a strong, electrically conductive bond with the Al. For the electroless nickel coating of mechanical components made of aluminum, a zincate activation process has been used for many years; however, extension of these techniques to semiconductor wafers requires careful control over these pretreatments to avoid damage to the very thin bondpads. This paper reports a number of experiments designed to characterize the activation of Al bondpads to electroless nickel plating, focusing on the effects of solution exposure time and bondpad composition. In addition, the results are discussed in the context of other studies presented in the literature to provide an understanding of the mechanism of the zincate activation process applied to Al bondpads.

Thermal modeling and management in ultrathin chip stack technology

Abstract: This paper presents a thermal modeling for power management of a new three-dimensional (3-D) thinned dies stacking process. Besides the high concentration of power dissipating sources, which is the direct consequence of the very interesting integration efficiency increase, this new ultra-compact packaging technology can suffer of the poor thermal conductivity (about 700 times smaller than silicon one) of the benzocyclobutene (BCB) used as both adhesive and planarization layers in each level of the stack. Thermal simulation was conducted using three-dimensional (3-D) FEM tool to analyze the specific behaviors in such stacked structure and to optimize the design rules. This study first describes the heat transfer limitation through the vertical path by examining particularly the case of the high dissipating sources under small area. First results of characterization in transient regime by means of dedicated test device mounted in single level structure are presented. For the design optimization, the thermal draining capabilities of a copper grid or full copper plate embedded in the intermediate layer of stacked structure are evaluated as a function of the technological parameters and the physical properties. It is shown an interest for the transverse heat extraction under the buffer devices dissipating most the power and generally localized in the peripheral zone, and for the temperature uniformization, by heat spreading mechanism, in the localized regions where the attachment of the thin die is altered. Finally, all conclusions of this analysis are used for the quantitative projections of the thermal performance of a first demonstrator based on a three-levels stacking structure for space application.

Reliability of PBGA assemblies under out-of-plane vibration excitations

Abstract: Vibration testing of plastic ball grid array (PBGA) assemblies to assess the reliability of the solder joints under external vibration excitations was reported in this paper. The test vehicle was an assembly with four 256 I/Os PBGA modules assembled on a printed circuit board (PCB). During the test, the assembly was clamped at two opposite sides to a vibration shaker. It was found that the dynamic displacement of the assembly under external out-of-plane sinusoidal vibration excitations was highly nonlinear. In order to determine the reliability of the solder joints, the resistance of each module was continuously monitored during the test. Under an out-of-plane sweep sinusoidal excitation with a constant acceleration amplitude of 2.5 G within a narrow frequency band around the fundamental resonant frequency of the assembly, the first-time-to-failure and mean-time-to-failure of the solder joints were found to be 0.46 and 6.19 million vibration cycles respectively. The failed solder joints were at the corners of the PBGA module. Most failures were due to cracks near the copper pad on the PCB side.

Fully process-compatible layout design on bond pad to improve wire bond reliability in CMOS ICs

Abstract: During manufacture of wire bonding in packaged IC products, the breaking of bond wires and the peeling of bond pads occur frequently. The result is open-circuit failure in IC products. There were several prior methods reported to overcome these problems by using additional process flows or special materials. In this paper, a layout method is proposed to improve the bond wire reliability in general CMOS processes. By changing the layout patterns of bond pads, the reliability of bond wires on bond pads can be improved. A set of different layout patterns of bond pads has been drawn and fabricated in a 0.6-/spl mu/m single-poly triple-metal CMOS process for investigation by the bond wire reliability tests, the ball shear test and the wire pull test. By implementing effective layout patterns on bond pads in packaged IC products, not only the bond wire reliability can be improved, but also the bond pad capacitance can be reduced for high frequency application. The proposed layout method for bond pad design is fully process-compatible to general CMOS processes.

Enhanced electronic system reliability - challenges for temperature prediction

Abstract: Using telecommunication as an example, it is argued that the electronics industry badly needs a change in attitude toward reliability thinking. The role of thermal design and reliability qualification is discussed in context of current industrial needs for short design cycles and rapid implementation of new technologies. Current and future practices are discussed in the context of newly-emerging reliability standards. Finally, two multi-company projects targeting the improvement of reliability through better temperature-related information are described.

Experimental and theoretical characterization of an antiferroelectric ceramic capacitor for power electronics

Abstract: Capacitance-voltage (C-V) measurements up to 800 VDC were made on a modified lead-zirconate (PbZrO/sub 3/) 20-layer multilayer ceramic (MLC) antiferroelectric power-electronic capacitor, with large energy-density storage capability. For these a precision impedance analyzer was used, in conjunction with a high-voltage capacitor dc-bias circuit configured for voltage-isolation from the analyzer input. A peak effective permittivity /spl epsiv/ /spl sim/ 4300 was derived at the capacitance peak of 133 nF at 400-V dc-bias, yielding an energy density storage of /spl sim/0.5 J/cc in the device volume of 0.022 cc. Modeling of the experimental C-V response was applied to three conceptual series-connected capacitance regions within each grain and grain-boundary region of the MLC. The equivalent capacitance component for the first region was derived from the voltage-dependent polarizations within a ferroelectric and/or antiferroelectric grain. This involved application of differing Langevin functions for modeling the ferroelectric and antiferroelectric polarizations. That for the second region related to the voltage and frequency dependence of the equivalent p-n junction capacitance at opposite sides of a grain-boundary and compensation-region, with Debye-type relaxation constants relating its frequency dependence. The third capacitance region was associated with the insulator-barrier region itself. Agreement between experimental and theoretical C-V-f responses was considered to be good, in view of the number of modeling parameters and variables employed.