IEEE Transactions on Components, Packaging and Manufacturing Technology 

About: IEEE Transactions on Components, Packaging and Manufacturing Technology is an academic journal published by Institute of Electrical and Electronics Engineers. The journal publishes majorly in the area(s): Materials science & Heat sink. It has an ISSN identifier of 2156-3950. Over the lifetime, 2813 publications have been published receiving 38146 citations. The journal is also known as: Components, packaging, and manufacturing technology, IEEE transactions on & T-CPMT.

High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV)

Abstract: We propose a high-frequency scalable electrical model of a through silicon via (TSV). The proposed model includes not only the TSV, but also the bump and the redistribution layer (RDL), which are additional components when using TSVs for 3-D integrated circuit (IC) design. The proposed model is developed with analytic RLGC equations derived from the physical configuration. Each analytic equation is proposed as a function of design parameters of the TSV, bump, and RDL, and is therefore, scalable. The scalability of the proposed model is verified by simulation from the 3-D field solver with parameter variations, such as TSV diameter, pitch between TSVs, and TSV height. The proposed model is experimentally validated through measurements up to 20 GHz with fabricated test vehicles of a TSV channel, which includes TSVs, bumps, and RDLs. Based on the proposed scalable model, we analyze the electrical behaviors of a TSV channel with design parameter variations in the frequency domain. According to the frequency-domain analysis, the capacitive effect of a TSV is dominant under 2 GHz. On the other hand, as frequency increases over 2 GHz, the inductive effect from the RDLs becomes significant. The frequency dependent loss of a TSV channel, which is capacitive and resistive, is also analyzed in the time domain by eye-diagram measurements. Due to the frequency dependent loss, the voltage and timing margins decrease as the data rate increases.

Die Attach Materials for High Temperature Applications: A Review

Abstract: The need for high power density and high temperature capabilities in today's electronic devices continues to grow. More robust devices with reliable and stable functioning capabilities are needed, for example in aerospace and automotive industries as well as sensor technology. These devices need to perform under extreme temperature conditions, and not show any deterioration in terms of switching speeds, junction temperatures, and power density, and so on. While the bulk of research is performed to source and manufacture these high temperature devices, the device interconnect technology remains under high focus for packaging. The die attach material has to withstand high temperatures generated during device functioning and also cope with external conditions which will directly determine how well the device performs in the field. This literature work seeks to review the numerous research attempts thus far for high temperature die attach materials on wide band gap materials of silicon carbide, gallium nitride and diamond, document their successes, concerns and application possibilities, all of which are essential for high temperature reliability.

3-D Printed Metal-Pipe Rectangular Waveguides

Abstract: This paper first reviews manufacturing technologies for realizing air-filled metal-pipe rectangular waveguides (MPRWGs) and 3-D printing for microwave and millimeter-wave applications. Then, 3-D printed MPRWGs are investigated in detail. Two very different 3-D printing technologies have been considered: low-cost lower-resolution fused deposition modeling for microwave applications and higher-cost high-resolution stereolithography for millimeter-wave applications. Measurements against traceable standards in MPRWGs were performed by the U.K.’s National Physical Laboratory. It was found that the performance of the 3-D printed MPRWGs were comparable with those of standard waveguides. For example, across X-band (8–12 GHz), the dissipative attenuation ranges between 0.2 and 0.6 dB/m, with a worst case return loss of 32 dB; at W-band (75–110 GHz), the dissipative attenuation was 11 dB/m at the band edges, with a worst case return loss of 19 dB. Finally, a high-performance W-band sixth-order inductive iris bandpass filter, having a center frequency of 107.2 GHz and a 6.8-GHz bandwidth, was demonstrated. The measured insertion loss of the complete structure (filter, feed sections, and flanges) was only 0.95 dB at center frequency, giving an unloaded quality factor of 152—clearly demonstrating the potential of this low-cost manufacturing technology, offering the advantages of lightweight rapid prototyping/manufacturing and relatively very low cost when compared with traditional (micro)machining.

Low-Cost Thin Glass Interposers as a Superior Alternative to Silicon and Organic Interposers for Packaging of 3-D ICs

Abstract: Interconnecting integrated circuits (ICs) and 3-D-ICs to the system board (printed circuit board) are currently achieved using organic or silicon-based interposers. Organic interposers face several challenges in packaging 2-D and 3-D-ICs beyond the 32-nm node, primarily due to their poor dimensional stability and coefficient of thermal expansion (CTE) mismatch to silicon. Silicon interposers made with back-end of line wafer processes can achieve the required wiring and I/O density, but their high-cost limit them to high-performance applications. Glass is proposed as a superior alternative to organic and silicon-based interposers for packaging of future ICs and 3-D-ICs with highest I/Os at lowest cost. This paper presents for the first time a novel thin and large panel glass interposer capable of scaling to 700 mm and larger panels with potential for significant cost reduction over interposers made on 200-mm or 300-mm wafers. The formation of small through vias at high speed has been the biggest technical barrier for the adoption of glass as an interposer and system substrate; and this paper describes pioneering research in via-formation in thin glass substrates, using a novel “polymer-on-glass” approach. Electrical modeling and design of through package vias (TPVs) in glass is discussed in detail, and the feasibility of 50-μm pitch TPVs in 180-μm thin glass substrates has been demonstrated. The excellent surface finish and low CTE of glass leads to increased I/O density, and increased functionality per unit area leading to system miniaturization.

Modeling and Analysis of Through-Silicon Via (TSV) Noise Coupling and Suppression Using a Guard Ring

Abstract: In three-dimensional integrated circuit (3D-IC) systems that use through-silicon via (TSV) technology, a significant design consideration is the coupling noise to or from a TSV. It is important to estimate the TSV noise transfer function and manage the noise-tolerance budget in the design of a reliable 3D-IC system. In this paper, a TSV noise coupling model is proposed based on a three-dimensional transmission line matrix method (3D-TLM). Using the proposed TSV noise coupling model, the noise transfer functions from TSV to TSV and TSV to the active circuit can be precisely estimated in complicated 3D structures, including TSVs, active circuits, and shielding structures such as guard rings. To validate the proposed model, a test vehicle was fabricated using the Hynix via-last TSV process. The proposed model was successfully verified by frequency- and time-domain measurements. Additionally, a noise isolation technique in 3D-IC using a guard ring structure is proposed. The proposed noise isolation technique was also experimentally demonstrated; it provided -17 dB and -10dB of noise isolation between the TSV and an active circuit at 100 MHz and 1 GHz, respectively.