IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B 

About: IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B is an academic journal. The journal publishes majorly in the area(s): Integrated circuit packaging & Soldering. It has an ISSN identifier of 1070-9894. Over the lifetime, 295 publications have been published receiving 7115 citations.

A review of 3-D packaging technology

Abstract: This paper reviews the state-of-the-art in three-dimensional (3-D) packaging technology for very large scale integration (VLSI). A number of bare dice and multichip module (MCM) stacking technologies are emerging to meet the ever increasing demands for low power consumption, low weight and compact portable systems. Vertical interconnect techniques are reviewed in detail. Technical issues such as silicon efficiency, complexity, thermal management, interconnection density, speed, power etc. are critical in the choice of 3-D stacking technology, depending on the target application, and are briefly discussed.

Modeling and analysis of multichip module power supply planes

Abstract: A method that would allow accurate modeling of arbitrarily shaped planes with bypass capacitors has been developed. It is compatible with a SPICE-based modeling method for the rest of the power supply hierarchy and the devices. A modified SPICE is used to accommodate distributed circuits. The distributed circuits are built with microwave analysis software and connected to SPICE by s-parameter files. The modeling process is described and examples of thick and thin-film power supply planes are presented with comparison to measured results. The method is used to explore potential design choices for a large MCM with many simultaneously switching drivers. >

Interconnect and circuit modeling techniques for full-chip power supply noise analysis

Abstract: This paper describes the interconnect and circuit modeling techniques to analyze the on-chip power supply noise for high-performance very large scale integration (VLSI) design. To reduce the complexity of full-chip analysis, a hierarchical power supply distribution model, which consists of a 12/spl times/12 package model, a 50/spl times/50 on-chip power bus model, and a distributed switching circuit model, is developed. This integrated chip-and-package model provides a complete analysis of the resistive IR drop, inductive delta-I noise, and the on-chip Vdd distribution. It also allows designers to identify the hot spots on the chip and optimize design variables to minimize the noise. Analysis results of our benchmark microprocessor chips will be presented to demonstrate the various applications of this methodology.

Analysis of the flow of encapsulant during underfill encapsulation of flip-chips

Abstract: In this paper, the flow of encapsulant during the underfill encapsulation of flip-chips has been studied. Analytical as well as numerical methods have been developed to analyze the flow. For capillary-driven encapsulation (by dispensing), the capillary force at the melt-front has been calculated based on a model for the melt-front shape. A model has also been developed for the analysis of forced-injection encapsulation. The numerical analysis uses a finite-element method based on a generalized Hele-Shaw method for solving the flow field. Experiments have been performed to investigate the flow behavior using actual chips and encapsulants. Short-shot runs have been performed to observe the melt-front advancement at different flow times. In addition, measurements have been made of the material properties of the encapsulant, namely its viscosity, curing kinetics and surface-tension coefficient. The experimental and simulation results have been compared in terms of the flow-front shapes and times at different fill fractions. Such comparisons indicate that the model developed in this study is adequate to approximately simulate the flow during encapsulation of flip chips.

Effect of intermetallic compounds on the thermal fatigue of surface mount solder joints

Abstract: The effect of Cu-Sn intermetallic compounds (IMC) on the fatigue failure of solder joints during thermal cycling has been studied. The samples consist of components [leadless ceramic chip carrier (LCCC)] soldered onto FR-4 printed circuit board (PCB), and are prepared by conventional reflow soldering using a 63Sn-37Pb solder paste. The specimens are subjected to thermal cycling between -35/spl deg/C and 125/spl deg/C with a frequency of two cycles per hour until failure. The results indicate that the fatigue lifetime of the solder joints depends on the thickness of IMC's layer between Cu-pad and bulk solder, and the relation of the lifetime to the thickness can be described as a monotonically decreasing curve. The lifetime is very sensitive to the thickness of the IMC when the thickness is less than 1.4 /spl mu/m. During thermal cycling the thickness of the IMC layer increases and then the interface between IMC and solder becomes gradually flatter. The results of X-ray diffraction and scanning electron microscope (SEM) analysis show that cracks propagate along the interface between the IMC layer and the solder joint. The Cu/sub 3/Sn (/spl epsiv/-phase) is also found to form between the Cu-pad and /spl eta/-phase during thermal cycling. On the basis of the above results, the thick and flattened IMC layer is shown to responsible for the fatigue failure of solder joint during thermal cycling. The results of this paper can be used to optimize the reflow soldering process for the fabrication of robust solder joints.