Showing papers in "IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B in 1998"

A review of 3-D packaging technology

Abstract: This paper reviews the state-of-the-art in three-dimensional (3-D) packaging technology for very large scale integration (VLSI). A number of bare dice and multichip module (MCM) stacking technologies are emerging to meet the ever increasing demands for low power consumption, low weight and compact portable systems. Vertical interconnect techniques are reviewed in detail. Technical issues such as silicon efficiency, complexity, thermal management, interconnection density, speed, power etc. are critical in the choice of 3-D stacking technology, depending on the target application, and are briefly discussed.

Interconnect and circuit modeling techniques for full-chip power supply noise analysis

Abstract: This paper describes the interconnect and circuit modeling techniques to analyze the on-chip power supply noise for high-performance very large scale integration (VLSI) design. To reduce the complexity of full-chip analysis, a hierarchical power supply distribution model, which consists of a 12/spl times/12 package model, a 50/spl times/50 on-chip power bus model, and a distributed switching circuit model, is developed. This integrated chip-and-package model provides a complete analysis of the resistive IR drop, inductive delta-I noise, and the on-chip Vdd distribution. It also allows designers to identify the hot spots on the chip and optimize design variables to minimize the noise. Analysis results of our benchmark microprocessor chips will be presented to demonstrate the various applications of this methodology.

Characterization of thin film microstrip lines on polyimide

Abstract: This paper presents an in depth characterization of thin film microstrip (TFMS) lines fabricated on Dupont PI-2611 polyimide. Measured attenuation and effective dielectric constant is presented for TFMS lines with thicknesses from 2.45-7.4 /spl mu/m and line widths from 5-34.4 /spl mu/m over the frequency range of 1-110 GHz. The attenuation is separated into conductor and dielectric losses to determine the loss tangent of Dupont PI-2611 polyimide over the microwave frequency range. In addition, the measured characteristics are compared to closed form equations for /spl alpha/ and /spl epsiv//sub eff/ from the literature. Based on the comparisons, recommendations for the best closed form design equations for TFMS are made.

Efficient transient simulation of high-speed interconnects characterized by sampled data

Abstract: In this paper, we present an algorithm for efficient simulation of high-speed interconnects characterized by sampled data. The method constructs pole-zero models of arbitrary interconnects using robust rational approximations of the measured or simulated scattering parameters. In order to obtain accurate interpolations of the data over a wide frequency range, a set of powerful techniques is applied to deal with the resulting ill-conditioned Vandermonde-like approximation matrices. By utilizing the analytic properties of the scattering parameters, the algorithm efficiently generates multiport pole-residue models. The models are combined with the lumped/distributed components for direct time- or frequency-domain simulations. The method can easily be implemented into conventional simulators such as simulation program with integrated circuit emphasis (SPICE) and advanced statistical analysis program (ASTAP) or reduced-order modeling techniques such as asymptotic waveform evaluation (AWE), complex frequency hopping (CFH), and Padd approximation via Lancros Process (PVL) for transient simulation of high-speed interconnect networks. Examples of linear and nonlinear networks are given to demonstrate the validity and accuracy of the method.

Modeling, simulation, and measurement of mid-frequency simultaneous switching noise in computer systems

Abstract: Complementary metal-oxide-semiconductor (CMOS) microprocessors operating in the hundreds of megahertz create significant current deltas due to the variation in switching activity front clock cycle to clock cycle. In addition to the high-frequency voltage variations more commonly discussed, a lower frequency noise component is also produced that lasts from 50-200 ns which we refer to as mid-frequency noise. In this paper, we discuss the design of IBM's CMOS S/390 computer for control of mid-frequency noise. This machine has a 10-way multiprocessor on a 127 mm by 127 mm multichip module (MCM) on a FR4 board. The chips on the MCM cause a current step of tens of Amps in a few cycles that can be sustained for many cycles. The power distribution and decoupling capacitors must supply that current without disturbing the voltage level at the circuits. The design of the system power distribution and modeling and verification of mid-frequency noise in this system is presented.

Microfluidic MEMS for semiconductor processing

Abstract: The advent of MEMS (microelectromechanical systems) will enable dramatic changes in semiconductor processing. MEMS-based devices offer opportunities to achieve higher performance and functionality, at lower cost, with decreased size and increased reliability. In this work, we describe the achievement of several important devices for use in the semiconductor equipment industry. They include a low-flow mass flow controller, a high-precision pressure regulator, and an integrated gas panel. Compared to current technology, the devices are ultra-small in size, thus minimizing dead volumes and gas contact surface areas. With wettable surfaces comprised of ceramic and silicon (or, silicon coated with Si/sub 3/N/sub 4/ or SiC), they are resistant to corrosion, and generate virtually no particles. The devices are created from modular components. The science and technology of these components will be detailed. The modules examined are: normally-open proportional valves; normally-closed, low leak-rate shut-off valves; critical orifices (to extract information of flow rate); flow models (to extract flow rate from pressure and temperature information); silicon-based pressure sensors; and, the precision ceramic-based packages which integrate these modules into useful devices for semiconductor processing. The work finishes with a detailed description of the low-flow mass flow controller.

Review and summary of a silicon micromachined gas chromatography system

Abstract: A miniature gas chromatography (GC) system has been designed and fabricated using silicon micromachining and integrated circuit (IC) processing techniques. The silicon micromachined gas chromatography system (SMGCS) is composed of a miniature sample injector that incorporates a 10 /spl mu/I sample loop; a 0.9-m long, rectangular-shaped (300 /spl mu/m width and 10 /spl mu/m height) capillary column coated with a 0,2-/spl mu/m thick copper phthalocyanine (CuPc) stationary-phase; and a dual-detector scheme based upon a CuPc-coated chemiresistor and a commercially available, 125-/spl mu/m diameter thermal conductivity detector (TCD) bead. Silicon micromachining was employed to fabricate the interface between the sample injector and the GC column, the column itself, and the dual-detector cavity. A novel IC thin-film processing technique was developed to sublime the CuPc stationary-phase coating on the column walls that were micromachined in the host silicon wafer substrate and Pyrex cover plate, which were then electrostatically bonded together. The SMGCS can separate binary gas mixtures composed of parts-per-million (ppm) concentrations of ammonia (NH/sub 3/) and nitrogen dioxide (NO/sub 2/) when isothermally operated (55-80/spl deg/C). With a helium carrier gas and nitrogen diluent, a 10 /spl mu/I sample volume containing ammonia and nitrogen dioxide injected at 40 psi (2.8 /spl times/105 Pa) ran be separated in less than 30 min.

Automatic generation of accurate circuit models of 3-D interconnect

Abstract: In order to optimize high-speed systems, designers need tools that automatically generate reduced order SPICE compatible models from geometric descriptions of interconnect and packaging. In this paper, we consider structures small compared to a wavelength, and use a discretized integral formulation combined with an Arnoldi-based model-order reduction strategy to compute efficiently accurate reduced-order models from three-dimensional (3-D) structures. Several issues are addressed including: (1) formulation to insure passivity in the reduced-order models; (2) efficient reduction using preconditioned inner-loop iterative methods; (3) expansion about multiple s-domain points. Results are presented on several industrial examples to demonstrate the capabilities and speed of these new methods.

Characterization of embedded passives using macromodels in LTCC technology

Abstract: This paper discusses the frequency and time domain response of embedded passive components in a multilayered structure fabricated using low temperature co-fired ceramic (LTCC) technology. A rational polynomial approximation that combines the accuracy of EM solvers with interpolation methods has been used to capture the frequency dependent losses and parasitics of embedded passives in a macro-model. This method allows for a significant speed-up in computation time while using commercial EM solvers. The macromodel with suitable modification has been used to compute the time domain response in SPICE for typical embedded passive structures. Simulation results show good correlation with time domain reflectometry/time-domain-transmission (TDR/TDT) measurements. The behavior of embedded passives in the high frequency operation of transmission lines and voltage divider networks has also been discussed.

Investigation of interfacial fracture behavior of a flip-chip package under a constant concentrated load

Abstract: In this paper, the interfacial fracture behavior of a flip-chip package subjected to a constant concentrated line load was investigated using a unique six-axis submicron tester coupled with a high density laser moire interferometry. The real-scale three-point bending flip-chip specimen, capable of measuring the crack growth rate (along the interface) and the interfacial fracture toughness was developed. The results show that the crack propagation along the interface of the passivated silicon chip/underfill under a constant concentrated load can be categorized into three stages occurring in the order mentioned with obvious transition points between them: (1) stable crack propagation stage; (2) unstable crack propagation stage; (3) quasicrack arrest stage. The moire interferometry technique was used to monitor and measure the crack length during the test. The crack growth rate along the interface of the passivated silicon chip/underfill was calculated in terms of the load line deflection versus time curve obtained from the test. In addition, the relationship between the crack length and the load line deflection was calibrated by using finite element analysis. The near tip displacement fields of the flip-chip package was also determined by the same method. The energy release rate was computed by using these near tip displacement variables through an analytical expression derived by authors. The interfacial fracture toughness G/sub c/ was determined by calculating the energy release rate corresponding to the crack length at the quasicrack arrest stage measured in the test. The underfill/chip passivation fracture toughness G/sub c/ and the phase angle /spl phi/ for the flip-chip package used in our experiments are about 35 J/m/sup 2/ and -65/spl deg/, respectively.

Effective material properties and thermal stress analysis of epoxy molding compound in electronic packaging

Abstract: In this study, the coefficient of thermal expansion (CTE) and the elastic modulus of epoxy molding compound (EMC) are measured using fabricated specimens and then the measured values are compared with the predicted values by theoretical equations (such as dilute suspension method, self consistent method, Hashin-Shtrikman's bounds, Shapery's bounds and others). The measured values are distributed within the upper and lower bounds of predicted values. The measured elastic modulus and the CTE of EMC approach close to the predicted values by self consistent method and upper bound of Shapery's equation respectively. Two-dimensional (2-D) and three-dimensional (3-D) finite element analysis are performed using the measured and analytically predicted values. Finite element method (FEM) analysis indicates that firstly the EMC with eighty weight percentage of filter shows less thermal stress when package is cooling down and relatively high thermal stress when package is heating up. Secondly the stress concentrations at the edge sections about two times higher than the interfaces and at the vertex parts about 1.4 times higher than the edge sections are observed.

Possibilities and limitations of I/sub DDQ/ testing in submicron CMOS

Abstract: I/sub DDQ/ testing is a well accepted testing approach based on the observation of the quiescent current consumption. Its growing industrial implementation is based on the possibility of detecting defects which escape other more traditional testing methods. However, its application costs are higher and its effectiveness in deep submicron technologies may decrease if the current trend of leakage increase is not stopped by creative innovation.

Ultra low loss millimeter wave multichip module interconnects

Abstract: We present the design and electrical characterization of a multilayer organic based multichip module (MCM) for use at W-band (75-110 GHz). The ultra-low loss microstrip transmission line on Kapton E(R) (a trademark of DuPont) thin films and benzocyclobutene (BCB) adhesives is reported at W-band. An electrical model for a vertically stacked via interconnect to an integrated circuit (IC) is experimentally developed. This interconnect exhibits very low parasitics and preserves excellent matched conditions for devices and circuits in a module. The electrical performance of the vertically stacked via offers superior performance relative to ribbon and wire bond results reported in the literature at millimeter wave frequencies. We conclude that this technology is capable of realizing compact modules at millimeter wave frequencies.

Solder-jetted eutectic PbSn bumps for flip-chip

Abstract: The commonly used deposition technology for solder bumps (evaporation or electroplating) requires thin-film processing. The compatibility of the solder-wettable metallizations does not allow the use of the same production equipment as installed in the wafer-fabrication facility. In this study, a maskless bump process is described, Here, solder droplets are ejected from a capillary and impinge on wettable bond-pad metallizations of electroless-deposited Ni/P-Au. Droplets impinging on a rough surface layer often bounce away. It is shown that this roughness layer is mainly determined by the Zn nucleation on the bondpad metallizations. Nucleation conditions are optimized to deposit only small particles of the same size. The volume of the droplets depends on the product of pulse amplitude and pulse length. Degradation of the interconnection between the piezoelectric actuator and the glass capillary requires a larger pulse amplitude for stable jetting behavior. In addition, it is found that every first droplet on a new position is larger than all other droplets ejected directly thereafter. The diameter distribution of the latter are within the requirements for the final bump. The quality of the solder-jetted bump is studied by several reliability tests after flip-chip assembly on printed wiring boards (PWBs). In combination with underfill, the reliability of solder-jetted bumps are comparable with electroplated bumps.

Thermomechanical analysis in electronic packaging with unified constitutive model for materials and joints

Abstract: A unified constitutive modeling approach based on the disturbed state concept (DSC) provides improved characterization of thermomechanical response of joining (solders), ceramics and printed wire board (PWB) materials in electronic packaging. Various versions in the DSC approach are calibrated and validated with respect to laboratory test data, and are implemented in a nonlinear finite element (FE) procedure. The hierarchical nature of this procedure permits the user to choose a constitutive model, simple (elastic) to sophisticated (elastovisco-plastic with disturbance), depending upon the material and need. The FE is used to analyze thermomechanical behavior of two typical problems: (1) leadless ceramic chip carrier (LCCC) package; (2) solder ball connect (SBC) package. The FE results under cyclic thermal loading are compared with experimental data for the two packages, and with a previous FE analysis for the SBC package. In conjunction with the idea of critical disturbance at which thermal fatigue failure can occur, the analyzes allow identification of cycles to failure, N/sub f/, and evaluation of reliability of the package. In the case of the SBC package, the analysis permits an evaluation of ball spacing on the thermomechanical behavior. The DSC approach can provide an integrated and improved procedure compared to available models for elastic, plastic, creep strains, and microcracking leading to degradation of strength and fatigue failure for a wide range of problems in electronic packaging under thermomechanical loading.

A technique for fast calculation of capacitance matrices of interconnect structures

Abstract: A finite difference (FD) method for rapid and accurate evaluation of capacitance matrices of interconnect configurations is described in this paper. The method utilizes newly-developed perfectly matching layer (PML) technique for mesh truncation, specially adapted to the static case in conjunction with a mixed boundary condition, referred to as the /spl alpha/-technique. The application of proposed approach to the modeling of complex structures, comprising multiple metal layers, cross-overs, vias, and bends embedded in a layered dielectric medium, is illustrated in the paper. The paper also shows the usefulness of the technique to the problem of mapping within the interconnect. A novel approach for efficient truncation of a class of large interconnects called the wraparound scheme, is introduced in the paper. Several numerical examples that illustrate the efficiency and flexibility of the approaches, described above, are included in the paper.

Linear fracture mechanics analysis on growth of interfacial delamination in LSI plastic packages under temperature cyclic loading

Abstract: A study is made of the tendency of growth of delamination between dissimilar materials occurring in large scale integration (LSI) plastic packages under temperature cyclic loading. Two groups of delamination growth processes are considered; one along the interface between the top surface of the die pad and the die-bonding layer, and the other along the interface between the bottom surface of the die pad and the encapsulant resin. In each group several different initial patterns of delaminations are assumed. Stress intensity factors and their mode ratios at the tips of growing delaminations are calculated by combining a thermoelastic finite element method for nonlinear contact problems and a linear interface fracture mechanics approach. The effects of geometries of delamination and leadframe materials on the tendency of delamination growth are clarified.

Programmable neural logic

Abstract: Circuits of threshold elements (Boolean input, Boolean output neurons) have been shown to be surprisingly powerful. Useful functions such as XOR, ADD and MULTIPLY can be implemented by such circuits more efficiently than by traditional AND/OR circuits. In view of that, we have designed and built a programmable threshold element. The weights are stored on polysilicon floating gates, providing long-term retention without refresh. The weight value is increased using tunneling and decreased via hot electron injection. A weight is stored on a single transistor allowing the development of dense arrays of threshold elements. A 16-input programmable neuron was fabricated in the standard 2 /spl mu/m double-poly, analog process available from MOSIS. We also designed and fabricated the multiple threshold element. It presents the advantage of reducing the area of the layout from O(n/sup 2/) to O(n), (n being the number of variables) for a broad class of Boolean functions, in particular symmetric Boolean functions such as PARITY. A long term goal of this research is to incorporate programmable single/multiple threshold elements, as building blocks in field programmable gate arrays.

Laser formed metallic connections

Abstract: Solid metallic connections have been successfully formed between two standard levels of metallization using a focused infrared (IR) laser. This new process of laser formed connections has been used to link continuous chains and with resistances of less than 0.8 /spl Omega/ per connection. A commercial laser repair system used extensively by the memory industry was employed to perform approximately 50000 individual links without failure. The electromigration resistance is comparable to standard metal interconnect. This technology has the potential to replace laser fuse cutting techniques to implement repair schemes and it can be used to program wiring in multichip module-deposited (MCM-D) or wafer scale integration applications implemented on silicon substrates. Furthermore, because it is an additive process, it lends itself to redundancy for higher yield and reliability.

Aging effects on shear fatigue life and shear strength of soldered thick film joints

Abstract: The effects of tin diffusion, silver and palladium dispersion, and intermetallic compound growth on the shear fatigue of solder joints between thick film mixed bonded conductor Pd-Ag and solder 62Sn-36Pb-2Ag are investigated. Microstructural analysis reveals that the intermetallic compounds (IMC's) Pd/sub 3/Sn/sub 2/, Pd/sub 3/Sn, Pd/sub 2/Sn, Pd/sub 3/Sn/sub 2/, PdSn, PdSn/sub 2/, PdSn/sub 4/, Ag/sub 5/Sn, Ag/sub 3/Sn, PbPd/sub 3/, and Pb/sub 3/Pd/sub 5/ are formed after aging. X-ray dot maps demonstrate that the longer the aging time, the more serious the silver and palladium dispersion into the solder and the tin diffusion into the conductor. It is observed that the tin diffuses to the interface of the substrate/conductor after 120 h aging. Shear strength tests with different strain rate show that the adhesion strength decreases with prolongation of aging time. Shear cycling tests indicate that the fatigue lifetime of the solder joints depends on the diffusion depth of the silver and palladium, especially the tin diffusion into the thick film conductor. The above results mean that the more serious is the tin and silver interdiffusion, and the more IMC's are formed in the solder joint (effects which are the result of prolonged storage at high temperature or of long term operation in real SMT assemblies), the more sensitive is the solder joint to stress. Eventually fatigue failure of the joint may result. It is argued that volume change and increased brittleness caused by the intermetallic formation, and volume swelling of the conductor layer due to tin diffusion, are major factors in the decrease of fatigue lifetime and degradation of the shear strength of the solder joints.

Characterization of a planar spiral inductor on a composite-resin low-impedance substrate and its application to microwave circuits

Abstract: The Q-factors of planar spiral inductors built on a polyimide-SiO/sub 2/-Si substrate are characterized as a function of the polyimide thickness. We found that inductor quality as high as that on a GaAs-microwave and millimeter-wave integrated circuit (MMIC) requires a polyimide thickness of over 100 /spl mu/m, resulting in a Q-factor of over 17. The applicability of a low-impedance substrate was confirmed through the investigation of a novel RF-MCM in a face-up-type structure for cellular phone systems using a composite epoxy resin-metallic substrate. A fabricated power amplifier module exhibited 28.5-dBm output power and 16% power efficiency at 1.75 GHz.

Composite and multilayered TaO/sub x/-TiO/sub y/ high dielectric constant thin films

Abstract: A novel low temperature deposition process using reactive pulsed dc magnetron sputtering has been developed to deposit thin dielectric films composed of either a composite or alternating layers of tantalum oxide and titanium oxide. Capacitors fabricated from these dielectric materials have been found to exhibit exceptional electrical properties. For the composite material, one film containing 22% TiO/sub y/ had a high dielectric constant of 38, a leakage current density of 10/sup -6/ A/cm/sup 2/ at 0.5 MV/cm, and a relatively high breakdown field strength of 2.3 MV/cm. By a slight modification of the deposition conditions, alternating layers of tantalum oxide and titanium oxide were deposited to form a high dielectric constant material. The electric at properties of these films were also exceptional: a dielectric constant of 44, a leakage current density of 3.4/spl middot/10/sup -8/ A/cm/sup 2/ at 0.5 MV/cm, and a breakdown field strength of 2.3 MV/cm. These films have potential applications in memory and advanced electronics packaging.

Electrical design of a cost-effective thermal enhanced plastic ball grid array package-NuBGA

Abstract: An electrically and thermally optimized plastic ball grid array (PBGA) package, called new and useful ball grid array (NuBGA) is presented. NuBGA is a cavity down package with a metal heat spreader covering the entire back-side of the chip. The heat spreader is laminated with a single-core double-sided organic substrate. Super electrical performance is achieved by using the split-wrap-around (SWA) or split-via-connection (SVC) design concepts. All traces on the core substrate are designed into /spl mu/-stripline and co-planar stripline structures. In this paper, the focus is on (1) the unique design concepts; (2) the electrical measurement; (3) the electrical analysis; (4) the electrical performance comparison with other standard packages.

Design methodology for chip-on-chip applications

Abstract: Chip-on-chip is a viable alternative solution for some applications requiring logic and memory integration. However, one of the impediments to this technology is lack of design infrastructure. Conventional multichip design methodologies which are extensions of standard board designs are not well-suited to chip-on-chip designs. To address this issue, we have implemented a chip-on-chip design methodology that incorporates both logic and memory design database and utilizes an auto-router to minimize routing layers. It emulates a two-layer routing system by using a single redistribution metal layer on each chip and solder bumps as vias. In this paper, we describe several chip-on-chip modules designed using this methodology and discuss the method's limitations.

Accurate, rapid, high frequency empirically based predictive modeling of arbitrary geometry planar resistive passive devices

Abstract: A novel technique is presented for the high speed, accurate, predictive modeling of arbitrary geometry integrated resistor structures manufactured in a variety of technologies, including those of both multichip modules (MCM's) and integrated circuits (IC's). The technique is based upon generating test structures in the process of interest, performing measurements, and extracting the behavior of a few key well identified building blocks. These building blocks can then be used for generating circuit models of other any structure created by valid combinations of those building blocks, which can then be simulated in a standard circuit simulator to predict behavior. The procedure has been experimentally verified, and shows good agreement with actual measurements up to 5-10 GHz. In addition, the model validity has been tested in several circuits by comparing the model predicted results against results obtained using the HP MDS simulator which uses measured parameters directly, with very good results. Since lumped element circuits are generated by this method, structure prediction speed is determined by circuit size and simulator small signal analysis time. The method is versatile and is well suited for circuit design applications.

Interface reaction between Ag-Pd conductor and Pd-Sn solder

Abstract: The intermetallic compound layer between Pb-Sn solder and Ag-Pd conductor after aging at 150/spl deg/C has been studied; elemental and phase distributions of this layer has been probed using SEM, EPMA and EDX. The investigation of the microstructure of the layer with EPMA liner analysis reveals segregation of Ag-rich and Pd-rich phases. Quantitative EDX analysis results show that the Ag-rich phase contains Ag and Sn with the Ag/Sn ratio around 3/1, and the Pd-rich phase Pd and Sn with the Pd/Sn ratio around 1/4. These phases are confirmed to be the intermetallic compounds Ag/sub 3/Sn and PdSn/sub 4/, respectively.

S/390 cost performance considerations for MCM packaging choices

Abstract: In this paper, we develop a cost performance metric for the comparison of MCM structures used for the packaging of the central electronic complex (CEC) of the S/390 systems. The approach is simple and general enough that it can be used to evaluate any first level package structure. The cost component is based on relative costs for the structures examined, while the performance is estimated through closed form formulae and simulation data of actual products. The results of this comparison show that a glass ceramic MCM with polyimide redistribution is the package of choice for bus frequencies larger than 160 MHz. For bus frequencies less than 160 MHz, all alternatives examined are cost performance equivalent and the choice should be based on other criteria that are application specific.

An 8-Bit 2-gigasample/second A/D converter multichip module for digital receiver demonstration on Navy AN/APS-145 E2-C Airborne Early Warning Aircraft radar

Abstract: This paper will discuss multichip module technology as it is applied to a prototype high performance direct digitizing channelized radar receiver system under development for the Navy's E2-C Airborne Early Warning Aircraft, which encompasses both analog signals at UHF frequencies and multigigahertz digital signals. Critical issues which arise in the design of such a system will be discussed, including thermal management, transmission line design, design of power and ground distribution systems, and analyses of voltage standing wave ratio and simultaneous switching noise. This paper will describe in detail the simulations and analyses which were undertaken during the development of the multichip module containing the analog-to-digital converter and demultiplexer for this system. Finally, test results from measurements of analog-to-digital converter performance at the full operating clock rates of the multichip module will be described, along with lessons learned for the design of subsequent generations of these high performance mixed signal systems.

Dynamic analysis of V transmission lines

Abstract: In this work, a dynamic analysis of the V line is presented. Previous work analyzed the performance of this structure for low frequency applications using quasistatic approximations. Here, we extend the analysis of the V line into the higher frequency range where dispersion becomes significant and where it cannot be predicted by quasistatic methods. We show that the V line provides features and advantages that are not present in the conventional microstrip structures, most notably the appreciable decrease in coupling between adjacent lines in comparison with the conventional microstrip structure. This feature makes the V line well suited for high packaging density applications. The full-wave analysis is carried out using a Yee-cell based finite-difference time-domain (FDTD) method, while enforcing a highly efficient and stable mesh truncation technique. Results are presented for a single and multiconductor structures.

Three-dimensional memory module

Abstract: Demand has recently increased for high packaging density and memory capacity of memory modules for electronic equipment. The new three-dimensional memory module satisfies this demand. This module has almost the same size as single memory packages [thin small outline packages (TSOPs): 17.4/spl times/9.22/spl times/1.2 mm] currently being used, and a package density four times as large. Electrical performance is better than that of TSOP's because the length of the wires is about half that of the TSOP's wires. Moreover, the cost of fabrication of this module is low. This paper reports the module's characteristics and fabrication process. The design concept is that next-generation memory devices will be produced by using current mass-produced memory devices.