Showing papers in "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems in 1983"
TL;DR: Upper and lower bounds for delay that are computationally simple are presented in this paper and can be used to bound the delay, given the signal threshold, and to certify that a circuit is "fast enough," given both the maximum delay and the voltage threshold.
Abstract: In MOS integrated circuits, signals may propagate between stages with fanout. The exact calculation of signal delay through such networks is difficult. However, upper and lower bounds for delay that are computationally simple are presented in this paper. The results can be used 1) to bound the delay, given the signal threshold, or 2) to bound the signal voltage, given a delay time, or 3) certify that a circuit is "fast enough," given both the maximum delay and the voltage threshold.
857 citations
TL;DR: A new approach to automatic wire routing of VLSI chips which is applicable to interconnection problem in uniform structures such as gate arrays, switchboxes, channels and is inherently fast, usually by an order of magnitude faster than the routers based on wave propagation (maze running) technique.
Abstract: We propose a new approach to automatic wire routing of VLSI chips which is applicable to interconnection problem in uniform structures such as gate arrays, switchboxes, channels. Popularity of gate arrays technologies still remains high among VLSI chip manufacturers and, as the scale of integration grows, the interconnection problem becomes increasingly difficult if not intractable. The same is true for problems of switchbox and channel routing, which usually arise in custom designs; the uniformity of wiring substrate unites them with gate array routing problem. Our approach was initially aimed at gate arrays, but it extends naturally to switchboxes and channels. Uniformity of the wiring substrate is the crucial assumption of the method. It assumes that horizontal and vertical wire segments are realized on different wiring layers and vias are introduced each time a wire changes direction. Any "jogs" ("wrong way" wires) are prohibited. Within these limitations our approach is advantageous over the existing wiring methodologies. Our final layout of wires is independent of both net ordering and ordering of pins within the nets. The wire densities we are able to achieve are often higher than those achieved by other routers. Because of the hierarchical nature of our method it is inherently fast, usually by an order of magnitude faster than the routers based on wave propagation (maze running) technique.
287 citations
IBM1
TL;DR: Simulated annealing, a new general-purpose method of multivariate optimization, is applied to global wire routing for both idealized (synthetic) and actual designs of realistic size and complexity.
Abstract: Simulated annealing, a new general-purpose method of multivariate optimization, is applied to global wire routing for both idealized (synthetic) and actual designs of realistic size and complexity. Since the simulated annealing results are better than those obtained by conventional methods we use them as a standard against which to compare several sequential or greedy strategies commonly employed in automatic wiring programs.
257 citations
IBM1
TL;DR: This paper proposes an algorithm which uses a graph-theoretic approach to solve efficiently the compaction problem with mixed constraints.
Abstract: A popular algorithm to compact VLSI symbolic layout is to use a graph algorithm similar to finding the "longest path" in a network The algorithm assumes that the spacing constraints on the mask elements are of the lower bound type However, to enable the user to have close control over the compaction result, a desired symbolic layout system should allow the user to add either the equality or the upper bound constraints on selected pairs of mask elements as well This paper proposes an algorithm which uses a graph-theoretic approach to solve efficiently the compaction problem with mixed constraints
138 citations
TL;DR: The relations model digital logic at the register-transfer (RT) level using algebraic relations, which express timing relationships that must be satisfied by any correct implementation.
Abstract: This paper describes a method for formally modeling digital logic using algebraic relations. The relations model digital logic at the register-transfer (RT) level. An RT-level behaviorial specification is used to develop the relations, which express timing relationships that must be satisfied by any correct implementation. An extension of the model is shown which can be used for synthesis at the RT level. The growth rate and computational properties of the model are discussed, and an example of synthesis is shown.
120 citations
TL;DR: This study suggests that one essentially has to have a good approximation of the region of acceptability in order to achieve significant variance reduction, and that importance sampling is very useful when there are few parameters and the yield is very high or very low.
Abstract: The efficiency of several variance reduction techniques (in particular, importance sampling, stratified sampling, and control variates) are studied with respect to their application in estimating circuit yields. This study suggests that one essentially has to have a good approximation of the region of acceptability in order to achieve significant variance reduction. Further, all the methods considered are based, either explicitly or implicity, on the use of a model. The control variate method appears to be more practical for implementation in a general purpose statistical circuit analysis program. Stratified sampling is the most simple to implement, but yields only very modest reductions in the variance of the yield estimator. Lastly, importance sampling is very useful when there are few parameters and the yield is very high or very low; however, a good practical technique for its implementation, in general, has not been found.
107 citations
TL;DR: This paper describes the topological routing algorithm in detail, based on a circle graph representation of the net intersection information of the routing problem, which selects a maximal set of nets that can be routed without vias.
Abstract: A new approach to the two-dimensional routing utilizing two layers is proposed. It consists of two major steps, topological routing and geometrical mapping. This paper describes the topological routing algorithm in detail. Based on a circle graph representation of the net intersection information of the routing problem, a maximal set of nets that can be routed without vias are selected. The layer assignments for the selected nets are determined by a global analysis so that the total number of vias needed is minimum. The layer assignment problem turns out to be a maximum-cut problem on an edge-weighted graph and we developed a greedy algorithm for it. According to the layer assignments, the detailed topological routes are then generated.
102 citations
TL;DR: A new algorithm to extract resistance values from an integrated circuit artwork description is presented, which first breaks the input polygons into simple pieces, and then finds the resistance through each piece.
Abstract: This paper presents a new algorithm to extract resistance values from an integrated circuit artwork description. Instead of trying to solve for the exact resistance values, heuristics are used to find an approximate solution. The algorithm first breaks the input polygons into simple pieces, and then finds the resistance through each piece. This procedure enables the extraction to be both fast and memory efficient. The heuristics used for splitting the polygons and calculating the pieces' resistance are derived from rules of electrostatics, and yield answers that are within 10 percent of the exact resistance values. The operations needed to break complex polygons into simpler pieces are very similar to other geometric operations used in artwork analysis systems.
85 citations
TL;DR: This paper describes the routing techniques used for a Hughes internally developed high-density silicon-gate bulk CMOS gate array family and gives a systematic breakdown of the routing task into well-defined subtasks to achieve a high degree of order independency in all subtasks.
Abstract: This paper describes the routing techniques used for a Hughes internally developed high-density silicon-gate bulk CMOS gate array family. This layout software can be easily adapted to different array sizes and/or technologies (e.g., bipolar) through a change of parameters. A routing model and hierarchical decomposition schemes are presented to address the routability issue. More specifically, this paper focuses on the formulation and analysis of global routing and vertical assignment problems and gives a systematic breakdown of the routing task into well-defined subtasks. Instead of performing sequential routing, techniques and formulations are introduced to achieve a high degree of order independency in all subtasks. In routing subtasks where iterations are required, independent selection and interconnection are performed to avoid order dependency in typical routing problems. Implementation results are provided to indicate the efficiency of the system.
85 citations
TL;DR: The architecture of a logic simulation machine employing distributed and parallel processing is described, which can accommodate different levels of modeling ranging from simple gates to complex functions, and support timing analysis.
Abstract: Special-purpose CAD hardware is increasingly being considered as a means to meet the challenge posed to conventional (software-based) CAD tools by the growing complexity of VLSI circuits. In this paper we describe the architecture of a logic simulation machine employing distributed and parallel processing. Our architecture can accommodate different levels of modeling ranging from simple gates to complex functions, and support timing analysis. We estimate that simulation implemented by the proposed special-purpose hardware will be between 10 and 60 times faster than currently used software algorithms running on general-purpose computers. With the available technology, a throughput of 1 000 000 gate evaluations/sec can be achieved.
65 citations
TL;DR: This paper describes a method for connecting an M OSFET 2-D device simulator to a circuit simulator via a 3-D table look-up MOSFET model via a proposed monotonic piecewise cubic interpolation technique.
Abstract: This paper describes a method for connecting an MOSFET 2-D device simulator to a circuit simulator via a 3-D table look-up MOSFET model. The computational cost of the device simulator is drastically reduced by a proposed monotonic piecewise cubic interpolation technique. With this technique, the device simulator needs to calculate only 100 ~ 200 points to make up an accurate 3-D table look-up MOSFET model. The computational time necessary for the interpolation is only about one third of the time for calculating one current point by the device simulator.
TL;DR: A new computer program is presented, PLEASURE, which implements several algorithms for multiple and/or constrained PLA folding and a constrained optimization problem to achieve minimal silicon area occupation with constrained positions of electrical inputs and outputs is defined.
Abstract: Programmable logic arrays are important building blocks of VLSI circuits and systems. We address the problem of optimizing the silicon area and the performances of large logic arrays. In particular, we describe a general method for compacting a logic array defined as multiple row and column folding and we address the problem of interconnecting a PLA to the outside circuitry. We define a constrained optimization problem to achieve minimal silicon area occupation with constrained positions of electrical inputs and outputs. We present a new computer program, PLEASURE, which implements several algorithms for multiple and/or constrained PLA folding.
TL;DR: An automatic routing scheme intended dedicatedly for general cell LSI is described, which is constructed of a number of algorithms such as for net ordering, global routing, and detailed routing.
Abstract: An automatic routing scheme intended dedicatedly for general cell LSI is described, which is constructed of a number of algorithms such as for net ordering, global routing, and detailed routing. This scheme is distinctive in that channel constraint loops are broken automatically at the stage of global routing, and a grid-free routing scheme is employed at the state of detailed routing. The routing program based on this scheme has been incorporated into a design system for LSI which is at work in practice. A part of implementation results are also shown.
TL;DR: A program which implements the proposed algorithms for routing nets inside an arbitrarily shaped region has been written and tested and the results from this program are shown as examples.
Abstract: In this paper we present a discussion of planarity testing and detailed single-layer routing. A program which implements the proposed algorithms for routing nets inside an arbitrarily shaped region has been written and tested. The results from this program are shown as examples.
TL;DR: The new timing verification method using the delay model is evaluated with respect to delay-time accuracy and execusion time in a logic LSI and circuit simulator accuracy is obtained in the short computer run time of a logic simulator.
Abstract: The propagation delay time of the ED MOS logic gate is precisely analyzed considering input waveform and loading conditions. According to theoretical consideration and circuit analysis, the rise mode delay time tpLH is approximated as a function of the output capacitance of only the gate concerned. The fall mode delay time t.pHL is determined by the input capacitance and output capacitance of the gate concerned. These results allow the easy implementation of the delay model into a logic simulator. A precise delay simulation is attained by considering the delay components, corresponding to each input node, at the output side of the logic element. The propagation delay times of the transmission gate are precisely analyzed. The operations of the transmission gate are divided into two modes; synchronous mode and asynchronous mode. Corresponding to each mode, the transmission gate, the preceding gate, and the succeeding gate have two kinds of delay times. To simulate delay times of each gate precisely, models which treat these three logic elements as one primitive element in a logic simulator have been proposed. The new timing verification method using the delay model is evaluated with respect to delay-time accuracy and execusion time in a logic LSI. Through this method, circuit simulator accuracy is obtained in the short computer run time of a logic simulator.
TL;DR: It is shown that a two-dimensional processor array structure can be applied to the placement problem, resulting in a substantial reduction of the processing time.
Abstract: A parallel processing algorithm for logic module placement is presented. Conventionally, such placement problems have been solved on a single processor in a sequential manner. In this paper, it is shown that a two-dimensional processor array structure can be applied to the placement problem, resulting in a substantial reduction of the processing time. This parallel processing algorithm is based on the concept that the adjacent pairwise exchange method could be expanded to the parallel processing case. By using simulation programs, it is shown that the placement results obtained by the parallel processing algorithm are a little better than those obtained by the sequential algorithm. In addition, the theoretical estimations in respect to the processing cycle iterations correspond well with the simulation results.
TL;DR: For a given placement of blocks and global routing of nets, a new formulation and its solution of the problem of determining the order of channels for the complete channel routing are presented.
Abstract: For a given placement of blocks and global routing of nets, a new formulation and its solution of the problem of determining the order of channels for the complete channel routing are presented. If the order of channels satisfying the condition exists, it is called the safe order since following it, each channel can be routed the wiring requirement without any prediction of necessary width. Thus the compaction of the routing area can be made utmost each time. The idea is based on the general feature of channel routers not on any particular one. Related subjects such as the simultaneously routable channels, generalization of the safe order, switch box routing, and the placement with nonrectangular blocks are discussed.
TL;DR: The intention of this paper is to demonstrate that layout programs of today have not yet become perfect, and a lot of effort in software development is necessary in order that automatic layouts can compared with manual designs.
Abstract: Some of the essentials for layout of complex VLSI circuits are hierarchical design based on macrocells of arbitrary size and shape, power nets with local varying width, signal nets with individual width and very compacted layouts which still have to guarantee all geometrical design rules. This paper is devoted to the problem of automatic routing with real geometries. VWROUT, a Variable Width Routing System is presented. This includes planar power net routing with variable width on a single layer, loose and final routing of signal nets with variable width on two layers (H-V routing), and layout compaction with design-rule verification. Though automatic routing systems have been developed successfully, the intention of this paper is to demonstrate that layout programs of today have not yet become perfect. A lot of effort in software development is necessary in order that automatic layouts can compared with manual designs.
TL;DR: The algorithm is compatible with classical time wheel mechanisms for logic simulation and therefore allows for assignable delay modeling also at the switch level and is shown to be 0(n) and proven to converge to a unique solution.
Abstract: In this paper a new algorithm for switch level simulation is presented. The algorithm is compatible with classical time wheel mechanisms for logic simulation and therefore allows for assignable delay modeling also at the switch level. The key to this algorithm is a local relaxation method which takes care of localized bilateral effects. The algorithm is shown to be 0(n) and proven to converge to a unique solution.
TL;DR: This paper describes a procedure for partitioning logic to minimize the number of gate arrays required to implement the logic and presents results using three different logic circuits ranging in size from 14 000 gates to 26 000 gates.
Abstract: This paper describes a procedure for partitioning logic to minimize the number of gate arrays required to implement the logic. The procedure consists of three algorithms to perform initial, iterative, and interactive logic partitioning. Results are presented using three different logic circuits ranging in size from 14 000 gates to 26 000 gates.
TL;DR: A new VLSI checking program, LIVES (Logic Interconnection VErification System), has been developed, which verifies the geometrical layout data to determine whether or not it correctly reflects the original logic level description.
Abstract: A new VLSI checking program, LIVES (Logic Interconnection VErification System), has been developed. LIVES verifies the geometrical layout data to determine whether or not it correctly reflects the original logic level description. An excellent LIVES feature, which no other programs have possessed yet, is that it can perform the check even when there are no identification marks on each logic gate in layout level description data. This feature is realized by employing new algorithms based on graph theory. In the verification procedure, LIVES Adopts graph isomorphism, which uses the new partitioning methods for vertices, especially tailored for the logic diagram. In the error detection procedure, a graph is divided into subgraphs, based on a new concept, "route-subgraph," and tests for graph isomorphism between subgraphs are performed. These algorithms enable precise and rapid search for any error points in the VLSI design. These new algorithms have been implemented and examined for practical feasibility. Experimental results have ensured that this program can detect errors in the VLSI layout patterns very quickly and precisely. LIVES will be a highly efficient tool in VLSI logic design by using it systematically combined with other CAD programs.
TL;DR: The gate matrix layout of random control logic in BELLMAC-32A with top-down hierarchical design methodology provided adaptability to evolving logic design with short turnaround time, high packing density competitive with hand layout, compatibility with computer-aided layout and verification tools, and technology updatability.
Abstract: BELLMAC-32A is a single-chip fully 32-bit high-end microprocessor designed in 2.5-?m twin-tub CMOS technology. This paper describes the gate matrix layout of random control logic in BELLMAC-32A with top-down hierarchical design methodology. The gate matrix layout provided (1) parallel team layout efforts, (2) adaptability to evolving logic design with short turnaround time, (3) high packing density competitive with hand layout, (4) compatibility with computer-aided layout and verification tools, (5) capability to fine-tune circuits, and (6) technology updatability. It took 6.5 engineer-years to complete the layout of random control logic with 7000 transistors although the logic design was continuously evolving during the layout period. The average packing density of gate matrix layout was 1500 ?m2 per transistor in random logic and 840 ?m2 per transistor in data path. BELLMAC-32A had more-than-three times performance improvement over its 3.5 ?m technology prototype chip BELLMAC-32, in which random control logic was implemented with polycells.
TL;DR: A new, computationally efficient method for the numerical evaluation of the equilibrium capacitance of one-dimensional MOS structures is presented.
Abstract: A new, computationally efficient method for the numerical evaluation of the equilibrium capacitance of one-dimensional MOS structures is presented. Capacitance-voltage (C-V) characteristics for arbitary impurity profiles and interface state distributions can be calculated for temperatures ranging from 50 K to 350 K. Examples of simulated C-V characteristics demonstrate the capability of the computer program MOSCAP using these techniques.
TL;DR: A heuristic algorithm is proposed for the layering problem of multilayer PWB wiring, associated with single-row routing, reduced to a problem of the interval graph by relaxing some restrictions in the original problem.
Abstract: This paper deals with the layering problem of multilayer PWB wiring, associated with single-row routing. The problem to be considered is restricted to the special case of street capacities up to two in each layer, and it is reduced to a problem of the interval graph by relaxing some restrictions in the original problem. Then, a heuristic algorithm is proposed for this problem.
TL;DR: A main objective of the router is not only to minimize the maximum of the local routing densities but also to distribute all the wiring requirements over channels evenly, in order to attain 100-percent interconnections within a limited area.
Abstract: A global router for gate array LSI's is described, which is intended to perform an interaction between placement and routing such that the features of one may be incorporated into those of another. This router is to generate for each net an interconnection pattern of channel segments in such a unified way of taking all interrelated interconnection requirements into account at once. A main objective of the router is not only to minimize the maximum of the local routing densities but also to distribute all the wiring requirements over channels evenly, in order to attain 100-percent interconnections within a limited area. An implementation result of the router is also shown.
TL;DR: This paper describes the definition and implementation of a multilevel representation which includes both behavioral and structural information and allows the system level designers to be in a closed loop of design aids with the technology level designers.
Abstract: This paper describes the definition and implementation of a multilevel representation which includes both behavioral and structural information. Information for the representation is generated by the CMU-DA synthesis system. A timing abstraction aid which extracts logic level timing information from a detailed implementation and makes it available for the ISPS behavioral simulator is discussed. Such a multilevel representation and design aid allows the system level designers to be in a closed loop of design aids with the technology level designers.
TL;DR: Symmetric displacement techniques for the timing analysis of VLSI circuits are introduced and their numerical properties such as stability and accuracy are investigated on different classes of circuits.
Abstract: Symmetric displacement techniques for the timing analysis of VLSI circuits are introduced. Their numerical properties such as stability and accuracy are investigated on different classes of circuits.
TL;DR: A rerouting scheme is described, which is incorporated into an existing automatic routing system for single-layer printed wiring boards (PWB's) and hybrid integrated circuits, to strip and reroute portions of the current wire patterns so that incomplete from-to's can be interconnected by means of getting rid of blockages.
Abstract: A rerouting scheme is described, which is incorporated into an existing automatic routing system for single-layer printed wiring boards (PWB's) and hybrid integrated circuits. This scheme is to strip and reroute portions of the current wire patterns so that not only incomplete from-to's can be interconnected by means of getting rid of blockages, but those conductor paths so far determined which form unnecessarily long detours can be improved. Several implementation results are also shown.
TL;DR: The local CAD environment, the motivation for edisim, its user interface and implementation are discussed, and the technique works well for small to medium size cells, but seems less useful on large designs when only a small fraction of the circuit can appear on the screen at once.
Abstract: A new CAD tool has been developed that provides the ability to interact graphically with the simulation of an LSI circuit. The tool is called EDISIM, for EDItor plus SIMulator. Compared with the textual interface provided by most simulators, the graphic interface of edisim is simpler to learn and faster to use for both the novice and the experienced designer. EDISIM displays the layout of a chip on a color screen, and allows the user to set the logical value of a net merely by pointing to any feature on it, such as a diffusion region or a metal connection. Results are also displayed graphically-nets at logic 1 are solid color, those at logic 0 are hollow, and those in the unknown state have an "X" through them. The technique works well for small to medium size cells, but seems less useful on large designs when only a small fraction of the circuit can appear on the screen at once. This paper discusses the local CAD environment, the motivation for edisim, its user interface and implementation.
TL;DR: A new charge based MOS transistor model for capacitances which will conserve transient charges is introduced, required to accurately simulate a certain class of dynamic circuits.
Abstract: A new charge based MOS transistor model for capacitances which will conserve transient charges is introduced. The model is required to accurately simulate a certain class of dynamic circuits. This model features continuous charge formulation in all regions of operation: accumulation, cutoff, and strong inversion. Capacitances are continuous in all regions except on the strong inversion to cutoff border. The channel potential is approximated by novel and weighted functions of the drain and source potentials. A hyperbolic tangent function splits the channel charge in strong inversion between the source and drain. Charge conservation and accuracy of the model are demonstrated with some real examples.