# Showing papers in "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems in 1988"

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TL;DR: A local mobility function, set up in terms of a simple Mattiessen's rule, provides a careful description of MOSFET operation in a wide range of normal (or gate) electric fields.

Abstract: A semiempirical model for carrier mobility in silicon inversion layers is presented. The model, strongly oriented to CAD (computer-aided design) applications, is suitable for two-dimensional numerical simulations of nonplanar devices. A local mobility function, set up in terms of a simple Mattiessen's rule, provides a careful description of MOSFET operation in a wide range of normal (or gate) electric fields, channel impurity concentrations of between 5*10/sup 14/ cm/sup -3/ and 10/sup 17/ cm/sup -3/ for the acceptor density of states and 6*10/sup 14/ cm/sup -3/ and 3*10/sup 17/ cm/sup -3/ for the donor density of states; and temperatures between 200 K and 460 K. Best-fit model parameters are extracted by comparing the calculated drain conductance with a very large set of experimental data points. >

697Â citations

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TL;DR: SOCRATES as discussed by the authors is an automatic test pattern generation system for combinational and scan-based circuits based on the FAN algorithm, improved implication, sensitization, and multiple backtrace procedures.

Abstract: An automatic test pattern generation system, SOCRATES, is presented. SOCRATES includes several novel concepts and techniques that significantly improve and accelerate the automatic test pattern generation process for combinational and scan-based circuits. Based on the FAN algorithm, improved implication, sensitization, and multiple backtrace procedures are described. The application of these techniques leads to a considerable reduction of the number of backtrackings and an earlier recognition of conflicts and redundancies. Several experiments using a set of combinational benchmark circuits demonstrate the efficiency of SOCRATES and its cost-effectiveness, even in a workstation environment. >

517Â citations

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TL;DR: Sehwa can find the minimum-cost design, the highest performance design, and other designs between these two in the design space and executes within minutes, for problems of practical size, on a VAX 11/750.

Abstract: A set of techniques for the synthesis of pipelined data paths is described, and Sehwa, a program that performs such synthesis, is presented. The task includes the generation of data paths from a data-flow graph along with a clocking scheme that overlaps execution of multiple tasks. Some design examples are given. Sehwa can find the minimum-cost design, the highest performance design, and other designs between these two in the design space. Sehwa is written in Franz Lisp and executes within minutes, for problems of practical size, on a VAX 11/750. >

405Â citations

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TL;DR: The DELIGHT.SPICE tool, a union of the DELIGHT interactive optimization-based computer-aided-design system and the SPICE circuit analysis program, is presented, yielding substantial improvement in circuit performance.

Abstract: DELIGHT.SPICE is the union of the DELIGHT interactive optimization-based computer-aided-design system and the SPICE circuit analysis program. With the DELIGHT.SPICE tool, circuit designers can take advantage of recent powerful optimization algorithms and a methodology that emphasizes designer intuition and man-machine interaction. Designer and computer are complementary in adjusting parameters of electronic circuits automatically to improve their performance criteria and to study complex tradeoffs between multiple competing objectives, while simultaneously satisfying multiple-constraint specifications. The optimization runs much more efficiently than previously because the SPICE program used has been enhanced to perform DC, AC, and transient sensitivity computation. Industrial analog and digital circuits have been redesigned using this tool, yielding substantial improvement in circuit performance. >

367Â citations

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TL;DR: The authors present state-assignment algorithms that heuristically maximize the number of common cubes in the encoded network to maximize theNumber of literals in the resulting combinational logic network after multilevel logic optimization.

Abstract: The problem of state assignment for synchronous finite-state machines (FSM), targeted towards multilevel combinational logic and feedback register implementations, are addressed. The authors present state-assignment algorithms that heuristically maximize the number of common cubes in the encoded network to maximize the number of literals in the resulting combinational logic network after multilevel logic optimization. Results over a wide range of benchmarks which prove the efficacy of the proposed techniques are presented. Literal counts averaging 20%-40% less than other state-assignment programs have been obtained. >

276Â citations

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TL;DR: The authors introduce the concept of R-minimality, which implies minimality with respect to cube reshaping, and demonstrate the crucial role played by this concept in multilevel minimization.

Abstract: An approach is described for the minimization of multilevel logic circuits. A multilevel representation of a block of combinational logic is defined, called a Boolean network. A procedure is then proposed, called ESPRESSOMLD, to transform a given Boolean network into a prime, irredundant, and R-minimal form. This procedure rests on the extension of the notions of primality and irredundancy, previously used only for two-level logic minimization, to combinational multilevel logic circuits. The authors introduce the concept of R-minimality, which implies minimality with respect to cube reshaping, and demonstrate the crucial role played by this concept in multilevel minimization. Theorems are given that prove the correctness of the proposed procedure. Finally, it is shown that prime and irredundant multilevel logic circuits are 100% testable for input and output single-stuck faults, and that these tests are provided as a byproduct of the minimization. >

254Â citations

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TL;DR: The deterministic sequential test-generation algorithm, based on extensions to the PODEM justification algorithm, is effective for midsized sequential circuits and can be used in conjunction with an incomplete scan design approach to generate tests for very large sequential circuits.

Abstract: An approach to test-pattern generation for synchronous sequential circuits is presented. The deterministic sequential test-generation algorithm, based on extensions to the PODEM justification algorithm, is effective for midsized sequential circuits and can be used in conjunction with an incomplete scan design approach to generate tests for very large sequential circuits. Tests for finite-state machines with a large number of states have been successfully generated using reasonable amounts of CPU time and close-to-maximum possible fault coverages have been obtained. For very large sequential circuits, an incomplete scan-design approach to test generation has been developed. The deterministic test generation algorithm is again used to generate test for faults in the modified circuit. All irredundant faults can be detected as in the complete scan design case, but at significantly less area and performance cost. The length of the test sequences for the faults can be bounded by a prescribed value-in general, a tradeoff exists between the number of memory elements required to be made scannable and the maximum allowed length of the test sequence. >

213Â citations

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TL;DR: This analysis shows that the traditional SSA fault model characterizes fewer than half of the faults extracted by FXT; graph-theoretic techniques provide little improvement in the percentage of realistic faults modeled.

Abstract: The inductive fault analysis (IFA) method is presented and a description is given of the CMOS fault extraction program FXT. The IFA philosophy is to consider the causes of faults (manufacturing defects) and then simulate these causes to find the faults that are likely to occur in a circuit. FXT automates IFA for a CMOS technology by generating a list of faults that are likely to occur in a CMOS circuit. The realistic faults generated by FXT are used to evaluate fault models, find the realistic fault coverage of test sets, and guide future testing research. How well various fault models characterize the realistic faults can be quantitatively measured because FXT's fault list includes the relative likelihood of occurrence (weight) of each extracted fault. The value of IFA and FXT is demonstrated by the analysis of five commercial CMOS circuits. This analysis shows that the traditional SSA fault model characterizes fewer than half of the faults extracted by FXT; graph-theoretic techniques provide little improvement in the percentage of realistic faults modeled. >

205Â citations

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TL;DR: A method for logic design verification is introduced in which a gate-level implementation of a circuit is compared with a functional-level specification and it is shown that the class of design errors that can be detected is very large.

Abstract: A method for logic design verification is introduced in which a gate-level implementation of a circuit is compared with a functional-level specification. In this method, test patterns that were developed to detect single stuck-line faults in the gate-level implementation are used instead to compare the gate-level implementation with the functional-level specification. In the presence of certain hypothesized design errors, such a test set will produce responses in the implementation that disagree with the responses in the specification. It is shown that the class of design errors that can be detected in this way is very large. >

188Â citations

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TL;DR: The authors present a fault coverage analysis method for test generation and fault diagnosis of large combinational circuits using a 16-valued logic system, GEMINI, and an extended fault model which includes stuck-at, stuck-open, and delay faults is used.

Abstract: The authors present a fault coverage analysis method for test generation and fault diagnosis of large combinational circuits. Input vectors are analyzed in pairs in two steps using a 16-valued logic system, GEMINI. Forward propagation is performed to determine, for each line in the network, the set of all possible values it can take if the network contains any single or multiple faults. Based on the values observed at primary outputs, backward implication is performed to determine the value actually carried by each line. Some deduced values imply the line is not faulty; similarly, some values imply that there is a fault in the subnetwork driving the line, or on the line itself. By keeping track of this information, it is possible to locate a fault to within its equivalence class. An extended fault model which includes stuck-at, stuck-open, and delay faults is used. Multiple faults of all multiplicities are implicitly considered; thus, the results obtained using this method are not invalidated in the presence of untested or untestable lines. >

164Â citations

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TL;DR: A discretization scheme is applied to the hydrodynamic model for semiconductor devices that generalizes the Scharfetter-Gummel method to both the momentum-conservation and the energy-cons conservation equations, providing a satisfactory description of such effects as velocity overshoot and carrier heating.

Abstract: A discretization scheme is applied to the hydrodynamic model for semiconductor devices that generalizes the Scharfetter-Gummel method to both the momentum-conservation and the energy-conservation equations. The major advantages of the scheme are: (1) the discretization is carried out without neglecting any terms, thus providing a satisfactory description of such effects as velocity overshoot and carrier heating; and (2) the resulting equations lend themselves to a self-consistent solution procedure similar to those currently used to solve the simpler drift-diffusion equations. Two-dimensional steady-state simulations of an n-channel MOSFET and of an n-p-n BJT (bipolar junction transistor) have been carried out by means of an improved version of the program HFIELDS. Carrier-temperature plots have been obtained with a reasonable computational effort, demonstrating the efficiency of this technique. The results have been compared with those obtained with the standard drift-diffusion model and significant differences in the electron concentration have been found, especially at the drain end of the MOSFET channel. >

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IBM

^{1}TL;DR: To investigate the question of what happens to aliasing errors in general, the function of LFSRs is modeled by a Markov process and a solution is obtained by the z-transform.

Abstract: Aliasing errors in linear feedback shift registers (LFSRs) used as signature analysis registers in self-testing networks are considered. A bound on aliasing is established by a straightforward algebraic analysis of LFSRs. It is calculated as a function of p, the probability of an error occurring at an output of the network under test. This bound is robust but is only good for p close to 1/2. To investigate the question of what happens to aliasing errors in general, the function of LFSRs is modeled by a Markov process and a solution is obtained by the z-transform. It is shown that for p>1/2 the aliasing probability for primitive polynomials converges much faster to the final steady-state value than for nonprimitive polynomials. For values of p >

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TL;DR: An algorithm to synthesize registers using multiport memories during data-path synthesis is presented, which considers not only the access requirements of registers but also their interconnection to operators in order to minimize required interconnections.

Abstract: An algorithm to synthesize registers using multiport memories during data-path synthesis is presented. The proposed approach considers not only the access requirements of registers but also their interconnection to operators in order to minimize required interconnections. The same approach can be applied to select the optimum number of buses in a multibus architecture. The method is illustrated with an example. >

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Motorola

^{1}TL;DR: In this paper, a statistically oriented methodology for optimization and sensitivity analysis of VLSI process, device, and circuit design through computer simulation has been developed, where emphasis has been placed on maintaining a clear distinction between design synthesis and design analysis.

Abstract: A statistically oriented methodology for optimization and sensitivity analysis of VLSI process, device, and circuit design through computer simulation has been developed. Emphasis has been placed on maintaining a clear distinction between design synthesis and design analysis. Design analysis is viewed as a multiple input-output system resulting in a multiple-constraints-optimization problem. It is shown how simple graphic techniques or rigorous mathematical optimization can be performed within a constrained desirability space to determine optimal operating conditions. This leads directly to the concept of global input factors. Which affect a large number of the response variables, and specific input factors, which can be used to adjust the operating level of a small number of response variables. By using the derived empirical equations to desensitize the responses to variations in input factors, the proposed methodology can play a key role in designing for manufacturability. As proof of concept, the methodology has been applied to the optimization of a VLSI BIMOS technology, with satisfactory results. >

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Siemens

^{1}TL;DR: It is shown that with up-to-date dimensions, the simple parallel-plate model is no longer adequate, and easy- to-use and fast-To-compute formulas exist that result in accurate and reliable capacitance values.

Abstract: A comparison is made between various approximations of the line-to-ground capacitance problem in a VLSI environment. It is shown that with up-to-date dimensions, the simple parallel-plate model is no longer adequate. However, easy-to-use and fast-to-compute formulas exist that result in accurate and reliable capacitance values. >

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TL;DR: These approaches achieve significant speedup over uniprocessor simulated annealing, giving high-quality VLSI placement of standard cells in a short period of time.

Abstract: An algorithm called heuristic spanning creates parallelism by simultaneously investigating different areas of the plausible combinatorial search space. It is used to replace the high-temperature portion of simulated annealing. The low-temperature portion of simulated annealing is sped up by a technique called section annealing, in which placement is geographically divided and the pieces are assigned to separate processors. Each processor generates simulated-annealing-style moves for the cells in its area and communicates the moves to other processors as necessary. Heuristic spanning and section annealing are shown experimentally to converge to the same final cost function as regular simulated annealing. These approaches achieve significant speedup over uniprocessor simulated annealing, giving high-quality VLSI placement of standard cells in a short period of time. >

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TL;DR: Two techniques are presented for optimizing the parametric yield of digital MOS circuit blocks for VLSI designs based on quasi-Newton methods and utilizes the gradient of the yield.

Abstract: Two techniques are presented for optimizing the parametric yield of digital MOS circuit blocks for VLSI designs. The first is based on quasi-Newton methods and utilizes the gradient of the yield. A novel technique for computing this yield gradient is derived and algorithms for its implementation are discussed. Geometrical considerations motivate the second method which formulates the problem in terms of a minimax problem. Both yield optimization techniques utilize transient sensitivity information from circuit simulations. Encouraging results have been obtained thus far; several circuit examples are included to demonstrate these techniques. >

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TL;DR: With this method, the length of time required for all of the test vectors to appear, possibly in some order, among the normal inputs to the circuit under test is of considerable importance.

Abstract: A method is presented for testing digital circuits during normal operation. The resources used to perform online testing are those which are inserted to alleviate the offline testing problem. The offline testing resources are modified so that during system operation they can also observe the normal inputs and outputs of a combinational circuit under test. The normal inputs to the circuit under test are with test vectors in its test set. When a normal input matches a test vector, the circuit output for such an input is typically compressed into a developing signature. When all of the test vectors in the test set have appeared as normal inputs, the signature is read and verified. With this method, the length of time required for all of the test vectors to appear, possibly in some order, among the normal inputs to the circuit under test is of considerable importance. >

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TL;DR: An algorithm is presented for the verification of the equivalence of two sequential circuit descriptions at the same of differing levels of abstraction, namely, at the register-transfer (RT) level and the logic level.

Abstract: An algorithm is presented for the verification of the equivalence of two sequential circuit descriptions at the same of differing levels of abstraction, namely, at the register-transfer (RT) level and the logic level. The descriptions represent general finite automata at the differing levels. A finite automaton can be described in ISP-like language and its equivalence to a logic level implementation can be verified using this algorithm. Two logic-level automata can be similarly verified for equivalence. The technique is shown to be computationally efficient for complex circuits. The efficiency of the algorithm lies in the exploitation of don't care information derivable from the RT or logic-level description during the verification process. Using efficient cube enumeration procedures at the logic level, the equivalence of finite automata with a large number of states in small amounts of CPU time was verified. A two-phase enumeration-simulation algorithm for verifying the equivalence of two logic-level finite automata with the same or differing number of latches is also presented. >

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TL;DR: The practicality of using signature registers as pseudorandom pattern generators is investigated by fault simulation experiments using an example circuit and it is shown that the patterns generated by signature registers are rarely repeated when the number of test patterns is relatively small compared to thenumber of possible patterns.

Abstract: Signature registers are commonly used to collect test responses in built-in self-testing (BIST). If the contents of signature registers can be used as test patterns, the overall testing time can be reduced due to improved testing parallelism. Moreover, the number of extra registers for implementing BIST could be reduced. Here, the characteristics of the patterns generated by signature registers are studied through analyses as well as experiments. It is shown that the patterns generated by signature registers are rarely repeated when the number of test patterns is relatively small compared to the number of possible patterns. It is also shown that the patterns generated are almost uniformly distributed. Therefore, signature registers can be used effectively as pseudorandom pattern generators. The practicality of using signature registers as pseudorandom pattern generators is investigated by fault simulation experiments using an example circuit. >

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TL;DR: BEAVER combines a delayed layering scheme with computational geometry techniques to heuristically produce a switchbox solution that minimizes both via and usage and wire length, and maximizes the use of a preferred routing layer.

Abstract: BEAVER combines a delayed layering scheme with computational geometry techniques to heuristically produce a switchbox solution that minimizes both via and usage and wire length, and maximizes the use of a preferred routing layer. Other important features are its use of priority queues to determine the order in which nets are routed, and its prioritized control of individual track and column usage to prevent routing conflicts. BEAVER consists of four tools that are run successively: a corner router, a line sweep router, a thread router, and a layerer. The corner router makes single-bend terminal-to-terminal connections. The line sweep router makes straight-line connections, single-bend connections, and two-bend connections. The thread router makes connections of arbitrary form. The layerer completes the switchbox by layering wires that have been assigned a location but not yet a layer. BEAVER has successfully routed all of the classic switchboxes. Its solution quality with respect to wire length was better than, or comparable to, the best previous solutions and its via usage was consistently the minimum. >

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TL;DR: An efficient Monte Carlo device simulator has been developed as a postprocessor of a two-dimensional numerical analyzer based on the drift-diffusion model, leading to a CPU time saving of at least one order of magnitude compared with the traditional approach.

Abstract: An efficient Monte Carlo device simulator has been developed as a postprocessor of a two-dimensional numerical analyzer based on the drift-diffusion model. The Monte Carlo package analyzes real VLSI MOSFETs in a minicomputer environment, overcoming some existing theoretical and practical problems. In particular, the particle free-flight time distribution is obtained by a new algorithm, leading to a CPU time saving of at least one order of magnitude compared with the traditional approach. To describe rare electron configurations, such as the high-energy tails of the distributions and the particle dynamics in the presence of large retarding fields, a multiple repetition scheme was implemented. Selected applications are presented to illustrate the simulator's capabilities. >

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TL;DR: A computer program has been written to allow simultaneous solution of an electrical network containing both nonlinear circuit elements and two-dimensional finite-element solid-state models.

Abstract: A computer program has been written to allow simultaneous solution of an electrical network containing both nonlinear circuit elements and two-dimensional finite-element solid-state models. The circuit solver is based on the popular SPICE-II program, while the PISCES-II program is used to model the solid-state devices. Both steady-state DC and time-dependent solutions are possible. Additional features have also been added to the solid-state model, including photogeneration and the optional use of cylindrical coordinates. >

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TL;DR: Two hybrid schemes for the design of maximum-length sequence generators (MLSGs) are presented and it is shown that the reconfiguration is very simple and the hardware overhead is low.

Abstract: Two hybrid schemes for the design of maximum-length sequence generators (MLSGs) are presented. Compared to an n-stage maximum-length LFSR (for generating 2/sup n/-1 nonzero distinct states) that uses m exclusive-or (XOR) gates, this hybrid MLSG will use exactly (m+1)/2 XOR gates if its characteristic polynomial meets certain requirements. For applications such as exhaustive testing, this hybrid MLSG is then reconfigured to include the all-zero state. It is shown that the reconfiguration is very simple and the hardware overhead is low. >

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TL;DR: A macromodeling and timing simulation technique is presented that allows fast and accurate delay calculations for CMOS circuits, well suited for delay calculations of regular structure VLSI circuits, as well as circuits designed from standard cell libraries.

Abstract: A macromodeling and timing simulation technique is presented that allows fast and accurate delay calculations for CMOS circuits. This method is well suited for delay calculations of regular structure VLSI circuits, as well as circuits designed from standard cell libraries. Timing models for both logic gate and transmission gate circuit forms are developed. Typical delay times were within 5% for logic gate circuits and 10% for transmission gate circuits when compared with SPICE results. The execution time of experimental simulator was over two orders of magnitude faster than SPICE. >

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TL;DR: A probabilistic model for pseudorandom testing of combinational circuits is presented and the expected fault coverage is shown to be accurately approximated as a series of exponentials that depends on the test length and the fault detectabilities.

Abstract: A probabilistic model for pseudorandom testing of combinational circuits is presented. The expected fault coverage is shown to be accurately approximated as a series of exponentials that depends on the test length and the fault detectabilities. The derivations do not require the pattern generator to have the same number of stages as there are network inputs. >

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TL;DR: Implementation methods based on cyclic codes are presented for pseudoexhaustive testing of combinational logic networks with restricted output dependency, using a modified linear-feedback shift register to generate exhaustive test patterns for every output of the circuit.

Abstract: Implementation methods based on cyclic codes are presented for pseudoexhaustive testing of combinational logic networks with restricted output dependency. A modified linear-feedback shift register (LFSR) is used to generate exhaustive test patterns for every output of the circuit. All detectable, combinational faults (those that do not change a combinational circuit to a sequential circuit) in each cone of logic driving a single output are guaranteed to be detected. Examples indicate that LFSRs based on cyclic codes have lower hardware cost and shorter or comparable test lengths than other approaches. These test-pattern generators are well suited to applications where short testing time, low hardware overhead, and 100% single-stuck-at fault coverage are required. >

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TL;DR: An alternative set of parameters for characterizing the linear, nonlinear, and statistical properties of analog-to-digital (A/D) converters is suggested, and an algorithm, referred to as the sinusoidal minimum error method is proposed to estimate the values of these parameters.

Abstract: Quantities such as peak error and integral or differential nonlinearity are commonly used to characterize the performance of analog-to-digital converters. However, these measures are not readily applicable to converter architectures that use feedback and oversampling. An alternative set of parameters for characterizing the linear, nonlinear, and statistical properties of analog-to-digital (A/D) converters is suggested, and an algorithm, referred to as the sinusoidal minimum error method is proposed to estimate the values of these parameters. The suggested approach is equally suited to examining the performance of A/D converters by means or either computer simulations of experimental measurements on actual circuits. >

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TL;DR: A performance metric is introduced for fault simulation, based on comparison with the serial algorithm, and is more accurate than those used in the past, which can improve fault-simulator performance by several orders of magnitude.

Abstract: MOZART, a concurrent fault simulator for large circuits described at the register-transfer, functional, gate, and switch levels, is described. The requirements of multilevel simulation have guided the definition of MOZART's syntax, value set, delay model, and algorithms. Performance is improved by reducing unnecessary activity. Two such techniques are levelized: two-pass simulation, which minimizes the number of events and evaluations, and list event scheduling, which allows optimized processing of simultaneous (fraternal) events for concurrent machines. Moreover, efficient handling of abnormally large or active fault machines can improve fault-simulator performance by several orders of magnitude. These and related issues are discussed; both analytical and experimental evidence is provided for the effectiveness of the solutions adopted in MOZART. A performance metric is introduced for fault simulation, based on comparison with the serial algorithm, and is more accurate than those used in the past. >

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TL;DR: In this article, the authors compared the analytical solutions to the numerical results to test the limits of the assumptions used in the analytic formulation and concluded that analytic solutions are of limited use in prediction of point defect profiles in two dimensions.

Abstract: Two-dimensional process modeling has been complicated by the increasing complexity of the physical models needed to characterize modern processes. Present physical models for diffusion favor modeling of both the vacancies and interstitials as well as the dopant impurities. these vacancies and interstitials are important in two dimensions since the lateral characteristic lengths are on the order of a few microns, which is comparable to device dimensions. Hence, full two-dimensional solutions of the point defect equations are required to accurately model two-dimensional diffusion. Since the defects diffuse many order of magnitude faster than the impurities, the problem of solving the coupled equations is numerically stiff and the numerical techniques become critical. The numerical methods in SUPREM-IV are described. Since the numerical solutions are time consuming, suitable analytic solutions are considered as an alternative. These analytic solutions are compared to the numerical results to test the limits of the assumptions used in the analytic formulation. The comparison forces the conclusion that analytic solutions are of limited use in prediction of point defect profilesin two dimensions. >