Showing papers in "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems in 1990"

Asymptotic waveform evaluation for timing analysis

Abstract: Asymptotic waveform evaluation (AWE) provides a generalized approach to linear RLC circuit response approximations. The RLC interconnect model may contain floating capacitors, grounded resistors, inductors, and even linear controlled sources. The transient portion of the response is approximated by matching the initial boundary conditions and the first 2q-1 moments of the exact response to a lower-order q-pole model. For the case of an RC tree model, a first-order AWE approximation reduces to the RC tree methods. >

Rigorous thermodynamic treatment of heat generation and conduction in semiconductor device modeling

Abstract: A treatment of the self-heating problem is presented. It is based on the laws of phenomenological irreversible thermodynamics (e.g. Onsager's relations and conservation of total energy) and is also consistent with the physical models usually considered in the isothermal drift diffusion approximation. The classical isothermal device equations are extended and completed by a generalized heat-conduction equation involving heat sources and sinks which, besides Joule and Thomson heat, reflect the energy exchanged through recombination (radiative and nonradiative) and optical generation. Thus the extended model also applies to direct semiconductors (e.g., optoelectronic devices) and accounts for effects caused by the ambient light intensity. It fully allows for low temperature since the case of incomplete ionization of donors and acceptors (impurity freeze-out) is properly incorporated in the theory. A critical comparison with previous work is made, showing that, in the steady state, some of the heuristic models of heat generation, thermal conductivity, and heat capacity could indeed approximate the correct results within an error bound of 1-10%. In the transient regime, however, none of the models used previously seems to be reliable, particularly, if short switching times ( >

OPASYN: a compiler for CMOS operational amplifiers

Abstract: A silicon compilation system for CMOS operational amplifiers (OPASYN) is discussed. The synthesis system takes as inputs system-level specifications, fabrication-dependent technology parameters, and geometric layout rules. It produces a design-rule-correct compact layout of an optimized operational amplifier. The synthesis proceeds in three stages: (1) heuristic selection of a suitable circuit topology; (2) parametric circuit optimization based on analytic models; and (3) mask geometry construction using a macro cell layout style. The synthesis process is fast enough for the program to be used interactively at the system design level by system designers who are inexperienced in operational amplifier design. >

NOVA: state assignment of finite state machines for optimal two-level logic implementation

Abstract: The problem of encoding the states of a synchronous finite state machine (FSM) so that the area of a two-level implementation of the combinational logic is minimized is addressed. As in previous approaches, the problem is reduced to the solution of the combinatorial optimization problems defined by the translation of the cover obtained by a multiple-valued logic minimization or by a symbolic minimization into a compatible Boolean representation. The authors present algorithms for this solution, based on a novel theoretical framework that offers advantages over previous approaches to develop effective heuristics. The algorithms are part of NOVA, a program for optimal encoding of control logic. Final areas averaging 20% less than other state assignment programs and 30% less than the best random solution have been obtained. Literal counts averaging 30% less than the best random solutions have been obtained. >

A realistic fault model and test algorithms for static random access memories

Abstract: Testing static random access memories (SRAMs) for all possible failures is not feasible and one must restrict the class of faults to be considered. This restricted class is called a fault model. A fault model for SRAMs based on physical spot defects, which are modeled as local disturbances in the layout of the SRAM, is presented. Two linear test algorithms that cover 100% of the faults under the fault model are proposed. A general solution is given for testing word-oriented SRAMs. The practical validity of the fault model and the two test algorithms are verified by a large number of actual wafer tests and device failure analyses. >

A genetic approach to standard cell placement using meta-genetic parameter optimization

Abstract: The genetic algorithm applies transformations on the chromosonal representation of the physical layout. The algorithm works on a set of configurations constituting a constant-size population. The transformations are performed through crossover operators that generate a new configuration assimilating the characteristics of a pair of configurations existing in the current population. Mutation and inversion operators are also used to increase the diversity of the population, and to avoid premature convergence at local optima. Due to the simultaneous optimization of a large population of configurations, there is a logical concurrency in the search of the solution space which makes the genetic algorithm an extremely efficient optimizer. Three efficient crossover techniques are compared, and the algorithm parameters are optimized for the cell-placement problem by using a meta-genetic process. The resulting algorithm was tested against TimberWolf 3.3 on five industrial circuits consisting of 100-800 cells. The results indicate that a placement comparable in quality can be obtained in about the same execution time as TimberWolf, but the genetic algorithm needs to explore 20-50 times fewer configurations than does TimberWolf. >

The analysis of one-dimensional linear cellular automata and their aliasing properties

Abstract: It is shown how to construct a general linear hybrid cellular automaton (CA) such that it has a maximum length cycle, and how the aliasing properties of such automata compare with linear feedback shift registers (LFSRs) when used as signature analyzers The construction is accomplished by formally demonstrating the isomorphism which binds this kind of CA to the LFSRs Consequently, these CAs can be analyzed as linear machines Linear algebraic techniques are then applied appropriately for the transformations, and a useful search algorithm is developed which, given an irreducible characteristic polynomial, finds a corresponding linear hybrid automaton Such CAs are tabulated for all irreducible and primitive polynomials up to degree 16, plus a selection of others of higher degree The behavior of a linear hybrid CA and that of its corresponding LFSR are similar-that is, they have the same cycle structure and only relabel the states The aliasing properties, when they are used as signature analyzers, remain unchanged >

Probabilistic simulation for reliability analysis of CMOS VLSI circuits

Abstract: A current-estimation approach to support the analysis of electromigration (EM) failures in power supply and ground buses of CMOS VLSI circuits is discussed. It uses the original concept of probabilistic simulation to efficiently generate accurate estimates of the expected current waveform required for electromigration analysis. Thus, the approach is pattern-independent and relieves the designer of the tedious task of specifying logical input waveforms. This approach has been implemented in the program CREST (current estimator) which has shown excellent accuracy and dramatic speedups compared with traditional approaches. The approach and its implementation are described, and the results of numerous CREST runs on real circuits are presented. >

Hierarchical test generation using precomputed tests for modules

Abstract: A novel test generation technique for large circuits with high fault coverage requirements is described. The technique is particularly appropriate for circuits designed by silicon compilers. Circuit modules and signals are described at a high descriptive level. Test data for modules are described by predefined stimulus/response packages that are processed symbolically using techniques derived from artificial intelligence. The packages contain sequences of stimulus and response vectors which are propagated as units. Since many test vectors are processed simultaneously, a substantial increase in test generation speed can be achieved. A prototype test generator which uses the technique to generate tests for acyclic circuits has been implemented. Preliminary results from this program suggest that for circuits composed of datapath elements, speed improvements of three orders of magnitude over conventional techniques may be possible. >

Continuous signature monitoring: low-cost concurrent detection of processor control errors

Abstract: A low-cost approach to concurrent detection of processor control errors is presented that uses a simple hardware monitor and signatures embedded into the executing program. Existing signature-monitoring techniques detect a large portion of processor control errors at a fraction of the cost of duplication. Analytical methods developed in this study show that the new approach, continuous signature monitoring (CSM), makes major advances beyond existing techniques. CSM reduces the fraction of undetected control-flow errors by orders of magnitude, to less than 10/sup -6/, while the number of signatures reaches a theoretical minimum, being lowered by as much as three times to a range of 4-11%. Signature cost is reduced by placing CSM signatures at locations that minimize performance loss and (for some architectures) memory overhead. CSM exploits the program memory's SEC/DED code to decrease error-detection latency by as much as 1000 times, to 0.016 program memory cycles, without increasing memory overhead. This short latency allows transient faults to be tolerated. >

New algorithms for the rectilinear Steiner tree problem

Abstract: An approach to constructing the rectilinear Steiner tree (RST) of a given set of points in the plane, starting from a minimum spanning tree (MST), is discussed. The main idea in this approach is to find layouts for the edges of the MST that maximize the overlaps between the layouts, thus minimizing the cost (i.e. wire length) of the resulting rectilinear Steiner tree. Two algorithms for constructing rectilinear Steiner trees from MSTs, which are optimal under the conditions that the layout of each edge of the MST is an L shape or any staircase, respectively, are described. The first algorithm has linear time complexity and the second algorithm has a higher polynomial time complexity. Steiner trees produced by the second algorithm have a property called stability, which allows the rerouting of any segment of the tree, while maintaining the cost of the tree, and without causing overlaps with the rest of the tree. Stability is a desirable property in VLSI global routing applications. >

Multiple distributions for biased random test patterns

Abstract: The test of integrated circuits by random patterns is very attractive, since no expensive test pattern generation is necessary and tests can be applied with a self-test technique or externally using linear feedback shift registers. Unfortunately, not all circuits are random-testable, because either the fault coverage is too low or the required test length too large. In many cases the random test lengths can be reduced by orders of magnitude using weighted random patterns. However, there are also some circuits for which no single optimal set of weights exists. A set of weights defines a distribution of the random patterns. It is shown that the problem can be solved using several distributions instead of a single one, and an efficient procedure for computing the optimized input probabilities is presented. If a sufficient number of distributions is applied, then all combinational circuits can be tested randomly with moderate test lengths. The patterns can be produced by an external chip, and an optimized test schedule for circuits with a scan path can be obtained. Formulas are derived to determine strong bounds on the probability of detecting all faults. >

On computing the sizes of detected delay faults

Abstract: Defects in integrated circuits can cause delay faults of various sizes. Testing for delay faults has the goal of detecting a large fraction of these faults for a wide range of fault sizes. Hence, an evaluation scheme for a delay fault test must not only compute whether or not a delay fault was detected, but also calculate the sizes of detected delay faults. Delay faults have the counterintuitive property that a test for a fault of one size need not be a test for a similar fault of a larger size. This makes it difficult to answer questions about the sizes of delay faults detected by a set of tests. A model for delay faults that answers such questions correctly, but with calculations simple enough to be done for large circuits, is presented. >

Incorporating bottom-up design into hardware synthesis

Abstract: A novel method for using bottom-up design information in the synthesis of integrated circuits from abstract behavioral description is reported. There are two important ways in which this method differs from traditional top-down synthesis techniques. First, it draws on a newly developed procedural database to collect detailed information on the physical and logical properties of the primitives available for building the design. Second, it partitions each design it considers into clusters that have physical as well as logical significance. This method for representing and organizing knowledge about candidate designs makes it possible to estimate physical placement and wiring, even at the abstract register-transfer (RT) level. This allows a more accurate evaluation of RT designs without doing a full logic-level or transistor-level layout. Partitioning also leads to a simple method for systematically exploring the space of possible designs to find the one that best meets the designer's objectives and constraints. >

Estimation of maximum currents in MOS IC logic circuits

Abstract: The authors deal with estimating currents in nMOS/CMOS IC logic circuits at three levels of hierarchies: gate level, macro level, and power/ground distribution level Models are developed for estimating currents in a macro-cell (macro) in response to input excitations Algorithms are developed to estimate the maximum current requirement for a macro and to identify the input excitation at which the maximum current occurs The macro currents are used to estimate the maximum currents in the segments of power (ground) distribution systems Some of the algorithms provide tradeoff between runtime and quality of solutions Experimental results are included >

Chippe: a system for constraint driven behavioral synthesis

Abstract: The Chippe system for constrained behavioural architecture synthesis uses a novel closed-loop design iteration technique in which the present state of the design is analyzed with respect to the goals and then modified for the next iteration. In this way the design state is iteratively driven towards meeting the global constraints imposed by the designer. The design synthesis is performed by a set of algorithmic tools specially constructed to permit the imposition of a wide variety of local constraints, and by a rule-based system which makes design analysis and modification decisions to set these local constraints. Key to these decisions is a design evaluator which examines the present state of the design and interactively reports its findings to the rule-based system. The closed-loop iteration strategy, the interaction between the rule base and the tools, and the evaluation performed to support the design decisions are detailed. Also presented are results from sample designs, including designs for the TMS320 digital signal processor chip. >

New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement

Abstract: Two approaches for the repair of large random access memory (RAM) devices in which redundant rows and columns are added as spares are presented. These devices, referred to as redundant RAMs, are repaired to achieve acceptable yield at manufacturing and production times. The first approach, the faulty line covering technique, is a refinement of the fault-driven approach. This approach finds the optimal repair solution within a smaller number of iterations than the fault-driven algorithm. The second approach exploits a heuristic criterion in the generation of the repair solution. This heuristic criterion permits a fast repair. The criterion is based on the calculation of efficient coefficients for the rows and columns of the memory. Simulation results are presented. Comparison of the proposed heuristic approaches with the fully exhaustive approach shows that repair can be accomplished in most cases. A considerable reduction in processing and complexity (number of records generated in the repair process for finding the optimal repair solution) is accomplished. >

Global routing based on Steiner min-max trees

Abstract: Global routing of multiterminal nets is studied. A novel global router is proposed; each step consists of finding a tree, called a Steiner min-max tree, that is Steiner tree with maximum-weight edge minimized (real vertices represent channels containing terminals of a net, Steiner vertices represent intermediate channels, and weights correspond to densities). An O (min(e loglog e, n/sup 2/)) time algorithm is proposed for obtaining a Steiner min-max tree in a weighted graph with e edges and n vertices. (This result should be contrasted with the NP-completeness of the traditional minimum-length Steiner tree problem). Experimental results on difficult examples, on randomly generated data, on master slice chips, and on benchmark examples from the Physical Design Workshop are included. >

An efficient microcode compiler for application specific DSP processors

Abstract: A computer program for microcode compilation for custom digital signal processors is presented. This tool is part of the CATHEDRAL II silicon compiler. The following optimization problems are highlighted: scheduling, hardware assignment, and loop folding. Efficient techniques to solve these problems are developed. This allows for the automatic synthesis of processor architectures which simultaneously exploit pipelining and parallelism. A demonstrator design is presented. >

A parallel branch and bound algorithm for test generation

Abstract: For circuits of VLSI complexity, test generation time can be prohibitive. Most of the time is consumed by hard-to-detect (HTD) faults, which might remain undetected even after a large number of backtracks. The problems inherent in a uniprocessor implementation of a test generation algorithm are identified, and a parallel test generation method which tries to achieve a high fault coverage for HTD faults in a reasonable amount of time is proposed. A dynamic search space allocation strategy which allocates disjoint search spaces to minimize the redundant work is proposed. The search space allocation strategy tries to utilize the partial solutions generated by other processors to increase the probability of searching in a solution area. The parallel test generation algorithm has been implemented on an Intel iPSC/2 hypercube. It is shown that parallel processing of HTD faults does indeed result in high fault coverage, which is otherwise not achievable by a uniprocessor algorithm. The parallel algorithm exhibits superlinear speedups in some cases due to search anomalies. >

Timing verification using statically sensitizable paths

Abstract: A new approach to the false path problem in timing verifiers is presented. This approach is based on the modeling of both the logic and timing behavior of a circuit. Using the logic propagation conditions associated with each delay, efficient algorithms have been developed to find statically sensitizable paths. These algorithms simultaneously perform a longest path search and a partial verification of the sensitization of the paths. The resulting paths undergo a final and complete sensitization. The algorithms find the longest statically sensitizable path, whose length is a lower bound to the critical path length, and its associated sensitizing input vector. The algorithms can be easily modified to provide an ordered list of all the statically sensitizable paths above a given threshold. An initial analysis of the circuit by the PERT algorithm guides the critical path search and allows pruning of subgraphs that cannot lead to the solution. Results show that these techniques succeed in curbing the combinatorial explosion associated with the longest statically sensitizable path search. >

Irredundant sequential machines via optimal logic synthesis

Abstract: It is shown that optimal sequential logic synthesis can produce irredundant, fully testable finite-state machines. Synthesizing a sequential circuit from a state transition graph description involves the steps of state minimization, state assignment, and logic optimization. Previous approaches to producing fully and easily testable sequential circuits have involved the use of extra logic and constraints on state assignments and logic optimization. Here it is shown that 100% testability can be ensured without the addition of extra logic and without constraints on the state assignment and logic optimization. Unlike previous synthesis approaches to ensuring fully testable machines, there is no area/performance penalty associated with this approach. This technique can be used in conjunction with previous approaches to ensure that the synthesized machine is easily testable. Given a state-transition-graph specification, a logic-level automaton that is fully testable for all single stuck-at faults in the combinational logic without access to the memory elements is synthesized. >

A method of fault simulation based on stem regions

Abstract: An exact fault simulation can be achieved by simulating only the faults on reconvergent fan-out stems, while determining the detectability of faults on other lines by critical path tracing within fan-out-free regions. The authors have delimited, for every reconvergent fan-out stem, a region of the circuit outside of which the stem fault does not have to be simulated. Lines on the boundary of such a stem region, called exit lines, have the following property: if the stem fault is detected on the line and the line is critical with respect to a primary output, then the stem fault is detected at that primary output. Any fault simulation technique can be used to simulate the stem fault within its stem region. The fault simulation complexity of a circuit is shown to be directly related to the number and size of stem regions in the circuit. The concept of stem regions has been used as a framework for an efficient fault simulator for combinational circuits. The concept allows a static reduction of the circuit area of explicit analysis for single- as well as multiple-output circuits. A dynamic reduction of processing steps is also achieved as the fault simulation progresses and fault coverage increases. The simulation algorithm is described, and experimental results are shown for the well-known benchmark circuits. >

Parallel global routing for standard cells

Abstract: The potential speedup of a standard cell global router using a general-purpose multiprocessor is investigated. LocusRoute, a global routing algorithm for standard cells, and its parallel implementation are presented. The uniprocessor speed and quality of LocusRoute is comparable to modern global routers. LocusRoute compares favorably with the TimberWolf 5.0 global router and a maze router that searches the same space more completely. Two successful methods of parallel decomposition of the router are presented. The first, in which multiple wires are routed in parallel, uses the notion of chaotic parallelism to achieve significant performance gains by relaxing data dependencies, at the cost of a minor loss in quality. Using iteration and careful assignment of wires to processors, this degradation is reduced. The approach achieves measured speedups from 5 to 14 using 15 processors. The second parallel decomposition technique is the evaluation of different routes for each wire on separate processors. It achieves speedups of up to 6 using 10 processors. It is demonstrated that when these two approaches are combined, the aggregate speedup is the product of the individual approaches' speedup, and, using an improved scheduling approach, it can be even greater. With a simple model based on these results, speedups of more than 75 using 150 processors are predicted. >

Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation

Abstract: Signal delay, chip area, and power dissipation are conflicting criteria for designing high-performance VLSI MOS circuits. Global optimization of transistor sizes in digital CMOS logic circuits with the design tool multiobjective gate-level optimization (MOGLO) is described. Analytical models for the design objectives are presented, and algorithms are discussed. Different techniques were combined to solve the circuit optimization problem with low computational costs. Precise gate-level delay models guarantee meaningful results, especially for high-speed logic circuits. >

An efficient small signal frequency analysis method of nonlinear circuits with two frequency excitations

Abstract: One of the excitations, 'carrier', is a large signal and an arbitrary T-periodic function of time. The other excitation, 'signal', is considered as a small perturbation to the periodic steady-state response driven by the carrier. To find a small signal frequency response for the 'signal', the method uses variational equations around the periodic steady-state response. These linearized time-varying differential equations are solved in the frequency domain using a time discretization method. The method can be used to compute the small signal frequency responses of nonideal switched capacitor filters, mixers, and other nonlinear circuits, if the circuit has a stable periodic response. The formulation of the problem, computational complexity of the method, error analysis, sensitivity analysis, implementation of the method, and some applications are covered. >

Computing signal delay in general RC networks by tree/link partitioning

Abstract: Most RC simulators handle only tree networks, not arbitrary networks. An algorithm is presented for computing signal delays in general RC networks using the RC-tree computation as the primary operation. The algorithm partitions a given network into a spanning tree and links. It computes the signal delay of the spanning tree, and updates the signal delay as it incrementally adds the links back to reconstruct the original network. If m is the number of links, this algorithm requires m(m+1)/2 updates and m+1 tree delay evaluations. All the tree delay evaluations involve computing signal delays with the same resistive spanning tree, but with different values for the capacitors. >

Tailor: a layout system based on trapezoidal corner stitching

Abstract: A VLSI layout design system named Tailor is described. Tailor operates on hierarchical layouts containing 45 degrees multiple angles. It consists of a well-integrated set of tools, including a window-driven editor, an incremental design rule checker, a circuit extractor, a one-dimensional compactor, a channel-based global router, and a transistor size optimizer. All tools use the same user interface and operate directly on Tailor's trapezoidal corner stitched database. Tailor's database structure is well suited for all of the tools because all important database operations, such as point searching, neighbor searching, area searching, and shadow searching, function very efficiently. All the tools in Tailor, except transistor optimization and routing, work directly on the layout hierarchy, which provides even greater efficiency. >

Layer assignment for multichip modules

Abstract: The layer assignment problem that arises in the design of a multichip module, a high-performance compact package for the interconnection of several hundred chips, is studied. The aim is to place each net in a x-y pair of layers, so as to minimize the number of such pairs. An approximation algorithm, running in O(nd) time is presented for minimizing the number of layers, where n is the number of nets and d is the (two-dimensional) density of the problem. >

Temperature measurement and equilibrium dynamics of simulated annealing placements

Abstract: One way to alleviate the heavy computation required by simulated annealing placement algorithms is to replace a significant fraction of the higher or middle temperatures with a faster heuristic, and then follow it with simulated annealing. A crucial issue in this approach is the determination of the starting temperature for the simulated annealing phase-a temperature should be chosen that causes an appropriate amount of optimization to be done, but makes good use of the structure provided by the heuristic. A method for measuring the temperature of an existing placement is presented. The approach is based on the measurement of the probability distribution of the change in cost function, P( Delta C), and makes the assumption that the placement is in simulated annealing equilibrium at some temperature. The temperature of placements produced by both a simulated annealing and a min-cut placement algorithm are measured, and good agreement with known temperatures is obtained. The P( Delta C) distribution is also used to give an interesting view of the equilibrium dynamics of simulated annealing. >