Showing papers in "IEEE Transactions on Computers in 1968"
TL;DR: The structure of ILLIAC IV, a parallel-array computer containing 256 processing elements, is described, special features include multiarray processing, multiprecision arithmetic, and fast data-routing interconnections.
Abstract: —The structure of ILLIAC IV, a parallel-array computer containing 256 processing elements, is described. Special features include multiarray processing, multiprecision arithmetic, and fast data-routing interconnections. Individual processing elements execute 4×10 6 instructions per second to yield an effective rate of 109 operations per second.
587 citations
TL;DR: A large part of the work is motivated by results and techniques which have been applied in the study of continuous-time linear dynamical systems and thus serves to point out the advantages which may accrue through simultaneous study of both continuous- time systems and linear sequential circuits.
Abstract: —This paper states the necessary and sufficient conditions for the existence of a feedforward inverse for a feedforward linear sequential circuit and gives an implicit procedure for constructing such inverses. It then goes on to give the necessary and sufficient conditions for the existence of general inverses with finite delay and gives procedures for constructing a class of such inverses. The discussion considers both the transfer function matrix description and the structural matrix description of the linear sequential circuit, together with the complementary nature of the results obtained from these two viewpoints. Finally, a large part of the work is motivated by results and techniques which have been applied in the study of continuous-time linear dynamical systems and thus serves to point out the advantages which may accrue through simultaneous study of both continuous-time systems and linear sequential circuits.
333 citations
IBM1
TL;DR: It is shown through example how the Boolean difference is used to analyze the effect of errors on the outputs of logic circuits.
Abstract: —The Boolean difference is defined. It is shown through example how the Boolean difference is used to analyze the effect of errors on the outputs of logic circuits. Examples are given of error detection problems, analysis of redundant logic, and the generation of diagnostic sequences.
203 citations
TL;DR: The nature of a class of division techniques which permit the selection of quotient digits in digital division by the inspection of truncated versions of the divisor and partial remainder is reviewed in detail.
Abstract: —The nature of a class of division techniques which permit the selection of quotient digits in digital division by the inspection of truncated versions of the divisor and partial remainder is reviewed in detail. Two types of mechanisms, or so-called model divisions, for the selection of quotient digits are introduced. For both types of techniques, analytic tools are suggested for determining the number of bits which must be inspected as a function of the radix and form of representation of quotient digits. The analysis accounts for the representation of the partial remainder in a redundant form such as the one produced by an adder-subtractor which eliminates carry-borrow propagation.
182 citations
TL;DR: A linear programming formulation of discriminant function design which minimizes the same objective function as the "fixed-increment" adaptive method is presented.
Abstract: —A common nonparametric method for designing linear discriminant functions for pattern classification is the iterative, or "adaptive," weight adjustment procedure, which designs the discriminant function to do well on a set of typical patterns. This paper presents a linear programming formulation of discriminant function design which minimizes the same objective function as the "fixed-increment" adaptive method. With this formulation, as with the adaptive methods, weights which tend to minimize the number of classification errors are computed for both separable and nonseparable pattern sets, and not just for separable pattern sets as has been the emphasis in previous linear programming formulations.
156 citations
TL;DR: A new way of computing the inner product of two vectors is described that can be performed using roughly n3/2 multiplications instead of the n3multiplications which the regular method necessitates.
Abstract: —In this note we describe a new way of computing the inner product of two vectors. This method cuts down the number of multiplications required when we want to perform a large number of inner products on a smaller set of vectors. In particular, we obtain that the product of two n×n matrices can be performed using roughly n3/2 multiplications instead of the n3multiplications which the regular method necessitates.
136 citations
TL;DR: Various network forms are described, differing in the number of cells needed, in the shape of the array, and in the length and regularity of intercell connections, which are some ways of setting up the array to achieve a desired permutation.
Abstract: —A class of networks is described that has the capability of permuting in an arbitrary manner a set of n digital input lines onto a set of n digital output lines. The circuitry of the networks is arranged in cellular form, i. e., in a two-dimensional iterative pattern with mainly local intercell connections, where the basic cell behaves as a reversing switch with a single memory flip-flop. Various network forms are described, differing in the number of cells needed, in the shape of the array, and in the length and regularity of intercell connections. Also discussed are some ways of setting up the array to achieve a desired permutation.
124 citations
TL;DR: A minimization technique suitable for computer implementation is presented and an algebra for switching circuits that may have multiple values is introduced.
Abstract: —An algebra for switching circuits that may have multiple values is introduced. A minimization technique suitable for computer implementation is then presented.
124 citations
TL;DR: An overview of the ILLIAC IV system is given and its software plans are discussed.
Abstract: —An overview of the ILLIAC IV system is given and its software plans are discussed.
118 citations
TL;DR: A precise, concise language is presented which facilitates the specification of complex digital systems and allows specification at different levels of detail from architecture to detailed Boolean equations.
Abstract: —Successful design and manufacture of future digital systems will depend upon the availability of a suitable design language. A precise, concise language is presented which facilitates the specification of complex digital systems. The language 1) is independent of any particular technology, design procedure, machine organization, etc., 2) allows specification at different levels of detail from architecture to detailed Boolean equations, and 3) may be com- piled into manufacturing information. Its syntax and semantics per- mit documents with an organization which parallels the block struc- ture of the systems they specify.
108 citations
TL;DR: The problem of designing test schedules for the testing or diagnosis of a small number of nontransient faults in combinational digital circuits (switching networks) is considered in detail and minimal test schedules can be readily derived.
Abstract: —he problem of designing test schedules for the testing or diagnosis of a small number of nontransient faults in combinational digital circuits (switching networks) is considered in detail. By testing and diagnosis we mean the following: 1) detection of a fault, 2) location of a fault, and 3) location of a fault within the confines of a prescribed package or module. It is shown that minimal test schedules can be readily derived–using procedures already worked out for solving certain problems in pattern recognition and switching theory–under the assumption that the selection of the test inputs in the schedule is independent of the response of the circuit under test. When this assumption is not made, it is shown that much shorter test schedules are sometimes possible, and procedures are offered for obtaining good ones. Finally, the general status of diagnostics for digital circuits is reviewed and evaluated, and specific problems remaining to be solved are described.
IBM1
TL;DR: An unconventional approach to character recognition is developed, based solely on the statistical properties of the language, therefore it can read printed text with no previous training or a priori information about the structure of the characters.
Abstract: —An unconventional approach to character recognition is developed. The resulting system is based solely on the statistical properties of the language, therefore it can read printed text with no previous training or a priori information about the structure of the characters. The known letter-pair frequencies of the language are used to identify the printed symbols in the following manner.
TL;DR: The generalized inverse computation is used to furnish a quick solution to the problem of fixed training samples and the use of recursive on-line computation is also recommended.
Abstract: —In this paper a least-square approach to multiclass pattern classification is undertaken. The generalized inverse computation is used to furnish a quick solution to the problem of fixed training samples. The use of recursive on-line computation is also recommended. Experimental results are presented to illustrate the approach. Both deterministic and statistical interpretations have been given to the approach. The pattern classifier proposed by Chaplin and Levadi [1] and the adaptive pattern classifier proposed by Patterson and Womack [2] are special cases of this approach.
TL;DR: The application of a fast division algorithm suitable for floating-point arithmetic to signed-digit number systems is described, based on the method of A. Svo-boda.
Abstract: —The application of a fast division algorithm, particu-larly suitable for floating-point arithmetic, to signed-digit number systems is described. This method, based on the method of A. Svo-boda, is performed in two steps: 1) the divisor is adjusted to be of the form (1+e) where e is a fractional quantity, while the dividend is adjusted accordingly, and 2) the generation of each quotient digit is determined by only one digit in the partial remainder together with the transfer digit (or carry/borrow) emanating from it. A working example of radix 16 is given.
TL;DR: This work considers the mapping of a functional's multidimensional bounded domain onto a bounded interval of the real line and suitably defining an equivalent function over the bounded interval so that properties of the original functional can be displayed.
Abstract: —The problem considered is the mapping of a functional's multidimensional bounded domain onto a bounded interval of the real line. This transformation is to have the property that "neighboring" points in the bounded interval are necessarily mapped from "neighboring" points in the bounded domain. The multidimensional bounded domain is partitioned into a finite number of elementary regions while the bounded interval is partitioned into the same finite number of elementary intervals. A one-to-one correspondence is defined between the elementary regions and intervals such that neighboring elementary intervals have corresponding multidimensional elementary regions that are neighboring. The degree of neighborliness is controlled by controlling the fineness of partitioning. By suitably defining an equivalent function over the bounded interval, properties of the original functional can be displayed.
TL;DR: The fixed-length distinguishing sequence (FLDS) is shown to be a special case of the more general VLDS and is applied in the design of simple and efficient preset fault-detection experiments for sequential machines.
Abstract: —A variable-length distinguishing sequence (VLDS) is a preset distinguishing sequence X 0 such that, if the machine is started in an unknown state, the output response of the machine to some prefix of X 0 will identify the initial state. The length of the required prefix is a function of the initial state. The properties of such sequences are investigated and a method which employs a modified version of the diagnosing tree is developed for generating and displaying all such sequences. The fixed-length distinguishing sequence (FLDS) is shown to be a special case of the more general VLDS. The VLDS is next applied in the design of simple and efficient preset fault-detection experiments for sequential machines.
TL;DR: A new approach to solving a set of nonlinear equations, described by fi(x1, x2, . . ., xn) = 0, i= 1, 2, ..., n, is presented, carried out by simple matrix inversion and matrix multiplication without evaluation of ∂fi/∂xj.
Abstract: —A new approach to solving a set of nonlinear equations, described by fi(x1, x2, . . ., xn) = 0, i= 1, 2, ..., n, is presented. The computation is carried out by simple matrix inversion and matrix multiplication without evaluation of ∂fi/∂xj. Thus, computation time is saved. The method converges rapidly if the initial approximation is close to the solution. A specific example, using nonlinear equations with two variables, shows the application of the method.
TL;DR: The possible introduction of changeable control memories in fourth-generation computers may color the manner in which programming systems are designed and implemented.
Abstract: —The possible introduction of changeable control memories in fourth-generation computers may color the manner in which programming systems are designed and implemented. With this type of machine, we will be able to implement varieties of instruction sets by writing microprograms to interpret them. The trade-offs involved in deciding what part of a system is to be handled by the hardware and what part is to be handled by software will provide a challenge for future systems designers and implementers.
TL;DR: This paper presents three methods for realizing asynchronous sequential circuits allowing multiple-input changes, but requiring that all input changes associated with an input transition be completed within a specified time after the first change.
Abstract: —A frequently imposed restriction in theoretical treatments of asynchronous sequential circuits is that only one input variable be allowed to change during a transition. In this paper, we present three methods for realizing asynchronous sequential circuits allowing multiple-input changes, but requiring that all input changes associated with an input transition be completed within a specified time after the first change. We also show that a single delay element is sufficient in the realization of normal mode flow tables, under these conditions.
TL;DR: A computer-oriented algorithm for synthesizing combinational logic circuits from a collection of functionally packaged circuits is developed that uses a hierarchy of "goals" in an iterative decision process in a manner similar to that employed by theorem proving and gamne playing programs.
Abstract: —A computer-oriented algorithm for synthesizing combinational logic circuits from a collection of functionally packaged circuits is developed. The algorithm uses a hierarchy of "goals" in an iterative decision process in a manner similar to that employed by theorem proving and gamne playing programs. With each iteration a set of "tasks" finds the circuit package which satisfies the highest level goal while meeting circuit constraints.
TL;DR: A method of extending the usefulness of residue coding (or congruence checking) to check for errors in operations such as complement, shift, and rotate (or cycle) is presented.
Abstract: —A method of extending the usefulness of residue coding (or congruence checking) to check for errors in operations such as complement, shift, and rotate (or cycle) is presented. The checking logic and a practical method for its implementation are derived. The cost of check circuitry is only of the order of 30 to 40 percent of the part of the processor that is subjected to checking. In another paper presently under review, a method for single error correction using a new code called "bi-residue code" is presented.
TL;DR: If the line delays are less than the minimum gate delay in the circuit, any normal mode sequential function can be realized without inserted delays and it is shown that a weaker line delay assumption is sufficient.
Abstract: —In an earlier paper, Unger showed that any normal mode flow table can be realized by an asynchronous sequential circuit without inserted delays in the feedback paths if and only if the flow table contains no essential hazards. No restrictions were placed on the relative magnitudes of line and gate delays. In this paper, we show that if the line delays are less than the minimum gate delay in the circuit, any normal mode sequential function can be realized without inserted delays. It is also shown that a weaker line delay assumption is sufficient. Two procedures for realizing asynchronous sequential circuits without inserted delays are presented.
TL;DR: A digital processor capable of computing the discrete Fourier transform for a range of audio signals in real time has been built as part of a facility to conduct research in signal processing.
Abstract: —A digital processor capable of computing the discrete Fourier transform for a range of audio signals in real time has been built as part of a facility to conduct research in signal processing. The digitized sample values can be complex. The arithmetic unit is configured to perform complex connectives, and automatic array scaling is used to make numerical accuracy independent of signal level. The Cooley–Tukey "fast Fourier transform" is the algorithm used.
TL;DR: This design procedure is based on the stochastic approximation technique, and has the updating property because it processes the sample patterns whenever they become available, and is shown to require very simple computation which leads to simple implementation.
Abstract: —A nonparametric training procedure for finding the optimal weights of the discriminant functions of a pattern classifier in any optimization criterion, expressible as a convex function from an arbitrary sequence of sample patterns, is proposed. This design procedure is based on the stochastic approximation technique, and has the updating property because it processes the sample patterns whenever they become available. This procedure is used to find the optimal weights for the least-mean-square error criterion, and is shown to require very simple computation which leads to simple implementation. Both two-category and multi-category cases are considered, and an acceleration scheme to increase the rate of convergence for the training procedure is also presented. These results are demonstrated by examples.
TL;DR: This paper shows that any switching function can be transformed to a completely symmetric switching function in which some of the arguments are redundant.
Abstract: —A number of techniques exist for realizing completely symmetric switching functions.1 Completely symmetric switching functions are particularly simple and economical to realize using contact-type gating elements. This paper shows that any switching function can be transformed to a completely symmetric switching function in which some of the arguments are redundant. (Obviously, if a given function is already completely symmetric no transformation is necessary.) The partial symmetry information inherent in a given function plays an important role in the transformation. Efficient machine-oriented methods exist for detecting the partial symmetries present in a switching function.
TL;DR: With slight modification the synthesis technique presented can be used to realize any given n-input-p-output synchronous sequential Moore machine in the form of a network composed of identical 2-state component machines.
Abstract: —A "synthesis technique" is presented for "realizing" any arbitrary binary input-binary output "synchronous sequential Moore machine" in the form of a network composed of identical 2-state "component machines." With slight modification the synthesis technique presented can be used to realize any given n-input-p-output synchronous sequential Moore machine in the form of a network composed of identical 2-state component machines.
TL;DR: Several methods of performing fast, efficient, binary-to-decimal conversion are described, each offering a unique advantage to general-purpose computers requiring special hardware to translate between binary and decimal numbering systems.
Abstract: —This note describes several methods of performing fast, efficient, binary-to-decimal conversion. With a modest amount of circuitry, an order of magnitude speed improvement is obtained. This achievement offers a unique advantage to general-purpose computers requiring special hardware to translate between binary and decimal numbering systems.
TL;DR: Nearest-neighbor classification is used to explain the high error rates obtained by general statistical procedures, and the minimum human error rate is estimated, and suggested as a performance standard.
Abstract: —The results of three experiments with Highleyman's hand-printed characters are reported. Nearest-neighbor classification is used to explain the high error rates (42 to 60 percent) obtained by general statistical procedures. An error rate of 32 percent is obtained by preceding piecewise-linear classification by edge-detecting preprocessing. The minimum human error rate is estimated, and suggested as a performance standard.
TL;DR: With the aid of Monte Carlo methods the following formula was obtained for the average cost, C(n, g, h), of the two-level minimal form of a 1-output combinational logical network which implements a Boolean function with g "one" vertices, h "zero" Vertices, and n independent variables: where the K's are constants.
Abstract: —The cost, or complexity, of a switching network is defined in two ways: by its diode count and by the number of modules from a predefined set required to build it. These modules were chosen as representative of a modular diode-transistor technology. With the aid of Monte Carlo methods the following formula was obtained for the average cost, C(n, g, h), of the two-level minimal form of a 1-output combinational logical network which implements a Boolean function with g "one" vertices, h "zero" vertices, and n independent variables: where the K's are constants. Since the same formula, except for the values of the constants, was obtained for the two different definitions of cost, one hopes that it would only be necessary to change the value of the constants to use the formula with other technologies. The formula was tested on 195 computer-generated samples. The average error was found to be 15.3 percent for the diode count and 15.7 percent for the module count. With the values of the K's set for predicting average diode count, the formula was tested on 48 existing networks. The average percentage error between predicted and actual cost was found to be 32.9 percent (the higher error is possibly due to a nonrandom selection of the input codes).
TL;DR: Basic theorems in the algebra are introduced first, and then, based on the theorem, table look-up oriented solutions for hardware overflow checking, sign detection, and floating-point additive operations are given.
Abstract: —A new residue number system algebra has been previously proposed by the author. The algebra has solved an essential theoretical barrier in the residue number system and has enabled one to pursue additive operations in the residue number system to their full extent, overcoming such difficulties as restrictions on the sign or magnitude of numbers in the system. In this paper, basic theorems in the algebra are introduced first, and then, based on the theorems, table look-up oriented solutions for hardware overflow checking, sign detection, and floating-point additive operations are given. The theorems expound the behavior of a quantity treated as a veiled mysterious function in the literature. To the best knowledge of the author, hardware overflow-checking schemes and floatingpoint additive operations in the residue number system have never been reported elsewhere. So far, the upper limit of the magnitude of numbers in the system ever discussed has been the one that is theory-limited, and floating-point operations in the residue number system have never been discussed.