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Showing papers in "IEEE Transactions on Computers in 1969"


Journal ArticleDOI
TL;DR: An algorithm for the analysis of multivariate data is presented along with some experimental results that is based upon a point mapping of N L-dimensional vectors from the L-space to a lower-dimensional space such that the inherent data "structure" is approximately preserved.
Abstract: An algorithm for the analysis of multivariate data is presented along with some experimental results. The algorithm is based upon a point mapping of N L-dimensional vectors from the L-space to a lower-dimensional space such that the inherent data "structure" is approximately preserved.

3,460 citations


Journal ArticleDOI
TL;DR: The purpose of this paper is to discuss the relative merits of square and hexagonal module arrays, to propose an operational symbolism for the various basic hexagonal modular transformations which may be performed by these comupters, to illustrate some logical circuit implementation, and to describe some elementary applications.
Abstract: The concept of the two-dimensional (2-D) parallel computer with square module arrays was first introduced by Unger. It is the purpose of this paper to discuss the relative merits of square and hexagonal module arrays, to propose an operational symbolism for the various basic hexagonal modular transformations which may be performed by these comupters, to illustrate some logical circuit implementation, and to describe a few elementary applications.

334 citations


Journal ArticleDOI
TL;DR: In this paper, a model for allocating information files required in common by several computers is developed for allocation of information files in a distributed manner, which considers storage cost, transmission cost, file lengths, and request rates, as well as updating rates of files.
Abstract: A model is developed for allocating information files required in common by several computers The model considers storage cost, transmission cost, file lengths, and request rates, as well as updating rates of files, the maximum allowable expected access times to files at each computer, and the storage capacity of each computer The criterion of optimality is minimal overall operating costs (storage and transmission) The model is formulated into a nonlinear integer zero-one programming problem, which may be reduced to a linear zero-one programming problem A simple example is given to illustrate the model

319 citations


Journal ArticleDOI
TL;DR: As a direct consequence of large-scale integration, many advantages in the design, fabrication, testing, and use of digital circuitry can be achieved if the circuits can be arranged in a two-dimensional iterative, or cellular, array of identical elementary networks, or cells.
Abstract: As a direct consequence of large-scale integration, many advantages in the design, fabrication, testing, and use of digital circuitry can be achieved if the circuits can be arranged in a two-dimensional iterative, or cellular, array of identical elementary networks, or cells. When a small amount of storage is included in each cell, the same array may be regarded either as a logically enhanced memory array, or as a logic array whose elementary gates and connections can be "programmed" to realize a desired logical behavior.

210 citations


Journal ArticleDOI
S. N. Cole1
TL;DR: An n-dimensional iterative array of finite-state machines is formally introduced as a real-time tape acceptor and the computational characteristics of iterative arrays are illuminated by establishing several results concerning the sets of tapes that they recognize.
Abstract: An n-dimensional iterative array of finite-state machines is formally introduced as a real-time tape acceptor. The computational characteristics of iterative arrays are illuminated by establishing several results concerning the sets of tapes that they recognize. Intercommunication between machines in an array is characterized by specifying a stencil for the array. The computing capability of the array is preserved even if its stencil is reduced to a simple form in which machines communicate only with their nearest neighbors. An increase of computing speed by a constant factor k is defined by encoding k-length blocks of the input tapes, which reduces the lengths of the tapes by 1/k; the time available for computation is correspondingly reduced since the computation must be real time. The computation speed of iterative arrays can be increased by any constant factor k. Two examples of one-dimensional arrays are provided. The first accepts the set of palindromes; the second accepts the set of all tapes of the form ττ (for any tape τ). The latter set of tapes is not a context-free language; therefore, the sets of tapes accepted by iterative arrays are not all contained in the class of context-free languages. Conversely, the class of context-free languages is not contained in the class of sets of tapes accepted by iterative arrays. The sets of tapes accepted by iterative arrays are closed under the operations: union, intersection, and complement; therefore, they form a Boolean algebra. They are not closed under the reflection or concatenation-product operations.

185 citations


Journal ArticleDOI
TL;DR: An efficient Walsh transform computation algorithm is derived which is analogous to the Cooley-Tukey algorithm for the complex-exponential Fourier transform.
Abstract: The discrete, orthogonal Walsh functions can be generated by a multiplicative iteration equation. Using this iteration equation, an efficient Walsh transform computation algorithm is derived which is analogous to the Cooley-Tukey algorithm for the complex-exponential Fourier transform.

172 citations


Journal ArticleDOI
TL;DR: This work has considered the problem of finding an easily applied algorithm that will result in a network such that the maximum delay through the network is minimized.
Abstract: An important aspect of the packaging of digital networks is the allocation of logic gates to modules such that a predetermined objective function is minimized. In order to develop techniques for this partitioning of a logic network we have considered the following problem: Given an acyclic combinational network composed of various primitive blocks such as NOR gates, assume that a maximum of M gates can be "clustered" together into larger modules, and that a maximum of P pins can be accommodated in each larger module. Assume also that in a network composed of such larger modules, no delay is encountered on the interconnections linking two gates internal to a module and a delay of one time unit is encountered on interconnections linking two gates in different modules . Find an easily applied algorithm that will result in a network such that the maximum delay through the network is minimized.

132 citations


Journal ArticleDOI
TL;DR: This paper considers the static scheduling of computations for a system containing two indentical processors and a solution for the two-machine case with preemptive scheduling is presented.
Abstract: One of the important potentials of multiprocessor systems is the ability to speed the completion of a computation by concurrently processing independent portions of the job. In this paper we consider the static scheduling of computations for a system containing two indentical processors. The object is to complete the computation in the minimum amount of time. A computation is assumed to be specified as a partially ordered set of tasks and the execution time for each task. A solution for the two-machine case with preemptive scheduling is presented.

117 citations


Journal ArticleDOI
TL;DR: The algorithm gives an indication as to the effectiveness of various transgeneration units and hence can also be used in an interactive manner if so desired for the actual design of a classification structure.
Abstract: A nonparametric procedure is developed for determining a structure for multivariate, multiclass pattern classification. The resultant classifier is in the form of a layered machine which is composed of multithreshold elements. The basic algorithm determines partitions which are parallel hyperplanes orthogonal to the feature coordinate dimensions. Inherent in the procedure is the concept of a transgenerator unit used to establish new feature dimensions such that effective partitioning can be obtained. While the choice of which classes of transgeneration units to consider is ultimately up to the user, a number of such units are suggested herein. The algorithm gives an indication as to the effectiveness of various transgeneration units and hence can also be used in an interactive manner if so desired for the actual design of a classification structure.

112 citations


Journal ArticleDOI
TL;DR: Fuzzy logic deals with propositions which may be ascribed values between falsehood and truth subjectively in either a continuous or a discrete fashion.
Abstract: Fuzzy logic deals with propositions which may be ascribed values between falsehood and truth (0 and 1) subjectively in either a continuous or a discrete fashion. This is in contrast to ordinary logic (two-valued or k-valued logic) in which a given proposition is ascribed values objectively using either deterministic or probabilistic approaches.

108 citations


Journal ArticleDOI
TL;DR: This paper considers a special class of state assignments called SST assignments which were first derived by Liu and later extended by Tracey and shows how this bound can be substantially improved.
Abstract: In this paper we consider the problem of deriving upper bounds on the number of state variables required for an n-state universal asynchronous state assignment (i.e., a state assignment which is valid for any n-state asynchronous sequential function). We will consider a special class of state assignments called SST assignments which were first derived by Liu [1] and later extended by Tracey [2]. In these assignments all variables which must change in a given transition are allowed to change simultaneously without critical races. The best universal bound known so far has been developed by Liu and requires 2so-1 state variables, where S0 = [log2n], n being the number of states, and [x] being the least integer > x. We shall show how this bound can be substantially improved. We further show that, by generalizing the state assignment to allow multiple codings for states, the bounds can be still further improved.

Journal ArticleDOI
TL;DR: The use of completion detection necessitated by the assumption of unbounded gate delays also causes the circuits to stop operating for approximately half of all possible single faults, thus achieving a degree of self-checking.
Abstract: This paper considers the general problem of the synthesis of asynchronous combinational and sequential circuits based on the assumption that gate delays may be unbounded and that line delays are suitably constrained. Certain problems inherent to circuit realizations with unbounded gate delays are discussed and methods of solving them are proposed. Specific synthesis techniques are presented for both combinational and sequential circuits. The use of completion detection necessitated by the assumption of unbounded gate delays also causes the circuits to stop operating for approximately half of all possible single faults, thus achieving a degree of self-checking.

Journal ArticleDOI
TL;DR: The nonweighted version of the n-tuple method has been found to work better than the maximum likelihood weighted version, and to achieve about 93 percent successful recognition of unconstrained hand-printed numerals, but at the cost of about 42 million bits of storage.
Abstract: The n-tuple method of pattern recognition has been simulated on a somewhat larger and more comprehensive scale than previously reported. The nonweighted version has been found to work better than the maximum likelihood weighted version, and to achieve about 93 percent successful recognition of unconstrained hand-printed numerals, but at the cost of about 42 million bits of storage.

Journal ArticleDOI
T.D. Friedman, Sih-Chin Yang1
TL;DR: The ALERT system converts preliminary high-level descriptions of computers into logic by "compiling" the architecture of a proposed machine in a form of Iverson notation into Boolean equations.
Abstract: The ALERT system converts preliminary high-level descriptions of computers into logic. The input to ALERT depicts the architecture of a proposed machine in a form of Iverson notation. As output, the architecture is "compiled" into Boolean equations, which may then be converted into standard computer circuits.

Journal ArticleDOI
TL;DR: An algorithm is presented for calculating recognition error when applying pattern vectors to an optimum Bayes' classifier, where the pattern vectors are assumed to come from two classes whose populations have Gaussian statistics with unequal covariance matrices and arbitrary a priori probabilities.
Abstract: An algorithm is presented for calculating recognition error when applying pattern vectors to an optimum Bayes' classifier. The pattern vectors are assumed to come from two classes whose populations have Gaussian statistics with unequal covariance matrices and arbitrary a priori probabilities. The quadratic discriminant function associated with a Bayes' classifier is used as a one-dimensional random variable from which the probability of error is calculated, once the distribution of the discriminant function is obtained.

Journal ArticleDOI
TL;DR: Factoring techniques are incorporated in computer-oriented algorithms for the synthesis of fan-in limited NAND switching networks and tree networks with reduced gate count or levels of logic are sought.
Abstract: Factoring techniques are incorporated in computer-oriented algorithms for the synthesis of fan-in limited NAND switching networks. Tree networks with reduced gate count or levels of logic are sought. While example FORTRAN programs emphasize computer execution of the algorithms, they are also efficient for hand execution.

Journal ArticleDOI
TL;DR: A branch-and-bound algorithm is presented for the synthesis of multioutput, multilevel, cycle-free NAND networks to realize an arbitrary given set of partially or completely specified combinational switching functions.
Abstract: A branch-and-bound algorithm is presented for the synthesis of multioutput, multilevel, cycle-free NAND networks to realize an arbitrary given set of partially or completely specified combinational switching functions. In a programmed version of the algorithm, fan-in, fan-out, and level constraints may be specified. Cost may be specified as a nonnegative integer linear combination of gates and gate inputs. Further constraints and cost criteria are compatible with the algorithm. A first solution is constructed by a sequence of local decisions, and backtracking is executed to find improved solutions and to prove the optimality of the final solution.

Journal ArticleDOI
TL;DR: This paper defines a series of tasks that transform any DDL document to Boolean and next-state equations from which a system may be implemented.
Abstract: A digital system design language, DDL, has been described and shown to provide a concise yet precise means of specifying the organization and operation of digital systems, regardless of timing mode or hardware types, at various levels of detail [2]. This paper defines a series of tasks that transform any DDL document to Boolean and next-state equations from which a system may be implemented. Each task of the transformation produces another DDL description of a system which uses fewer features of the language.

Journal ArticleDOI
TL;DR: Recognition experiments have been performed on handprinted characters using a set of features which has not been applied previously to handprinting, and results on numeric samples compare favorably with those of other investigators despite the small dimensionality of the feature vector.
Abstract: Recognition experiments have been performed on handprinted characters using a set of features which has not been applied previously to handprinting. Glucksman's "characteristic loci" were utilized in experiments with the well-known Highleyman data, as well as samples generated at Stanford Research Institute and Honeywell. Two recognition algorithms were tested. Results on numeric samples compare favorably with those of other investigators despite the small dimensionality of the feature vector. On the constrained Honeywell samples, recognition rates exceeding 98 percent were achieved using the simpler algorithm. With alphabetic samples, some problems remain in resolving persistent ambiguities, and methods for attacking these problems are considered.

Journal ArticleDOI
TL;DR: This paper is an attempt to develop "minimization algorithms for cellular arrays" for arbitrary switching functions that minimize a set of design parameters like size of the arrays and complexity of the individual cells.
Abstract: A fundamental problem in "cellular logic" is to be able to "synthesize" "cellular arrays" for arbitrary switching functions that minimize a set of design parameters like size of the arrays and complexity of the individual cells and of the interconnection pattern on the cells. This paper is an attempt to develop "minimization algorithms for cellular arrays."

Journal ArticleDOI
TL;DR: A class of methods for pattern classification using a set of samples of a type directly derived from concepts related to superposition, and it is shown that smooth potential functions exist that will separate arbitrary sets of sample points.
Abstract: This paper discusses a class of methods for pattern classification using a set of samples They may also be used in reconstructing a probability density from samples The methods discussed are potential function methods of a type directly derived from concepts related to superposition The characteristics required of a potential function are examined, and it is shown that smooth potential functions exist that will separate arbitrary sets of sample points Ideas suggested by Specht in regard to polynomial potential functions are extended

Journal ArticleDOI
TL;DR: The addition algorithm, decimal adder with signed digit arithmetic p presented here was designed to establish that it is possible to form an additional algorithm for the adder so that it can be used to transform numbers written in a conventional decinal form into a signed digit form, and vice versa.
Abstract: Addition algorithm, decimal adder with signed digit arithmetic p presented here was designed to establish the following facts: the redundant representation of a decimal digit xi by a 5-bit binary number Xi=3xi leads to a logical design of extreme simplicty; it is possible to form an additional algorithm for the adder so that it can be used to transform numbers written in a conventional decinal form into a signed digit form, and vice versa.

Journal ArticleDOI
TL;DR: Simulation of digital designs of digital logic designer's tasks, one of the ever-increasing trend to relieve man of time consuming menial tasks via automation, is the topic of this paper.
Abstract: In the ever-increasing trend to relieve man of time consuming menial tasks via automation, the digital logic designer's tasks have come under study. Various phases of this work are now being performed by computers. One of these phases, simulation of digital designs, is the topic of this paper.

Journal ArticleDOI
TL;DR: It is shown that under rather general conditions an explicit, closed formula for the sign function can be obtained and in a special case, when one of the moduli is 2, the signfunction becomes an EXCLUSIVE-OR function.
Abstract: This paper is concerned with the sign detection problem in residue number systems. The proposed solution is applicable only to nonredundant systems. It is shown that under rather general conditions an explicit, closed formula for the sign function can be obtained. In a special case, when one of the moduli is 2, the sign function becomes an EXCLUSIVE-OR function. A sign detection algorithm is proposed and methods of implementing the algorithm are presented.

Journal ArticleDOI
TL;DR: Methods of functional approximation for the computer solution of initial value partial differential equation problems provide a device by which these solutions can be approximated by those ofInitial value problems in sets of ordinary differential equations.
Abstract: Methods of functional approximation for the computer solution of initial value partial differential equation problems provide a device by which these solutions can be approximated by those of initial value problems in sets of ordinary differential equations. A number of ways to achieve this have been suggested, some of them general, some of them utilizing specific properties of the equations at hand. What all these methods have in common is the fact that the solution u(x, t) of a partial differential equation in space x and time t is approximated by a function u*(a1(t), a2(t), . . ., aN(t)), where the dependence upon x is prescribed. In most applications, u* is linear in the ai(t), i.e., u*= =ai(t)fi(x). The ai(t) satisfy a set of ordinary differential equations obtained as the result of the approximation process. This system of ordinary differential equations is then integrated by classical analog or digital computer methods.

Journal ArticleDOI
TL;DR: A small, but fast, associative memory can be used in a "look-aside" manner to improve the overall memory performance of a computer.
Abstract: A small, but fast, associative memory can be used in a "look-aside" manner to improve the overall memory performance of a computer. For a 128-cell 100-ns associate memory working with a 1-us main memory, the effective memory cycle time is reduced to between 350-to 400-ns.

Journal ArticleDOI
TL;DR: This paper analyzes the performance, for a particular strategy, of a head-per-track type auxiliary storage system in a real-time environment and obtains an approximate stationary distribution for the waiting time of a file access request in the system.
Abstract: This paper analyzes the performance, for a particular strategy, of a head-per-track type auxiliary storage system in a real-time environment. The prototype system of either fixed-head disks or drums incorporates a hardware queuer. This device attempts to always select first that request for a data transfer which will incur the shortest rotational latency relative to all other possible waiting file access requests. The queueing analysis is concerned with the tradeoff which is experienced in practice between throughput of a stochastic service device and the response time for each service request. An exact analysis of the system is shown to be totally unmanageable. Therefore, the approach is to estimate the results via physical arguments. We obtain an approximate stationary distribution for the waiting time of a file access request in the system.

Journal ArticleDOI
TL;DR: This paper discusses essential difficulties in calculating mean path lengths on a directed graph model of computations and efficient approximations to mean processing time (mean path length) of programs in such an environment are given.
Abstract: This paper discusses essential difficulties in calculating mean path lengths on a directed graph model of computations. This study was part of a larger study of a priori scheduling of computer programs in a parallel processing environment. Efficient approximations to mean processing time (mean path length) of programs in such an environment are given.

Journal ArticleDOI
TL;DR: This paper describes the design of the processing element (PE) of I IV, a parallel processing computer consisting of 256 PE's, each with an associated 2048 word memory.
Abstract: This paper describes the design of the processing element (PE) of I IV, a parallel processing computer consisting of 256 PE's, each with an associated 2048 word memory. Each PE-memory combination with its data-dependent controls is a computer in itself, devoid of those controls common to all PE-memory combinations, such as instruction decoding, instruction look-ahead, etc.

Journal ArticleDOI
Jr. K.S. Menger1
TL;DR: The transform presented in this paper applies to functions which describe logic network behavior, and both form and development of this transform pair resembles the Fourier transform in harmonic analysis.
Abstract: The transform presented in this paper applies to functions which describe logic network behavior. Given a function G defined over a finite domain, it is shown that G(u) = Et F(t)ut for each element u in the domain, where finite-field arithmetic is assumed. Here, function F is the transform of G, and it is shown that F(t) = Eu G(u)(-u)-t for each integer t in a finite set. Both form and development of this transform pair resembles the Fourier transform in harmonic analysis.