Showing papers in "IEEE Transactions on Computers in 1975"
TL;DR: This paper discusses the design of a primary memory system for an array processor which allows parallel, conflict-free access to various slices of data, and subsequent alignment of these data for processing, and a network based on Stone's shuffle-exchange operation is presented.
Abstract: This paper discusses the design of a primary memory system for an array processor which allows parallel, conflict-free access to various slices of data (e.g., rows, columns, diagonals, etc.), and subsequent alignment of these data for processing. Memory access requirements for an array processor are discussed in general terms and a set of common requirements are defined. The ability to meet these requirements is shown to depend on the number of independent memory units and on the mapping of the data in these memories. Next, the need to align these data for processing is demonstrated and various alignment requirements are defined. Hardware which can perform this alignment function is discussed, e.g., permutation, indexing, switching or sorting networks, and a network (the omega network) based on Stone's shuffle-exchange operation [1] is presented. Construction of this network is described and many of its useful properties are proven. Finally, as an example of these ideas, an array processor is shown which allows conflict-free access and alignment of rows, columns, diagonals, backward diagonals, and square blocks in row or column major order, as well as certain other special operations.
1,210 citations
TL;DR: The method of branch and bound is implemented in the present algorithm to facilitate rapid calculation of the k-nearest neighbors, by eliminating the necesssity of calculating many distances.
Abstract: Computation of the k-nearest neighbors generally requires a large number of expensive distance computations. The method of branch and bound is implemented in the present algorithm to facilitate rapid calculation of the k-nearest neighbors, by eliminating the necesssity of calculating many distances. Experimental results demonstrate the efficiency of the algorithm. Typically, an average of only 61 distance computations were made to find the nearest neighbor of a test sample among 1000 design samples.
776 citations
TL;DR: In this correspondence two methods are given for calculating the probability that the output of a general combinational network is 1 given the probabilities for each input being 1.
Abstract: In this correspondence two methods are given for calculating the probability that the output of a general combinational network is 1 given the probabilities for each input being 1. We define the notions of the probability of a signal and signal independence. Then several proofs are given to show the relationship between Boolean operations and algebraic operations upon probabilities. As a result of these, two simple algorithms are presented for calculating output probabilities. An example of the usefulness of these results is given with respect to the generation of tests for the purpose of fault detection.
433 citations
TL;DR: An algorithm that finds the k nearest neighbors of a point, from a sample of size N in a d-dimensional space, with an expected number of distance calculations is described, its properties examined, and the validity of the estimate verified with simulated data.
Abstract: An algorithm that finds the k nearest neighbors of a point, from a sample of size N in a d-dimensional space, with an expected number of distance calculations is described, its properties examined, and the validity of the estimate verified with simulated data.
430 citations
TL;DR: A new method for the extraction of features in a two-class pattern recognition problem is derived that is based entirely upon discrimination or separability as opposed to the more common approach of fitting.
Abstract: A new method for the extraction of features in a two-class pattern recognition problem is derived. The main advantage is that the method for selecting features is based entirely upon discrimination or separability as opposed to the more common approach of fitting. The classical example of fitting is the use of the eigenvectors of the lumped covariance matrix corresponding to the largest eigenvalues. In an analogous manner, the new technique selects discriminant vectors (or features) corresponding to the largest "discrim-values." The new method is compared to some of the more popular alternative techniques via both data-dependent and mathematical examples. In addition, a recursive method for obtaining the discriminant vectors is given.
428 citations
TL;DR: A signed logarithmic number system, which is capable of representing negative as well as positive numbers is described, and it is shown that negative numbers can be represented in the sign/logarithm number system.
Abstract: A signed logarithmic number system, which is capable of representing negative as well as positive numbers is described. A number is represented in the sign/logarithm number system by a sign bit and the logarithm of the absolute value of the number (scaled to avoid negative logarithms).
273 citations
TL;DR: This correspondence describes an improved method of detecting "angles" on a digital curve that is similar to, but gives better results than, a method described in an earlier paper.
Abstract: This correspondence describes an improved method of detecting "angles"—i.e., maxima of the difference between successive nonoverlapping average slopes—on a digital curve. The method is similar to, but gives better results than, a method described in an earlier paper.
273 citations
TL;DR: Several variations of the single fault detection problem for combinational logic circuits are looked at and it is shown that deciding whether single faults are detectable by input-output (I/O) experiments is polynomially complete, i.e., there is a polynomial time algorithm to decide if they are detectable.
Abstract: We look at several variations of the single fault detection problem for combinational logic circuits and show that deciding whether single faults are detectable by input-output (I/O) experiments is polynomially complete, i.e., there is a polynomial time algorithm to decide if these single faults are detectable if and only if there is a polynomial time algorithm for problems such as the traveling salesman problem, knapsack problem, etc.
265 citations
TL;DR: An algorithm is described for generating fuzzy partitions which extremize a fuzzy extension of the k-means squared-error criterion function on finite data sets X, and the behavior of the algorithm is compared with that of the ordinary ISODATA clustering process and the maximum likelihood method.
Abstract: An algorithm is described for generating fuzzy partitions which extremize a fuzzy extension of the k-means squared-error criterion function on finite data sets X. It is shown how this algorithm may be applied to the problem of estimating the parameters (a priori probabilities, means, and covariances) of mixture of multivariate normal densities, given a finite sample X drawn from the mixture. The behavior of the algorithm is compared with that of the ordinary ISODATA clustering process and the maximum likelihood method, for a specific bivariate mixture.
236 citations
TL;DR: This paper presents Markov chain models for analyzing the extent of memory interference in multiprocessor systems with a crosspoint switch for processor-memory communication and the results predicted are compared with some simulation results and some actual measurements on C.mmp, a multipROcessor system being built at Carnegie-Mellon University.
Abstract: This paper presents Markov chain models for analyzing the extent of memory interference in multiprocessor systems with a crosspoint switch for processor-memory communication. Processor behavior is simplified to an ordered sequence of a memory request followed by a certain amount of processing time. The results predicted by the model are compared with some simulation results and some actual measurements on C.mmp, a multiprocessor system being built at Carnegie-Mellon University.
227 citations
TL;DR: A clustering algorithm based on the branch and bound method of combinatorial optimization determines the globally optimum classification and is computationally efficient.
Abstract: The problem of clustering N objects into M classes may be viewed as a combinatorial optimization algorithm. In the literature on clustering, iterative hill-climbing techniques are used to find a locally optimum classification. In this paper, we develop a clustering algorithm based on the branch and bound method of combinatorial optimization. This algorithm determines the globally optimum classification and is computationally efficient
TL;DR: The methodology is a model of the test data generation process and can be used to characterize the basic problems of testData generation and build an automatic test data Generation system.
Abstract: A methodology for generating program test data is described. The methodology is a model of the test data generation process and can be used to characterize the basic problems of test data generation. It is well defined and can be used to build an automatic test data generation system.
TL;DR: A technique is described which allows overlapping images to be combined into a photomosaic in which the visual impact of the introduced seam has been minimized.
Abstract: A technique is described which allows overlapping images to be combined into a photomosaic in which the visual impact of the introduced seam. has been minimized. Images which have been brought into geometric and gray scale register are combined on a line-by-line basis by choosing a "best" seam point for each line. The resulting artificial edge at the seam point is then locally smoothed.
IBM1
TL;DR: This paper presents a technique for generating statistically random sequences to test complex logic circuits and several techniques for assigning these weights and for varying them are discussed on the basis of the primary algorithm.
Abstract: A heuristic method for generating large-scale integration (LSI) test patterns is described. In particular, this paper presents a technique for generating statistically random sequences to test complex logic circuits. The algorithms used to obtain a set of tests by means of weighted logic signal variations are included. Several techniques for assigning these weights and for varying them are discussed on the basis of the primary algorithm. Also described is a means of obtaining a minimal number of test patterns. This approach has proved successful in obtaining fault-detecting patterns.
TL;DR: A technique for the quantitative evaluation of edge detection schemes is used to assess the performance of three such schemes using a specially-generated set of images containing noise to relate the quantitative comparison to real-life imagery.
Abstract: A technique for the quantitative evaluation of edge detection schemes is presented. It is used to assess the performance of three such schemes using a specially-generated set of images containing noise. The ability of human subjects to distinguish the edges in the presence of noise is also measured and compared with that of the edge detection schemes. The edge detection schemes are used on a high-resolution satellite photograph with varying degrees of noise added in order to relate the quantitative comparison to real-life imagery.
TL;DR: This correspondence shows how this method can be used to detect any given curve in a specific orientation and can be easily implemented and efficiently implemented in a parallel machine.
Abstract: In Hough [1], Duda and Hart [2], and Griffith [3] procedures were proposed for detecting lines in pictures and in [2] Duda and Hart extended their method for more general algebraic curve, fitting. This correspondence shows how this method can be used to detect any given curve in a specific orientation. The procedure presented here con be easily implemented and can be efficiently implemented in a parallel machine.
TL;DR: A simplified proof of a modification of Booth's multiplication algorithm by MacSorley to a form which examines three multiplier bits at a time is presented.
Abstract: A simplified proof of a modification of Booth's multiplication algorithm by MacSorley to a form which examines three multiplier bits at a time is presented. In comparison with the original Booth's algorithm, which examines two bits at a time, the modified algorithm requires half the nutmber of iterations at the cost of somewhat increased complexity for each iteration.
TL;DR: A technique for decomposition of polygons into simpler components is described and illustrated with applications in the analysis of handwritten Chinese characters and chromosomes.
Abstract: A technique for decomposition of polygons into simpler components is described and illustrated with applications in the analysis of handwritten Chinese characters and chromosomes. Polygonal approximations of such objects are obtained by methods described in the literature and then parts of their concave angles are examined recursively for separating convex or other simple shape components. Further decomposition of the latter is possible. The final result can be expressed as a labeled graph and processed further through the introduction of either fuzzy predicates or syntactic pattern recognition techniques.
TL;DR: The Navy funded Advanced Avionics Fault Isolation System (AAFIS) concept utilizes BIT logic for cost-effective fault detection and fault isolation to a digital subsystem and to the faulty module therein.
Abstract: Advances in integrated circuit technology are decreasing acquisition cost per function of digital hardware while system software costs are increasing. The hardware advances allow practical implementation of more sophisticated and complex systems which have fewer components, but which may present severe test and maintenance problems due to their complexity. As a result, the use of built-in test (BIT) hardware in place of software becomes increasingly attractive. The Navy funded Advanced Avionics Fault Isolation System (AAFIS) concept utilizes BIT logic for cost-effective fault detection and fault isolation to a digital subsystem and to the faulty module therein. Added logic, available at low cost with advanced microelectronics, is used to perform test pattern generation in each subsystem and to code over the test sequence the outputs and test points on each subsystem module. The coded test response is compared to a predetermined constant. The OR of resulting module pass-fail signals indicates subsystem faults, while identification of a module fail signal provides isolation to a faulty module. Practical coding techniques are presented, with tradeoff of speed, test effectiveness and logic requirements for each. BIT logic design and simulation results verify high fault detection and moderate added logic for BIT.
TL;DR: The schedules produced by a simple critical path priority method are shown to be near optimal for randomly generated computation graphs.
Abstract: The problem of scheduling tasks on a system of independent identical processors is discussed and the performance of a suboptimal method is evaluated. The computation is modeled by an acyclic directed graph G(T,<), where node set T represents the set of tasks to be completed and edge set < defines the precedence between tasks. The objective is to minimize the finishing time of the computation graph. Known theoretical results are reviewed and a general branch-and-bound algorithm for finding optimal solutions is presented. The schedules produced by a simple critical path priority method are shown to be near optimal for randomly generated computation graphs.
IBM1
TL;DR: The software and hardware architecture of a system designed as a research tool for experiments on programming the computer controlled assembly of mechanical objects and the application of the system to sample assemblies is discussed.
Abstract: This paper describes the software and hardware architecture of a system designed as a research tool for experiments on programming the computer controlled assembly of mechanical objects. The software consists of a real-time control level and a background level in which an on-line interpreter permits interactive programming. The hardware consists of a manipulator with sensory feedback coupled to an IBM System/7. Additional facilities are available through a link to an IBM System/370 Model 145. The application of the system to sample assemblies is also discussed.
TL;DR: A systematic anaylsis is given of the topological changes that can occur when overlapping figures move together or apart and a computer program based on these results is described, and experimental results are presented.
Abstract: A general mathematical model is developed as an idealization of the problem of determining cloud motions from satellite pictures. The model consists of superimposed planes of rigid moving polygons. The problem is to determine from a sequence of scenes the linear and angular velocities of the figures, and to decompose the scene into its component figures. Study of the model reveals a number of fundamental relations that form the basis for an analysis program. In particular, a systematic anaylsis is given of the topological changes that can occur when overlapping figures move together or apart. A computer program based on these results is described, and experimental results are presented.
TL;DR: Some formal models for pattern-sensitive faults (PSF's) in random-access memories are presented and an efficient procedure for constructing a checking sequence for the memory is presented.
Abstract: Some formal models for pattern-sensitive faults (PSF's) in random-access memories are presented. The problem of detecting unrestricted PSF's is that of constructing a checking sequence for the memory. An efficient procedure for constructing such a checking sequence is presented. A local PSF is defined as a PSF where the faulty behavior of a memory cell C i depends on a fixed group of cells called the neighborhood of C i . Neighborhoods are divided into two classes, open and closed. Test generation methods are described for local PSF's defined on both open and closed neighborhoods. The detection of PSF's when only one memory cell is faulty (single PSF's) is also discussed.
TL;DR: A probabilistic treatment of general combinational networks has been developed and algorithms to calculate the probability of the output of a logic circuit being 1 and simplifications to the algorithm result when sets of input probabilities are given the same value.
Abstract: A probabilistic treatment of general combinational networks has been developed. Using the notions of the probability of a signal and signal independence, algorithms have been presented to calculate the probability of the output of a logic circuit being 1. Simplifications to the algorithm result when sets of input probabilities are given the same value, and this process called bundling is described in the paper. Finally, a series of examples illustrate the application of the probabilistic approach to the analysis of faulty logic circuits.
TL;DR: By a simple transformation, the results can also be applied to the solution of any triangular linear system of equations Ax̄ = b̄, and the computer need only perform one type of operation at each time step.
Abstract: We give new time and processor bounds for the parallel evaluation of linear recurrence systems. Such systems may be represented as x =c + Ax where A is an n X n strictly lower triangular matrix and c is a constant column vector. We show that O og 2 2n) time steps and n3/ 8 + 0O2) processors are sufficient. We also show that mth order linear recurrences, i. e., where A has a bandwidth of m, can be computed within O(log 2 mlog 2 n) time steps with at most 3m2n/4 + O(mn) processors. In all cases, our bounds on time and processors are improvements on previous results, and the computer need only perform one type of operation at each time step (SIMD operation). By a simple transformation, the results can also be applied to the solution of any triangular linear system of equations Ax = b.
TL;DR: The result of applying the Rademacher-Walsh transform domain classification to Boolean functions of up to fourth order indicates that threshold functions play an important part in the composition of Boolean functions.
Abstract: Five operations are defined in the Rademacher-Walsh transform domain. It is shown that these operations allow Boolean functions to be classified in a very concise way. The result of applying this classification to Boolean functions of up to fourth order indicates that threshold functions play an important part in the composition of Boolean functions. A synthesis method is developed for the synthesis of any Boolean function using, as a basic element, an "optimized universal threshold logic gate." This gate overcomes the analog threshold tolerancing problems encountered in other threshold gate designs and is readily fabricated in an integrated circuit form. The use of this gate in logic design is expected to provide a considerable cost-saving over conventional methods.
TL;DR: Determination of the detectability and diagnosability of a digital system containing at most t faulty system components is considered and results are presented which permit the determination of t-fault detectable and t-Fault diagnosable with repair for the system.
Abstract: Determination of the detectability and diagnosability of a digital system containing at most t faulty system components is considered. The model employed is to an extent independent of the means used to implement diagnostic procedures, i.e., whether the tests are accomplished via hardware, software, or combinations thereof. A parameter, called the closure index, is defined which characterizes the capability for executing valid tests in the presence of faults. The closure index can be thought of as the size of the smallest potentially undetectable multiple-fault in the system as modeled. On the basis of this parameter, results are presented which permit the determination of t-fault detectability and t-fault diagnosability with repair for the system. Examples are presented to illustrate the application of the model for systems close to those encountered in actual practice.
TL;DR: It is shown that to detect t faults, t ≥ 1, in a network realizing an arbitrary n-variable logic function only tests need be applied ([x] is the integer part of x) and that these tests are independent of the function being realized.
Abstract: Fault detecting test sets to detect multiple stuck-at-faults (s-a-faults) in certain networks, realizing Reed-Muller(RM) canonic expressions called RM canonic (RMC) networks, are given. It is shown that to detect t faults, t ≥ 1, in a network realizing an arbitrary n-variable logic function only tests need be applied ([x] is the integer part of x) and that these tests are independent of the function being realized.
TL;DR: The interaction problem between asynchronous logic elements is formulated with emphasis on the synchronizer and the principle result is to predict, in a probabilistic manner, the time necessary to move from the metastable point to one of the stable boundaries.
Abstract: The interaction problem between asynchronous logic elements is formulated with emphasis on the synchronizer A detailed analytic treatment of the binary flip-flop action in the metastable region is presented The principle result is to predict, in a probabilistic manner, the time necessary to move from the metastable point to one of the stable boundaries The effects of circuit time constant and circuit noise are discussed in detail Theoretical results are correlated with laboratory measurements and suggestions for acceptable probability of error performance are given
TL;DR: Formulas for the detection probability and the number of random input patterns required to complete the test generation with a high probability are obtained for an irredundant fan-out-free combinational network tree consisting of identical n-input NAND gates.
Abstract: In this paper the random test generation method for large logic circuits is analyzed. Formulas for the detection probability and the number of random input patterns required to complete the test generation with a high probability are obtained for an irredundant fan-out-free combinational network tree consisting of identical n-input NAND gates. The quantitative estimates for the number of random input patterns required for test generation appear to depend upon the number of levels in the circuit and the fan-ins of the gates. Experimental results for actual computer logic circuits are given and show the validity of the approach.