Showing papers in "IEEE Transactions on Device and Materials Reliability in 2008"

Reliability of GaN High-Electron-Mobility Transistors: State of the Art and Perspectives

Abstract: Failure modes and mechanisms of AlGaN/GaN high-electron-mobility transistors are reviewed. Data from three de-accelerated tests are presented, which demonstrate a close correlation between failure modes and bias point. Maximum degradation was found in "semi-on" conditions, close to the maximum of hot-electron generation which was detected with the aid of electroluminescence (EL) measurements. This suggests a contribution of hot-electron effects to device degradation, at least at moderate drain bias (VDS 30-50 V), new failure mechanisms are triggered, which induce an increase of gate leakage current. The latter is possibly related with the inverse piezoelectric effect leading to defect generation due to strain relaxation, and/or to localized permanent breakdown of the AlGaN barrier layer. Results are compared with literature data throughout the text.

A Review on the Reliability of GaN-Based LEDs

Abstract: We review the degradation mechanisms that limit the reliability of GaN-based light-emitting diodes (LEDs). We propose a set of specific experiments, which is aimed at separately analyzing the degradation of the properties of the active layer, of the ohmic contacts and of the package/phosphor system. In particular, we show the following: 1) low-current density stress can determine the degradation of the active layer of the devices, implying modifications of the charge/deep level distribution with subsequent increase of the nonradiative recombination components; 2) high-temperature storage can significantly affect the properties of the ohmic contacts and semiconductor layer at the p-side of the devices, thus determining emission crowding and subsequent optical power decrease; and 3) high-temperature stress can significantly limit the optical properties of the package of high-power LEDs for lighting applications.

Accelerated Life Test of High Brightness Light Emitting Diodes

Abstract: Short-term accelerated life test activity on high brightness light emitting diodes is reported. Two families of 1-W light-emitting diodes (LEDs) from different manufacturers were submitted to distinct stress conditions: high temperature storage without bias and high dc current test. During aging, degradation mechanisms like light output decay and electrical property worsening were detected. In particular, the degradation in light efficiency induced by thermal storage was found to follow an exponential law, and the activation energy of the process was extrapolated. Aged devices exhibited a modification of the package epoxy color from white to brown. The instability of the package contributes to the overall degradation in terms of optical and spectral properties. In addition, an increase in thermal resistance was detected on one family of LEDs. This increase induces higher junction temperature levels during operative conditions. In order to correlate the degradation mechanisms and kinetics found during thermal stress, a high dc current stress was performed. Results from this comparative analysis showed similar behavior, implying that the degradation process of dc current aged devices is thermal activated due to high temperatures reached by the junction during stress. Finally, the different effects of the stress on two families of LEDs were taken into account in order to identify the impact of aging on device structure.

Compact Modeling of MOSFET Wearout Mechanisms for Circuit-Reliability Simulation

Abstract: The integration density of state-of-the-art electronic systems is limited by the reliability of the manufactured integrated circuits at a desired circuit density. Design rules, operating voltages, frequencies, and temperatures are precisely chosen to ensure correct product functional operation over its intended lifetime. Thus, in order to obtain the overall performance and functionality bounded by various design and manufacturing constraints, the integrated circuit reliability must be modeled and analyzed at the very beginning of design stages. This paper reviews some of the most important intrinsic wearout mechanisms of MOSFETs (including hot-carrier injection, time-dependent dielectric breakdown, and negative bias temperature instability) and introduces new accelerated-lifetime and SPICE compact models of these wearout mechanisms. Based on these circuit-aging models, a new SPICE reliability simulation approach is proposed and demonstrated with a simplified SRAM design on a commercial 90-nm technology to help designers understand device-failure behaviors, predict circuit reliability, and improve product robustness.

Single Event Upsets in Deep-Submicrometer Technologies Due to Charge Sharing

Abstract: Circuit and 3D technology computer aided design mixed-mode simulations show that the single event upset vulnerability of 130- and 90-nm hardened latches to low linear energy transfer (LET) particles is due to charge sharing between multiple nodes as a result of a single ion strike. The low LET vulnerability of the hardened latches is verified experimentally.

Performance Degradation of High-Brightness Light Emitting Diodes Under DC and Pulsed Bias

Abstract: This paper presents the results of an experimental investigation of the performance of commercially available high-brightness light emitting diodes (HBLEDs). Three different families of white HBLEDs from three different manufacturers are considered. The main issues taken into account and reported in detail are the following: quality of the emitted light, impact of the driving strategy on the expected device lifetime, thermal management and related aging effects. The execution of a large number of accelerated stress tests reveals the weaknesses of the technology with respect to thermal degradation and the sensitivity of the device performance degradation to the adopted driving strategy. Furthermore, square-wave driving has been compared to conventional dc driving in terms of device performance and reliability. Comparison has been carried out for the same average current value of the driving waveforms. It has been found that square-wave driving can be an effective alternative to dc driving in terms of device efficiency only for high duty cycles. For low duty cycles, worse performance was detected due to the saturation of efficiency at high peak current levels. Reliability tests did not univocally indicate whether the use of pulsed bias can be more convenient than dc driving in terms of lumen maintenance. The three families of devices submitted to dc and pulsed stresses showed different behaviors, indicating that stress kinetics strongly depends on the LED technological structure and package thermal design.

Temperature-Dependent Characterization of AlGaN/GaN HEMTs: Thermal and Source/Drain Resistances

Abstract: This paper shows the application of simple dc techniques to the temperature-dependent characterization of AlGaN/ GaN HEMTs in terms of the following: 1) thermal resistance and 2) ohmic series resistance (at low drain bias). Despite their simplicity, these measurement techniques are shown to give valuable information about the device behavior over a wide range of ambient/channel temperatures. The experimental results are validated by comparison with independent measurements and numerical simulations.

Mechanisms of RF Current Collapse in AlGaN–GaN High Electron Mobility Transistors

Abstract: The physical mechanisms underlying RF current- collapse effects in AlGaN-GaN high-electron-mobility transistors are investigated by means of measurements and numerical device simulations. This paper suggests the following conditions: 1) both surface and buffer traps can contribute to RF current collapse through a similar physical mechanism involving capture and emission of electrons tunneling from the gate; 2) surface passivation strongly mitigates RF current collapse by reducing the surface electric field and inhibiting electron injection into traps; 3) for surface-trap densities lower than 9 x 1012 cm-2, surface-potential barriers in the 1-2-eV range can coexist with surface traps having much a shallower energy and, therefore, inducing RF current-collapse effects characterized by relatively short time constants.

Effect of BTI Degradation on Transistor Variability in Advanced Semiconductor Technologies

Abstract: The effect of PMOS transistor negative bias temperature instability (NBTI) on product performance is a key reliability concern. As technology scales and device dimensions shrink, the trend in the V T variability at both time zero and after NBTI aging increases. The time0 V T variability can be explained by the random nature of dopants, whereas the randomly generated defects in the gate oxide can account for the aging-induced device DeltaV T variability. This paper focuses on the bias temperature instability stress-induced device DeltaV T variability and the trend across several technology generations. The remarkable correlation of aging-induced DeltaV T variability to the gate oxide area suggests that the continued device geometry scaling will increase the aging-induced variability. For the first time, aging-induced DeltaV T variability was characterized on transistors fabricated with high-kappa gate dielectric that also showed similar dependence to the gate oxide area.

The Impact of Aging Effects and Manufacturing Variation on SRAM Soft-Error Rate

Abstract: This paper describes modeling and hardware results of how the soft-error rate (SER) of a 65-nm silicon-on-insulator SRAM memory cell changes over time, as semiconductor aging effects shift the SRAM cell behavior. This paper also describes how the SER changes in the presence of systematic and random manufacturing variation.

Understand NBTI Mechanism by Developing Novel Measurement Techniques

Abstract: Our recent investigations and understanding of the negative bias temperature instability (NBTI) degradation in p-MOSFETs with ultrathin SiON gate dielectric are reviewed. The progressive understanding of NBTI mechanism is mainly related to the novel measurement techniques we developed. We show in this paper the following: 1) For the conventional charge pumping and direct-current current-voltage interface trap measurement, the interface trap density Nit is underestimated due to the recovery during measurement delay. The existing Nit data should be reexamined; 2) an ultrafast pulsed I-V method [fast pulsed measurement (FPM)] is developed to measure DeltaVth with measurement time tM = 100 ns. It can be considered as free from recovery during measurement; 3) due to the degradation during the initial threshold voltage measurement, the existing slow on-the-fly (OTF) DeltaVth measurement distorts (overestimates) the slope and induces a kink at early stress time in the Log-Log curve of the time evolution of NBTI degradation. A fast OTF DeltaVth measurement method is developed to overcome this problem; 4) a novel OTF interface trap (OFIT) measurement method is developed which is free from interface trap recovery during measurement. The OFIT measurement provides the most reliable data to inspect the interface trap R-D model; 5) combining the OFIT and FPM measurements, we decompose the NBTI DeltaVth into two components: A slow DeltaVth it component contributed by with a slow recovery time longer than 50mus and a fast DeltaVth ox component contributed by DeltaVox with a broad spectrum of recovery time, including a component with very fast recovery time (100 ns); and 6) the dynamic degradation by DeltaVth it component is frequency-independent and can be measured by a dc method, whereas the dynamic degradation DeltaVth ox by component measured by FPM is increased by increasing frequency. The ten-year lifetime of the p-MOSFETs is mainly determined by the degradation of the DeltaVth it component.

A Temperature-Gradient-Induced Failure Mechanism in Metallization Under Fast Thermal Cycling

Abstract: In this paper, a novel mechanism is shown to cause the failure evolution in a metallization system under fast temperature cycle stress. The failure evolution is triggered by the lateral temperature distribution across the device, which causes an accumulating plastic deformation of the metallization. The root cause for the deformation emerges at the position of the maximum gradient in temperature.

Influence of Nitrogen on Negative Bias Temperature Instability in Ultrathin SiON

Abstract: Negative bias temperature instability (NBTI) and its recovery phenomenon in ultrathin silicon oxynitride (SiON2) films were investigated. To discuss the influence of nitrogen incorporation into silicon dioxide films, we used NO-nitrided SiON and plasma-nitrided SiON. As a result, it was found that the recovery for plasma-nitrided SiON is less marked than that for NO-nitrided SiON, although NBTI can be suppressed by plasma nitridation. It is also experimentally confirmed that hydrogen plays an important role in these phenomena. On the basis of these results, we proposed nitrogen-originated NBT degradation involving hydrogen at SiON/Si interface and hole trapping/detrapping. Furthermore, NBTI under ac stress was investigated. Not only NBTI was more suppressed under ac stress than under dc stress as already reported, but also, this behavior of dynamic NBTI is independent of nitrogen distribution in SiON.

Reliability of Printed Circuit Boards Processed Using No-Clean Flux Technology in Temperature–Humidity–Bias Conditions

Abstract: Printed circuit board (PCB) specimens containing three different IPC-B-25 test structures were exposed to temperature-humidity-bias conditions in order to evaluate the effects of no-clean flux chemistry, conductor spacing, voltage bias, and test environment on surface insulation resistance (SIR). Comb patterns on the PCBs were coated with a eutectic (63Sn/37Pb) solder applied by a hot air solder leveling and processed by using no-clean aqueous-based and rosin-based fluxes. The SIR failure rate with rosin-based no-clean flux was observed to be greater than that with aqueous-based no-clean flux. This was explained by the more corrosive nature of the flux residues and the larger concentration of hygroscopic weak organic acids in the rosin-based flux residues. A characteristic of the SIR failures for PCBs processed with rosin-based flux was a series of intermittent SIR drops, which could severely affect the reliability of electronic assemblies. It was hypothesized that flux residues combined with adsorbed moisture from the environment form an acidic medium, occasionally breaking through the tin oxide passivation layer on the electrodes. Penetration of the passivation layer combined with conductive flux residues bridging the electrodes caused the resistance to decrease, and rehealing of the passivation layer resulted in the intermittent behavior. Conductor spacing was observed to represent a factor in the electrochemical migration process that is independent of electric field. Since conductor spacings in electronic products continue to decrease, the experimental results support recommendations to replace 25-mil (0.64-mm) comb structures on industry standard test boards with those having smaller spacings, below 12.5 mil (0.32 mm), that accurately reflect the greater risk for SIR drops of today's higher density assemblies.

Photosensitivity Analysis of Gallium Nitride and Silicon Carbide Terahertz IMPATT Oscillators: Comparison of Theoretical Reliability and Study on Experimental Feasibility

Abstract: Reliability of terahertz-frequency (~1.0 THz) characteristics of wide-bandgap (WBG) wurtzite (Wz)-GaN- and 4H-SiC-based p++nn++-type single-drift-region (SDR) impact avalanche transit time (IMPATT) devices (normal and photoilluminated) is compared through a simulation scheme. The simulation experiment reveals that an RF power density of 3.37 times 1011 W middotm-2 (efficiency of 18.2%) at around 1.126 THz may be realized from the optimized unilluminated GaN IMPATT device, whereas the unilluminated 4H-SiC IMPATT device is expected to generate an RF power density of 1.35 times 1011 W middotm-2 (efficiency of 9%) at 1.05 THz. However, the parasitic series resistance reduces the maximum exploitable power density from the terahertz devices. Under optical illumination, additional photogenerated carriers are created in the devices, and these carriers change the admittance and negative resistance properties of the terahertz IMPATT diodes. The performance modulation of the terahertz devices is simulated, and the results are compared in this paper. Under external radiation, the operating frequencies of the GaN- and SiC-based diodes are found to shift upward by 6.0 and 40.0 GHz, respectively, with degradation of maximum output-power density level and device negative resistance. The extensive simulation experiments establish that, although the photosensitivity of the 4H-SiC-based IMPATT device is better than its GaN counterpart, the overall terahertz performance of the unilluminated GaN IMPATT device is far better than the 4H-SiC-based device, particularly in terms of output power and efficiency. The simulation results and the proposed experimental methodology presented here can be used for realizing optically tuned WBG IMPATT oscillators for terahertz communication.

Defect Generation in p-MOSFETs Under Negative-Bias Stress: An Experimental Perspective

Abstract: In this paper, a focused review is made of our previously reported (2002-2007) work on negative-bias temperature-instability (NBTI) measurement and analysis. Using suitable cross-reference to other published work, the impacts of stress condition, characterization technique, and gate-oxide process on measured NBTI parameters are reviewed. The large scatter of measured time, bias, and temperature dependencies of NBTI, which are observed in published literature, is carefully analyzed. A common framework for NBTI physical mechanism is suggested and discussed. Issues lacking proper understanding at present are also highlighted.

A Consistent Deep-Level Hole Trapping Model for Negative Bias Temperature Instability

Abstract: This paper addresses a fundamental question on the physics of negative bias temperature instability (NBTI). Besides interface states, is oxide trapped charge (i.e., trapped holes) generated concurrently by NBTI stress? The discussion is made against a backdrop of critical questions, evolving from recent studies, which challenge the validity of the charge pumping method used commonly for quantifying and differentiating interface states from an oxide trapped charge. An objective and systematic analysis of dc current-voltage data reveals a broad energy distribution of stress induced positive trap states. Relative difference in the energy levels of these positive trap states determines their role as either interface states (trap states in the Si bandgap) or oxide trapped charge (deep-level trap states near and above the Si conduction band edge). This framework satisfactorily explains many electrical characteristics, known hitherto, of an NBTI-stressed p-MOSFET without specific regard to the exact origin of the traps. However, distinct relaxation characteristics of deep-level positive trap states, as compared to those of the interface states, imply a fundamental difference in the origin of these traps. Under positive gate biasing, the density of interface states is unchanged, but the density of deep-level positive trap states is significantly reduced. Electrical behavior of the deep-level positive trap states is shown to conform to that of oxide traps, implying that these trap states arise from hole trapping. However, a detailed temperature dependence study indicates that the mechanism, which is responsible for the generation of a substantial portion of the positive trap charge, has a very small activation energy (0.02 eV). This observation suggests that the generation of a significant portion of the positive trap charge is neither due to the breaking of bonds nor is rate-limited by matter transport. A possible mechanism involving a negative-field-induced loss of electronic charge from nitrogen donors is proposed.

Dispersive Transport and Negative Bias Temperature Instability: Boundary Conditions, Initial Conditions, and Transport Models

Abstract: Negative bias temperature instability (NBTI) has evolved into one of the most serious reliability concerns for highly scaled pMOSFETs. It is most commonly interpreted by some form of reaction-diffusion model, which assumes that some hydrogen species is first released from previously passivated interface defects and then diffuses into the oxide. It has been argued, however, that hydrogen motion in the oxide is trap-controlled, resulting in dispersive transport behavior. This defect-controlled transport modifies the characteristic exponent in the power law that describes the threshold-voltage shift. So far, a number of NBTI models based on dispersive transport have been published. Interestingly, although seemingly based on similar physical assumptions, these models result in different predictions. Most notably, both an increase and a decrease in the power-law time exponent with increasing dispersion have been reported. Also, different functional dependences on the dispersion parameter have been given in addition to differences in the prefactors and the saturation behavior. We clarify these discrepancies by identifying the boundary and initial conditions which couple the transport equations to the electro-chemical reaction at the interface as the crucial component. We proceed by deriving a generalized reaction (dispersive) diffusion formalism and provide the missing link between the various published models by demonstrating how each of them can be derived from this generalized model.

Time-Dependent Dielectric Breakdown of 4H-SiC/ $ \hbox{SiO}_{2}$ MOS Capacitors

Abstract: Time-dependent dielectric breakdown (TDDB) is one of the major issues concerning long-range reliability of dielectric layers in SiC-based high-power devices. Despite the extensive research on TDDB of SiO2 layers on Si, there is a lack of high-quality statistical TDDB data of SiO2 layers on SiC. This paper presents comprehensive TDDB data of 4H-SiC capacitors with a SiO2 gate insulator collected over a wide range of electric fields and temperatures. The results show that at low fields, the electric field acceleration parameter is between 2.07 and 3.22 cm/MV. At fields higher than 8.5 MV/cm, the electric field acceleration parameter is about 4.6 cm/MV, indicating a different failure mechanism under high electric field stress. Thus, lifetime extrapolation must be based on failure data collected below 8.5 MV/cm. Temperature acceleration follows the Arrhenius model with activation energy of about 1 eV, similar to thick SiO2 layers on Si. Based on these experimental data, we propose an accurate model for lifetime assessment of 4H-SiC MOS devices considering electric field and temperature acceleration, area, and failure rate percentile scaling. It is also demonstrated that temperatures as high as 365degC can be used to accelerate TDDB of SiC devices at the wafer level.

Gate-Induced-Drain-Leakage Current in 45-nm CMOS Technology

Abstract: Gate-induced-drain-leakage (GIDL) current in 45-nm state-of-the-art MOSFETs is characterized in detail. For the current technology node with a 1.2-V power-supply voltage, the GIDL current is found to increase in MOSFETs with higher channel-doping levels. In contrast to the classical GIDL current generated in the gate-to-drain overlap region, the observed GIDL current is generated by the tunneling of electrons through the reverse-biased channel-to-drain p-n junction. A band-to-band tunneling model is used to fit the measured GIDL currents under different channel-doping levels and bias conditions. Good agreement is obtained between the modeled results and experimental data. In addition, the dependence of the GIDL current on body bias, lateral electric field, channel width, and temperature is characterized and discussed.

Thermal Analysis of LED Arrays for Automotive Headlamp With a Novel Cooling System

Abstract: In this paper, we report the thermal performance of a light-emitting diode (LED) headlamp module with a novel cooling system. An air-circulating cooling system was design for the LED headlamp module. The precise fluid field modeling and heat transfer analysis using computational fluid dynamics were performed according to the practical working conditions for the headlamp. The junction temperatures of LEDs were found to decrease by using the air-cooling system and, thus, improved the heat dissipating capability of the LED array. The junction temperature of the LED array was decreased from 70.6degC to 30.25degC when the circulating speed of the air increased from 0 to 120 km/h. Also, the temperature decrease of 2degC ~ 4degC was obtained by using fins. By thermal analysis, the cooling system of LED arrays for the headlamps was found to be feasible. Also, the reliability of the headlamp with LED arrays can be improved with a good cooling system.

Thermal and Mechanical Analysis of High-Power LEDs With Ceramic Packages

Abstract: In this paper, we present the thermal and mechanical analysis of high-power light-emitting diodes (LEDs) with ceramic packages. Transient thermal measurements and thermomechanical simulations were performed to study the thermal and mechanical characteristics of ceramic packages. Thermal resistances from the junction to the ambient were decreased from 79.6 to 46.7degC/W by replacing the plastic mold with a ceramic mold for LED packages. Thermomechanical stress induced in the heat-block test was simulated using a finite-element method. Higher level of thermomechanical stress in the chip was found for LEDs with ceramic packages, despite less mismatching coefficients of thermal expansion, compared with that with plastic packages. The thermomechanical-stress components in the direction of the thickness were found to be larger than that in other two directions. The results suggest that the thermal performance of LEDs can be improved by using ceramic packages, but the mounting process of the high-power LEDs with ceramic packages is critically important and should be the reason for causing delaminating interface layers in the packages.

Flex Cracking of Multilayer Ceramic Capacitors Assembled With Pb-Free and Tin–Lead Solders

Abstract: In this paper, an experimental study was conducted to study susceptibility to flex cracking of multilayer ceramic capacitors (MLCCs), in which a comparison was made between identical samples which were assembled using either Pb-free (Sn3.0Ag0.5Cu) or eutectic tin-lead (Sn37Pb) solder. Flex testing was performed on MLCCs with different sizes (1812 and 0805) and on different dielectric materials (C0G and X7R) obtained from three different manufacturers. Experimental results showed that MLCCs mounted on printed circuit boards (PCBs) with Pb-free solder crack less with board flexing than those mounted on boards with eutectic tin-lead solder. For 1812-size MLCCs assembled with tin-lead solder, the PCB strain at 10% failure ranged between 1700 and 2000 microstrains. The PCB strain at 10% failure for 1812-size MLCCs assembled with Pb-free solder varied between 2300 and 9600 microstrains, depending on the MLCC manufacturer. C0G MLCCs are more resistant to flex cracking than X7R MLCCs. Out of 96 samples tested, none of the C0G MLCCs showed evidence of flex cracking up to the maximum strain level on board of about 137 000 microstrains. In contrast, in the case of X7R MLCCs, from the same manufacturer, assembled with tin-lead solder, 94 out of 96 capacitors failed.

The Effect of Gate-Bias Stress and Temperature on the Performance of ZnO Thin-Film Transistors

Abstract: The stability of ZnO thin-film transistors is investigated by using gate-bias stress. It is found that the application of positive and negative stress results in the device transfer characteristics shifting in positive and negative directions, respectively. It is postulated that this device instability is a consequence of charge trapping at or near the channel/insulator interface. In addition, there is a degradation of subthreshold behavior and channel mobility, which is suggested to result from the defect-state creation within the ZnO layer. The effect of elevated temperature stress shows a predominance of interface-state creation in comparison to trapping under gate-bias stress. Device instability appears to be a consequence of the charging and discharging of preexisting trap states at the interface and in the channel region of the devices. All stressed devices recover their original characteristics after a short period at room temperature without the need for any thermal or bias annealing.

Increased Rate of Multiple-Bit Upset From Neutrons at Large Angles of Incidence

Abstract: Neutron interactions with terrestrial systems produce soft errors, increasing the failure-in-time (FIT) rate of advanced CMOS circuits. These neutron-induced errors are a critical reliability problem facing advanced technologies. This paper reports the accelerated neutron testing on a 90-nm CMOS SRAM that exhibits an increased multiple-bit upset FIT rate from neutrons at large angles of incidence. The modeling of these data is used to predict the reliability of ground-based systems.

Analysis of Al Doping Effects on Resistivity and Electromigration of Copper Interconnects

Abstract: In this paper, we investigated the effect of impurity (aluminum; Al) doping on the resistivity of damascene copper (Cu) interconnects by categorizing it into surface, grain-boundary, and impurity-scattering factors by means of a comprehensive scattering model. Segregation of Al dopant atoms to the interface of the lines increases the resistivity through increased surface scattering. Electromigration (EM)-induced Cu drift is suppressed as the Al concentration increases. The EM lifetime is improved by the suppression of Cu diffusion due to the piled-up Al at the top surface of the Cu interconnects.

Temperature-Level Effect on Solder Lifetime During Thermal Cycling of Power Modules

Abstract: In this paper, we show that, during thermal cycling, the solder lifetime of power modules is not only dependent on temperature variation, but we also highlight the influence of some other key parameters such as upper and lower dwell temperature levels. In particular, we show the influence of these parameters on the solder crack initiation and propagation in the solder layer between the direct copper bonding and base plate of high-power insulated gate bipolar transistor modules. For this purpose, both experimental and numerical investigations have been carried out. Concerning thermal cycling tests, three temperature profiles have been done: -40degC/120degC, 40degC/120degC, and -40degC/40degC. Results have shown that stress values in the solder are monitored by the low temperature level and that the strain is monitored by the high-level one. We observed that the relative magnitude of strain variations is larger than that of stress variation. In order to understand experimental results, finite-element simulations with various high and low temperatures have been performed. Results have pointed out that the solder exhibits two different mechanical behaviors, depending on whether the upper dwell temperature (Tmax) exceeds or not a homologous temperature of approximately 0.74 Tm. When Tmax is below this value, shear strain variations remain in relatively small range values, and shear stress variations have a linear dependence with the temperature variation. In these conditions, only energy-based models should be used for solder lifetime estimation. On the contrary, when Tmax is above 0.74 Tm, shear stress variations reach a saturation value while inelastic shear strains increase significantly. Therefore, in these conditions, either strain- or energy-based models could be used for solder lifetime estimation. Finally, the thermal cycling behaviors of a lead-free solder (SnAg3Cu0.5) and a lead-based one (SnPb37) are numerically compared.

Time-to-Breakdown Weibull Distribution of Thin Gate Oxide Subjected to Nanoscaled Constant-Voltage and Constant-Current Stresses

Abstract: In this paper, we report, for the first time, the statistical distribution of thin-gate-oxide breakdown characterized by using conductive atomic force microscopy (C-AFM) in conjuncdion with the semiconductor parameter analyzer Agilent 4156C. Nanoscaled constant-voltage stress (CVS) and constant-current stress (CCS) were applied to the samples, and the time-to-breakdown Tbd Weibull plots were obtained as a function of stress condition as well as oxide thickness. A different trend in TBD Weibull distribution dependence on the oxide thickness was found for the case of nanoscaled CVS and CCS. By examining the pre- and post-breakdown I-V characteristics as well as their curve fittings, we found that different degradation mechanisms are involved in the oxides subjected to CVS and CCS. For oxides subjected to nanoscaled CVS, the degradation follows the percolation model, whereas for those subjected to nanoscaled CCS, the degradation obeys the trap-assisted tunneling model. The Weibull slope beta value obtained in this paper is found to be consistent with those in the conventional oxide-breakdown tests.

Effect of the Interfacial $\hbox{SiO}_{2}$ Layer in High- $k$ $ \hbox{HfO}_{2}$ Gate Stacks on NBTI

Abstract: A relative contribution of the interface and bulk dielectric defects to negative bias temperature instability (NBTI) in the metal/HfO2/SiO2 gate stacks was investigated. Interface trap generation was assessed by the direct-current current-voltage (DCIV) technique, which independently measures the interface defect density from bulk oxide charges and delineates the contribution of the interface defect generation to the overall NBTI measured by the threshold voltage shift (DeltaVTH). The metal/high-fc induced traps in the interfacial SiO2 layer were found to control the fast transient trap charging/generation processes, which affect the power-law exponents of DeltaVTH and the stress-generated interface trap density DeltaDIT stress time dependencies. Similar kinetics of the long-term DeltaVTH(t) and DeltaDIT(t) dependencies in the high-fe and SiO2 gate stacks suggests that the degradation is governed by the same mechanism of trap charging/generation in the SiO2 film. The investigation leads to a novel methodology for the time-to-failure (TTF) extrapolation, in which the measured DeltaVTH and DeltaDIT values are adjusted for the contributions from the fast transient defect charging/generation processes. It is shown that the conventional TTF analysis might greatly overestimate TTF. Post-NBTI stress recovery at zero relaxation voltage measured by the DCIV method showed that oxide charges and interface traps relax at the same rate indicating that the interface processes may dominate DeltaVTH relaxation. At positive relaxation voltages, however, the oxide charge relaxation exhibits a fast transient component. Relaxation at positive bias also shows an as yet unexplained fast component in the interface trap recovery.

Pulse-Stress Dependence of NBTI Degradation and Its Impact on Circuits

Abstract: In this paper, we provide an overview of the impact of pulsed stress on PMOS devices during negative-bias stress. This paper is divided into the following three sections: 1) DC stress, where the impact of relaxation on the negative bias temperature-instability (NBTI)-induced degradation in FET parameters is discussed, 2) impact of low-frequency ( 1 MHz) pulse stress, which is studied using ring oscillators (ROs). Finally, the implication of the relaxation during NBTI stress when a PMOS device is subjected to a pulse stress is discussed from the circuit perspective. Based on RO-degradation data measured up to 3 GHz, we conclude that, for circuits operating in a continuous switching mode, NBTI will not be a show stopper.