Showing papers in "IEEE Transactions on Device and Materials Reliability in 2009"
TL;DR: In this paper, the authors summarized recent advances in the understanding of charge trapping and defect generation in HfO2/TiN gate stacks and discussed test procedures specifically tailored to quantify gate stack reliability.
Abstract: It has been demonstrated that the introduction of HfO2/ TiN gate stacks into CMOS technologies provides the means to continue with traditional device gate length scaling. However, the introduction of HfO2 as a new gate dielectric and TiN as a metallic gate electrode into the gate stack of FETs brings about new challenges for understanding reliability physics and qualification. This contribution summarizes recent advances in the understanding of charge trapping and defect generation in HfO2/ TiN gate stacks. This paper relates the electrical properties to the chemical/physical properties of the high-epsiv dielectric and discusses test procedures specifically tailored to quantify gate stack reliability of HfO2/TiN gate stacks.
TL;DR: In this paper, the quality of MOSFET gate stacks where high-k materials are implemented as gate dielectrics is investigated, and both drain-and gate-current noises are evaluated in order to obtain information about the defect content of the gate stack.
Abstract: In this paper, we investigate the quality of MOSFET gate stacks where high-k materials are implemented as gate dielectrics. We evaluate both drain- and gate-current noises in order to obtain information about the defect content of the gate stack. We analyze how the overall quality of the gate stack depends on the kind of high-k material, on the interfacial layer thickness, on the kind of gate electrode material, on the strain engineering, and on the substrate type. This comprehensive study allows us to understand which issues need to be addressed in order to achieve improved quality of the gate stack from a 1/f noise point of view.
TL;DR: In this paper, the effects of large-temperature cycling range on direct bond aluminum (DBA) substrate reliability were investigated as it could be a viable alternative to direct bond copper (DBC) substrate.
Abstract: Substrate reliability has, for a long time, been a concern for systems exposed to harsh environments. State-of-the-art direct bond copper (DBC) substrate is susceptible to large-temperature cycling range. Due to the coefficient of thermal expansion mismatch between copper and the base ceramic (e.g., Al2O3 and AlN), delamination of copper from the ceramic base plate caused by thermomechanical stresses is often observed. In this paper, effects of large-temperature cycling range on direct bond aluminum (DBA) substrate reliability were investigated as it could be a viable alternative to DBC. DBA substrates with different metallizations were thermally cycled between -55degC and 250degC. Unlike the DBC substrate, no delamination of aluminum from the aluminum-nitride ceramic base plate was observed in the DBA substrates. However, it was observed that surface roughness of metallization increased during the thermal cycling test. It is believed that, in the high-temperature regime, the significant amount of thermal stress and grain-scale deformation caused recrystallization and grain-boundary sliding to become very active in the aluminum layer, thus leading to the observed increase in surface roughness. The influence of metallization over the aluminum surface on the extent of surface roughness was also characterized.
TL;DR: A review of the most prevalent failure mechanisms resulting from the use of dielectrics in electrostatically driven MEMS devices and methods to characterize both their material properties and impact on reliability performance is provided in this article.
Abstract: After decades of improving semiconductor-device reliability, dielectric failure rates resulting from surface-charge accumulation, dielectric breakdown, and charge injection have been reduced to an almost imperceptible range. However, the influence of dielectric properties and behavior on device performance in microelectromechanical systems (MEMS) is still poorly understood and a substantial contributor to device failure. The difference is primarily due to two factors. First, the characteristic length scale and electrical stress of dielectrics in MEMS are often an order of magnitude or more than in semiconductor devices. Lateral dimensions of tens of micrometers increase the probability of including defect sites, and higher applied voltages increase the probability of dielectric breakdown. Second, dielectrics in MEMS are often designed to fulfill multiple functions, often with no equivalent in semiconductor devices. The use of dielectrics as structural material puts substantial emphasis on material properties other than the classic dielectric properties. The use of freestanding elements in MEMS causes large interfacial surfaces between the dielectric and air which in turn provides various charge trap mechanisms. The same surfaces, when allowed to come in contact, could lead to a failure mechanism called stiction, where the surfaces cannot be separated after contact. This paper provides a review of the most prevalent failure mechanisms resulting from the use of dielectrics in electrostatically driven MEMS devices and methods to characterize both their material properties and impact on reliability performance.
TL;DR: In this article, mitigation techniques to reduce the increased SEU cross section associated with charge sharing in a 90-nm dual-interlocked-cell latch are proposed, which is caused by heavy-ion angular strikes depending on the direction of the ion strike, thereby exacerbating charge sharing among multiple circuit nodes.
Abstract: In this paper, mitigation techniques to reduce the increased SEU cross section associated with charge sharing in a 90-nm dual-interlocked-cell latch are proposed The increased error cross section is caused by heavy-ion angular strikes depending on the direction of the ion strike, thereby exacerbating charge sharing among multiple circuit nodes The use of nodal spacing as a mitigation technique shows an order of magnitude decrease on upset cross section as compared to a conventional layout, and the use of guard-rings show no noticeable effect on upset cross section
TL;DR: In this article, a two-light-source step computation method based on the Monte Carlo theory is developed, and five different optical structures are discussed, and it is suggested that an optical structure with plane and remote phosphor location should be a suitable choice for LED packaging.
Abstract: High-power-light-emitting-diode (LED) packaging is crucial for the development of solid-state lighting. Phosphor's location could affect the LED packaging performance such as light extraction and correlated color temperature (CCT). This paper systematically analyzes first the effects of phosphor's location on LED packaging performance. A two-light-source step computation method based on the Monte Carlo theory is developed, and five different optical structures are discussed. Results show that the location of phosphor has small impact on light extraction but could greatly affect CCT. Remote phosphor location presents higher light extraction than proximate phosphor location. However, the increase is slight, and too remote location could reduce light extraction. A convex phosphor layer has higher light extraction but lower yellow-blue ratio than a plane phosphor layer. Considering the significant variation of CCT, it is suggested that an optical structure with plane and remote phosphor location should be a suitable choice for LED packaging.
TL;DR: In this article, the authors demonstrate the value of RF impedance measurements as an early indicator of physical degradation of solder joints as compared to dc-resistance measurements, and compare their respective sensitivities in detecting interconnect degradation.
Abstract: Traditional methods used to monitor interconnect reliability are based on measurement of dc resistance. DC resistance is well suited for characterizing electrical continuity, such as identifying an open circuit, but is not useful for detecting a partially degraded interconnect. Degradation of interconnects, such as cracking of solder joints due to fatigue or shock loading, usually initiates at an exterior surface and propagates toward the interior. At frequencies above several hundred megahertz, signal propagation is concentrated at the surface of interconnects, a phenomenon known as the skin effect. Due to the skin effect, RF impedance monitoring offers a more sensitive and reproducible means of sensing interconnect degradation than dc resistance. Since the operation of many types of electronic product requires transmission of signals with significant frequency components in the gigahertz range, this has the further implication that even a small crack at the surface of an interconnect may adversely affect the performance of current and future electronics. This paper demonstrates the value of RF impedance measurements as an early indicator of physical degradation of solder joints as compared to dc-resistance measurements. Mechanical fatigue tests have been conducted with an impedance-controlled circuit board on which a surface mount component was soldered. Simultaneous measurements were performed of dc resistance and time domain reflection coefficient as a measure of RF impedance while the solder joints were stressed. The RF impedance was observed to increase in response to the early stages of cracking of the solder joint while the dc resistance remained constant. Failure analysis revealed that the RF impedance increase resulted from a physical crack, which initiated at the surface of the solder joint and propagated only partway across the solder joint. A comparison between RF impedance and event detectors was made to compare their respective sensitivities in detecting interconnect degradation. These test results indicate that RF impedance can serve as a nondestructive early indicator of solder joint degradation and as an improved means for assessing reliability of high-speed electronics.
TL;DR: In this paper, the warpage of flip-chip PBGA packages subject to thermal loading (from room temperature to 260?C) was measured and simulated using a full-field shadow moirE?.
Abstract: The aim of this paper was to measure and simulate the warpage of flip-chip PBGA packages subject to thermal loading (from room temperature to 260?C). In the experiments, a full-field shadow moirE? was used to measure real-time out-of-plane deformations (warpages) on the substrate and chip surfaces of the flip-chip packages under thermal heating and cooling conditions. A finite-element method (FEM) and Suhir's die-assembly theory, together with the measured material data (elastic moduli and coefficients of thermal expansion (CTEs) for organic substrates), were used to analyze the thermally induced deformations of the packages to gain insight into their mechanics. The strain gauge data used to determine the CTEs of the substrates also indicated that there was nearly no bending strain under thermal loading. The full-field warpages on the substrate surface of the packages from the shadow moirE? were documented under temperature loading. It was also found that there were different zero-warpage temperatures (which resulted in a variation of warpages at room temperature) for the four test packages during thermal loading, but they had similar warpage rates (the slope of warpage with respect to temperature). This might have been due to the creep of the underfill and the solder bumps in the packages at the solder reflow temperature. Regardless of the zero-warpage temperature, the warpage of the packages can be well simulated or predicted by FEM and Suhir's theory. The key material properties (elastic moduli and CTEs for the substrate and underfill) that affect the maximum warpage of the package were thoroughly studied. It was found that, among these material properties, a low elastic modulus for the underfill can significantly reduce the maximum warpage, while its CTE is much less sensitive to warpage. Moreover, the substrate CTE affects the warpage of a package only with noncompliant underfills, while a typical substrate elastic modulus (ranging from 10 to 30 GPa) is insensitive to warpage, unless its value is lower than a few gigapascals.
TL;DR: In this article, anodic polarization behavior of the electrode materials was investigated using a microelectrochemical setup using scanning electron microscopy (SEM)/energy dispersive spectroscopy and focused ion-beam SEM.
Abstract: Electrochemical migration behavior of end terminals on ceramic chip resistors (CCRs) was studied using a novel experimental setup in varying sodium chloride concentrations from 0 to 1000 ppm. The chip resistor used for the investigation was 10-k? CCR size 0805 with end terminals made of 97Sn3Pb alloy. Anodic polarization behavior of the electrode materials was investigated using a microelectrochemical setup. Material makeup of the chip resistor was investigated using scanning electron microscopy (SEM)/energy dispersive spectroscopy and focused-ion-beam SEM. Results showed that the dissolution rate of the Sn and stability of Sn ions in the solution layer play a significant role in the formation of dendrites, which is controlled by chloride concentration and potential bias. Morphology, composition, and resistance of the dendrites were dependent on chloride concentration and potential.
TL;DR: In this article, high-power PC-LEDs with selected concentration and thickness of cerium-doped yttrium aluminum garnet (Ce:YAG) phosphor-silicone layer were investigated to study the thermal degradation effect.
Abstract: In this paper, high-power phosphor-converted white-light-emitting diodes (PC-LEDs) with selected concentration and thickness of cerium-doped yttrium aluminum garnet (Ce:YAG) phosphor-doped silicones are investigated to study the thermal-degradation effect of the Ce:YAG phosphor-silicone layer. The experimental results showed that the lumen loss, chromaticity (CIE shift), and spectrum intensity reduction increase as the concentration of Ce:YAG phosphor-doped silicone increases. Although silicone degradation attributed to the final thermal degradation, it is not a dominant factor until a much thicker silicone is employed in PC-LEDs. The major degradation mechanism of the PC-LEDs results from the higher doping concentration of Ce:YAG in silicone. We found that 94% lumen loss was attributed to 5.5 wt% Ce:YAG doping and only 6% of the lumen loss was due to a 1-mm thickness of silicone degradation. However, the negligible differences of measured fluorescent lifetimes among the test samples before and after thermal aging (at 150 degC for 500 h) eliminated any significant nonradioactive quenching processes that existed in the aged samples. The emission spectra indicate that a higher doping concentration in silicone causes a higher degree of loss at the emission wavelength of Ce:YAG. Therefore, minimizing any unwanted interactions, such as refractive index and thermal-expansion mismatches, between the phosphor and the silicone during thermal aging is a new direction of addressing thermal reliability for high-power PC-LEDs. From practical points of view, we found that a lower doping concentration of the Ce:YAG phosphor in thin silicone is a better choice in terms of having less thermal degradation for use in packaging of the high-power PC-LEDs modules and is essential to extend the operating lifetime of the phosphor-based white LED modules.
TL;DR: In this article, the effects of void morphology and critical current density (jc) on the electromigration failure distributions of Cu/low-k dual-damascene vias were examined.
Abstract: We examine the effects of void morphology and critical current density (jc) on the electromigration failure distributions of Cu/low-k dual-damascene vias. Cu dual-damascene vias exhibit multiple modes of electromigration-induced voiding, and reliability is strongly dependent on the morphology of voids. We have developed a model of failure for dc and pulsed dc currents that allows prediction of failure time distributions for vias, taking into account void morphology. We obtain good agreement between the model predictions and experimental data for all observed void morphologies. The model demonstrates that while the concept of ldquoimmortalityrdquo is valid for individual conductors, it cannot be applied to eliminate failure of all nominally identical conductors in large sample sizes that are typical of integrated circuits. We experimentally confirm the existence of resistance increase failures for test populations of nominally identical conductors stressed below the sample average jc. Moreover, failure time distributions for vias exhibit distortion from lognormal and saturation in the vicinity of jc, but they are predictable for all values of j. New reliability extrapolation procedures are required for accurate projection of electromigration lifetimes close to jc. We suggest that the description of the effects of jc on failure distributions of vias discussed here is generally valid irrespective of the choice of conductor and barrier layer materials, and we demonstrate equivalent characteristic behavior of electromigration failure time distributions for both Al and Cu interconnects. Our results also indicate that, in general, accurate modeling of jc for conductor failure requires consideration of both nucleation and growth phenomena, with the relative contribution of each process to jc being dependent on the voiding failure mode.
TL;DR: In this article, the authors address key unit process/processintegration challenges and highlight recent internal/partner and industry findings in the context of TSV manufacturability at 300 mm.
Abstract: Through-silicon via (TSV) will transition to high volume production when end-customer value (as exhibited by functionality, performance, form factor, etc.) are delivered at equivalent yield and cost. While this has been successfully achieved for CMOS image sensors (starting with 200 mm), significant work remains to be done in the TSV value chain (design-materials-process-packaging-test) in the communication and memory segments. This paper will address key unit process/process-integration challenges and highlight recent internal/ partner and industry findings in the context of TSV manufacturability at 300 mm.
TL;DR: In this article, a general electromigration model is presented with special focus on the influence of grain boundaries and mechanical stress, and the possible calibration and usage scenarios of electromigration tools are discussed.
Abstract: The demanding task of assessing long-time interconnect reliability can only be achieved by combination of experimental and technology computer-aided design (TCAD) methods. The basis for a TCAD tool is a sophisticated physical model which takes into account the microstructural characteristics of copper. In this paper, a general electromigration model is presented with special focus on the influence of grain boundaries and mechanical stress. The possible calibration and usage scenarios of electromigration tools are discussed. The physical soundness of the model is proved by 3-D simulations of typical dual-damascene structures used in accelerated electromigration testing.
TL;DR: In this paper, a physical model and a simulation algorithm are used to predict electromigration (EM)-induced stress evolution in dual inlaid copper interconnects, which consists of the effect of grain boundaries (GBs) and texture-related variations of the modulus of elasticity.
Abstract: A novel physical model and a simulation algorithm are used to predict electromigration (EM)-induced stress evolution in dual inlaid copper interconnects. The aim of the current simulation was to investigate the dual effect of the microstructure, which consists of the effect of grain boundaries (GBs) and the effect of texture-related variations of the modulus of elasticity on the stress evolution in copper lines caused by EM. The major difference between our approach and the previously described ones is the accounting of additional stress generated by the plated atoms. The results of the numerical simulation have been proven experimentally by EM degradation studies on fully embedded dual inlaid copper interconnect test structures and by subsequent microstructure analysis, mainly based on electron backscatter diffraction (EBSD) data. The virtual EM-induced void formation, movement, and growth in a copper interconnect were continuously monitored in an in situ scanning electron microscopy experiment. The copper microstructure, particularly the orientation of grains and GBs, was determined with EBSD. For interconnects with interfaces that resist atomic transport and where GBs are the important pathways for atom migration, degradation and failure processes are completely different for microstructures with randomly oriented GBs compared with ldquobamboolikerdquo microstructures. The correspondence between simulation results and experimental data indicates the applicability of the developed model for optimization of the physical and electrical design rules.
TL;DR: General expressions for a large-signal RF safe-operating area, which account for the effect of load impedance on the dynamic output current and voltage characteristics, are presented and show excellent agreement with experimental results.
Abstract: This paper examines the performance and reliability implications associated with aggressively biased cascode SiGe HBT power-amplifier cores under large-signal RF operating conditions. The role of high-power RF stress on device degradation and failure is examined in detail. General expressions for a large-signal RF safe-operating area, which account for the effect of load impedance on the dynamic output current and voltage characteristics, are presented. These show excellent agreement with experimental results. Useful operating guidelines for reliable large-signal operation are provided.
TL;DR: In this article, the channel hot-carrier degradation in nMOS transistors is studied for different SiO2/HfSiON dielectric stacks and compared to SiO 2.
Abstract: Channel hot-carrier (CHC) degradation in nMOS transistors is studied for different SiO2/HfSiON dielectric stacks and compared to SiO2. We show that, independent of the gate dielectric, in short-channel transistors, the substrate current peak (used as a measure for the highest degradation) is at VG = VD, whereas for longer channels, the maximum peak is near VG = VD/2. We demonstrate that this shift in the most damaging CHC condition is not caused by the presence of the high- k layer but by short-channel effects. Furthermore, the CHC lifetime of short-channel transistors was evaluated at the most damaging condition VG = VD, revealing sufficient reliability and even larger operating voltages for the high-k stacks than for the SiO2 reference.
TL;DR: In this article, a step buried oxide PSOI (SB-PSOI) was proposed to increase the breakdown voltage of PSOIsosceles-MOS field effect transistor.
Abstract: For the first time, we report a novel partial-silicon-on-insulator (PSOI) lateral double-diffused MOS field-effect transistor where the buried oxide layer consists of two sections with a step shape in order to increase the breakdown voltage. This new structure is called step buried oxide PSOI (SB-PSOI). We demonstrate that an electric field was modified by producing two additional electric field peaks, which decrease the common peaks near the drain and source junctions in the SB-PSOI structure. Two-dimensional simulations show that the breakdown voltage of SB-PSOI is nearly four to five times higher in comparison to its PSOI counterpart. Moreover, we elucidate operational principles, as well as design guidelines, for this new device.
TL;DR: In this paper, the authors studied the temperature dependence of channel hot-carrier degradation in n-MOS transistors with high-k dielectrics and demonstrated that the total degradation consists of two components: the classical CHC damage located at the drain side and the degradation produced by the voltage drop over the gate dielectric, which can be considered a positive bias temperature instability (PBTI) effect.
Abstract: The temperature dependence of channel hot-carrier (CHC) degradation in n-MOS transistors with high-k dielectrics has been studied. The analysis starts from the most damaging CHC stress conditions at room temperature (V G = V D/2 for long channels and V G = V D for short channels). We find that, for long-channel transistors, the CHC degradation decreases at high temperature, while for short-channel transistors, an increase is observed. In this paper, a new picture to explain the observed increment of CHC damage with temperature for short-channel transistors with high-k dielectric is presented. We demonstrate that the total CHC degradation consists of two components: the classical CHC damage located at the drain side and the degradation produced by the voltage drop over the gate dielectric, which can be considered a positive bias temperature instability (PBTI) effect. Particularly for short transistors stressed at high temperatures, this PBTI component dominates the total CHC degradation.
TL;DR: In this article, the effect of temperature cycling and elevated temperature/humidity on the thermal performance of filled polymer TIMs using the laser flash method was examined using a three-layer sandwich structure.
Abstract: Thermal interface materials (TIMs) have become increasingly important in reducing the interfacial thermal resistance between contacting surfaces inside electronic devices, such as at the die-heat-sink or heat-spreader-heat-sink interfaces. While the focus regarding implementing TIMs remains on reducing the thermal resistance path, the long-term performance of the TIM is important from a life-cycle standpoint. This paper presents test and analysis results examining the effect of temperature cycling and elevated temperature/humidity on the thermal performance of filled polymer TIMs using the laser flash method. A three-layer sandwich structure was used to simulate loading conditions encountered by TIMs in actual applications and to assess the change in their thermal resistances. The evaluated thermal resistance included contact and bulk resistances and was calculated using the Lee algorithm, an iterative method that uses the properties of the single layers and the three-layer sandwich structures. Test samples included three thermal putties, a gap filler, an adhesive, a gel, and two gap pads. For most materials, little change or slight improvement in the thermal performance was observed over the course of environmental exposures. Scanning acoustic microscope images revealed delamination in one group of gap pad samples and cracking in the putty samples as a result of temperature cycling. One thermal putty material showed degradation due to temperature cycling resulting from bulk material changes near the glass transition temperature, while other samples showed little change or slight improvement in the thermal performance over the course of temperature cycling.
TL;DR: In this article, an effective and efficient methodology for reliability simulation is developed to bridge the gap between device-level reliability and that at product level, and a design for reliability methodologies is proposed and classified into two categories: device and circuit levels.
Abstract: In this paper, an effective and efficient methodology for reliability simulation is developed to bridge the gap between device-level reliability and that at product level. For the first time, reliability and circuit-failure behaviors under analog and mixed-signal operating conditions are simulated and analyzed with a high-speed Flash analog-to-digital converter (ADC) circuit developed in advanced CMOS technology. We demonstrate how the failure rate at circuit-level integrating multiple failure mechanisms is determined as a function of operating voltage and temperature. The results show that the dominant failure mechanism and failure rate could be changed by operating conditions. Based on the complete analysis of the ADC circuit operating under normal condition, negative bias temperature instability (NBTI) is the predominant failure mechanism in normal analog and mixed-signal applications, and failure rate increases with the elevated temperature. The impact of NBTI on circuit performance is addressed in detail. Two different types of degradation caused by NBTI are investigated: output voltage degradation and delay. The simulation results are verified by the field data. After exploring the reliability behaviors, a design for reliability methodologies is proposed and classified into two categories: device and circuit levels. This paper shreds light for the circuit life estimation and further reliable design.
TL;DR: In this article, the authors present the underlying physics and modeling of aggressively biased cascode SiGe heterojunction bipolar transistor power amplifier (PA) cores under large-signal operating conditions.
Abstract: This paper presents the underlying physics and modeling of aggressively biased cascode SiGe heterojunction bipolar transistor power amplifier (PA) cores under large-signal operating conditions. The damage characteristics observed during RF operation, particularly the base leakage and collector-base (CB) junction failure, are investigated in detail using dc stress methods. Base leakage was characterized across geometry, voltage, and current conditions, and a damage model is purposed based on Shockley-Read-Hall theory and the reaction-diffusion equation. This model is used to predict damage under aggressive RF operations, in order to extract the operational lifetime of SiGe PAs. The onset of CB junction failure was modeled using the current-gain collapse model, and it accurately captures the failure threshold current I Fail observed during RF stress.
TL;DR: In this article, the yield stress of the power metallization is shown to play a crucial role for the generation of metal deformation and passivation cracks, leading to the development of a new layered metalization material with a distinctly increased yield stress, resulting in a considerably reduced failure generation.
Abstract: Concerning thermomechanically induced failures, such as metal line deformation and passivation cracks, there is a practicable way to achieve the zero-defect limit of plastic-encapsulated power devices. This limit can be reached by evaluating the influence of the major components involved and, consequently, by selecting the appropriate materials and measures. On the other hand, the interdependence between all components must always be kept in mind, i.e., chip and package have to be regarded as an entity. An important finding was that applying simply one improvement step will not necessarily lead to the desired goal. Only the implementation of all improvement steps considering their interdependence is the key for the perfect overall system chip and package. In Part I of this series of papers, the yield stress of the power metallization is shown to play a crucial role for the generation of metal deformation and passivation cracks. Understanding the ratcheting mechanism led to the development of a new layered metallization material with a distinctly increased yield stress, resulting in a considerably reduced failure generation.
TL;DR: In this article, the water-drop test (WDT) and the anodic-polarization test on Sn and Pb electrodes are compared, and their results are shown that the higher the voltage is, the shorter the time to failure becomes.
Abstract: Electronic devices are becoming more miniaturized, and their operating environment is becoming more severe. In a condition of high humidity, high temperature, and high voltage applied, metals in electronics can cause insulation failure by making conductive filaments, which is called electrochemical migration. To understand this phenomenon, the water-drop test (WDT) and the anodic-polarization test on Sn and Pb electrodes are conducted, and their results are compared. Under constant voltage conditions for WDT, initial current of Sn rapidly decreased, but that of Pb did not decrease due to the passivity formation of Sn. In the case of Sn, two zones are distinguishable by level of biased voltage. In the first zone, the current value of Sn is lower than that of Pb by about two orders of magnitude. In the second zone, the current value of Sn is lower than that of Pb by about one order of magnitude. This is due to the corrosion behavior of Sn: passivity formation in the first zone and the pitting corrosion occurrence in the second zone. It was shown that the higher the voltage is, the shorter the time to failure becomes. The total amount of electric charge for the insulation failure of Sn is smaller than that of Pb, which can be explained by the difference in microstructure of dendrites of each material caused by the different corrosion behavior.
TL;DR: In this paper, the authors presented the unique features exhibited by a proposed structure of coaxially gated carbon nanotube field effect transistor (CNTFET) with doped source and drain extensions using the self-consistent and atomistic scale simulations, within the nonequilibrium Green's function formalism.
Abstract: In this paper, we present the unique features exhibited by a proposed structure of coaxially gated carbon nanotube field-effect transistor (CNTFET) with doped source and drain extensions using the self-consistent and atomistic scale simulations, within the nonequilibrium Green's function formalism. In this novel CNTFET structure, three adjacent metal cylindrical gates are used, where two side metal gates with lower workfunction than the main gate as an extension of the source/drain on either side of the main metal gate are biased, independent of the main gate, to create virtual extensions to the source and the drain and also to provide an effective electrical screen for the channel region from the drain voltage variations. We demonstrate that the proposed structure of CNTFET shows improvement in device performance focusing on leakage current, on-off current ratio, and voltage gain. In addition, the investigation of short-channel effects for the proposed structure shows improved drain-induced barrier lowering, hot-carrier effect, and subthreshold swing, all of which can affect the reliability of CMOS devices.
TL;DR: In this paper, the effect of stress-induced leakage current (SILC) on positive bias temperature instability (PBTI) was investigated in nFETs with SiO 2/HfO2/TiN dual-layer gate stacks under a wide range of bias and temperature stress conditions.
Abstract: The positive bias temperature instability (PBTI) and the stress-induced leakage current (SILC) effects are thoroughly examined in nFETs with SiO2/HfO2/TiN dual-layer gate stacks under a wide range of bias and temperature stress conditions. Experimental evidence of the SILC increase with time is obtained suggesting the activation of a trap generation mechanism. Threshold voltage (V T) instability is found to be the result of a complicated interplay of two separate mechanisms; filling of preexisting electron traps versus trap generation each one dominating at different stress condition regimes. Furthermore, V T instability relaxation experiments, undertaken at judiciously chosen conditions, show that the preexisting and stress-induced traps exhibit similar detrapping kinetics indicating that both types of traps may have similar characteristics. Finally, it is shown that the role of the SILC effect (and the associated trap generation component) on V T instability is process dependent and that SILC reduction is accompanied by enhancement of the PBTI device lifetime.
TL;DR: In this paper, the suitability of ESD diodes formed with the isolated P-well/deep N-well diffusions available in triple-well technologies is evaluated for high-speed I/O applications.
Abstract: Layout options for CMOS ESD diodes' p-n junction geometry and metal routing are investigated in this paper. Experiments are performed using 90- and 180-nm technologies. Using the figures of merit ICP/C and R ON * C, it is shown that twin-well stripe diodes with nonminimum diffusion width and high-level broadside routing are optimum for gigahertz-frequency I/Os. In addition, the suitability of ESD diodes formed with the isolated P-well/deep N-well diffusions available in triple-well technologies is evaluated for high-speed I/O applications.
TL;DR: In this paper, the electrical properties of triisopropylsilylethynyl (TIPS) pentacene organic thin-film transistor (OTFT) depending on solvent type were investigated.
Abstract: We investigated the electrical properties of triisopropylsilylethynyl (TIPS) pentacene organic thin-film transistor (OTFT) depending on solvent type. TIPS pentacene was spin coated by using chlorobenzene, p-xylene, chloroform, and toluene as solvents. A broad spectrum of electrical properties was affected by the solvent choice. Fabricated OTFT with chlorobenzene shows field-effect mobility of 1.0 × 10-2 cm2/V · s, on/off ratio of 4.3 × 103, and threshold voltage of 5.5 V. In contrast, with chloroform, the mobility is 5.8 × 10-7 cm2/V · s, on/off ratio of 1.1 × 102, and threshold voltage of 1.7 V. Further investigation by measurement of the grain size of TIPS thin films by atomic force microscopy (AFM) and X-ray diffraction spectroscopy showed that solvents with higher boiling points resulted in larger grain sizes and improved crystallinity. The higher performance electrical characteristics are explained by large grain size and high crystallinity of the TIPS pentacene layer in films spin coated with higher boiling point such as chlorobenzene.
TL;DR: In this article, the impact of process variability and gate oxide degradation on the performance of an amplifier circuit was investigated, and the results showed that both aspects can be decisive in the circuit reliability.
Abstract: With the continuous transistor scaling, device mismatch related to intrinsic process variability increases and becomes one of the most important problems to be faced during circuit design. In addition, gate oxide wear-out strongly affects the device reliability and adds a time dependence to device mismatch. In this paper, the impact on circuit functionality of both process variability and gate oxide degradation is studied. First, the effect of the gate oxide damage on the NMOS and PMOS transistor characteristics and their variability has been analyzed. Second, a methodology based on combined SPICE and Monte Carlo simulations to analyze the time-dependent variability at device and circuit levels is presented, which has allowed to reproduce the experimental data. Finally, using the proposed methodology, the influence of the process variability and gate oxide wear-out on the functionality of different configurations of an amplifier circuit was investigated. The results show that both aspects can be decisive in the circuit reliability.
TL;DR: In this paper, the authors describe the investigation of a Plasma-Induced Damage (PID) event in the metal stack of an 8-in 130-nm-high volume process line.
Abstract: This paper describes the investigation of a Plasma-Induced Damage (PID) event in the metal stack of an 8-in 130-nm-high volume process line. The relevant PID stress and measurement sequence used during standard productive fast Wafer Level Reliability Monitoring, which had detected this event, is discussed, and it is shown to be very effective. Additionally, hot carrier stress was performed on MOS transistors with antenna structures connected to the gate electrode for the quantification of the effect of PID on MOS device characteristics. It is demonstrated that the complete investigation can be done on production wafers in a very short time and only on scribe line test structures, saving time and hardware cost for extra wafers.
TL;DR: In this article, a reaction-diffusion (R-D)-based framework is developed for determining the number of interface traps as a function of time, for both the dc and the ac (dynamic NBTI) stress cases.
Abstract: Negative bias temperature instability (NBTI) in PMOS transistors has become a serious reliability concern in present-day digital circuit design. With continued technology scaling, and reducing oxide thickness, it has become imperative to accurately determine its effects on temporal circuit degradation, and thereby ensure reliable operation for a finite period of time. A reaction-diffusion (R-D)-based framework is developed for determining the number of interface traps as a function of time, for both the dc (static NBTI) and the ac (dynamic NBTI) stress cases. The effects of finite oxide thickness, and the influence of trap generation and annealing in polysilicon, are incorporated. The model provides a good fit with experimental data and also provides a satisfying explanation for most of the physical effects associated with the dynamics of NBTI. A generalized framework for estimating the impact of NBTI-induced temporal degradation in present-day digital circuits, is also discussed.