Showing papers in "IEEE Transactions on Device and Materials Reliability in 2011"
TL;DR: In this paper, the effects of thermally induced stresses on the interfacial reliability of TSV structures were examined using a linear superposition method, and a semianalytic solution was developed for a simplified structure consisting of a single TSV embedded in a silicon wafer.
Abstract: Continual scaling of on-chip wiring structures has brought significant challenges for materials and processes beyond the 32-nm technology node in microelectronics. Recently, 3-D integration with through-silicon vias (TSVs) has emerged as an effective solution to meet the future interconnect requirement. Among others, thermomechanical reliability is a key concern for the development of TSV structures used in die stacking as 3-D interconnects. This paper examines the effects of thermally induced stresses on the interfacial reliability of TSV structures. First, 3-D distribution of the thermal stress near the TSV and the wafer surface is analyzed. Using a linear superposition method, a semianalytic solution is developed for a simplified structure consisting of a single TSV embedded in a silicon (Si) wafer. The solution is verified for relatively thick wafers by comparing to numerical results from finite element analysis (FEA). The stress analysis suggests interfacial delamination as a potential failure mechanism for the TSV structure. An analytical solution is then obtained for the steady-state energy release rate as the upper bound for the interfacial fracture driving force, while the effect of crack length is evaluated numerically by FEA. With these results, the effects of the TSV dimensions (e.g., via diameter and wafer thickness) on the interfacial reliability are elucidated. Furthermore, the effects of via material properties and dielectric buffer layers are discussed.
TL;DR: In this paper, after analyzing the materials and geometries for high-power white LED lighting at all levels, failure modes, mechanisms, and effects analysis (FMMEA) was used in the PoF-based PHM approach to identify and rank the potential failures emerging from the design process.
Abstract: Recently, high-power white light-emitting diodes (LEDs) have attracted much attention due to their versatility in applications and to the increasing market demand for them. So great attention has been focused on producing highly reliable LED lighting. How to accurately predict the reliability of LED lighting is emerging as one of the key issues in this field. Physics-of-failure-based prognostics and health management (PoF-based PHM) is an approach that utilizes knowledge of a product's life cycle loading and failure mechanisms to design for and assess reliability. In this paper, after analyzing the materials and geometries for high-power white LED lighting at all levels, i.e., chips, packages and systems, failure modes, mechanisms and effects analysis (FMMEA) was used in the PoF-based PHM approach to identify and rank the potential failures emerging from the design process. The second step in this paper was to establish the appropriate PoF-based damage models for identified failure mechanisms that carry a high risk.
TL;DR: In this article, an analysis of electrical bias stress instability in amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) is presented.
Abstract: In this paper, we report an analysis of electrical bias stress instability in amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs). Understanding the variations of TFT characteristics under an electrical bias stress is important for commercial goals. In this experiment, the positive gate bias is initially applied to the tested a-IGZO TFTs, and subsequently, the negative gate bias is applied to the TFTs. For comparison with the subsequently negative-gate-bias-applied TFTs, another experiment is performed by directly applying the negative gate bias to the tested TFTs. For the positive gate bias stress, a positive shift in the threshold voltage (Vth) with no apparent change in the subthreshold swing (SSUB) is observed. On the other hand, when the negative gate bias is subsequently applied, the TFTs exhibit higher mobility with no significant change in SSUB, whereas the shift of the Vth is much smaller than that in the positive gate bias stress case. These phenomena are most likely induced by positively charged donor-like subgap density of states and the detrapping of trapped interface charge during the positive gate bias stress. The proposed mechanism was verified by device simulation. Thus, the proposed model can explain the instability for both positive and negative bias stresses in a-IGZO TFTs.
TL;DR: In this paper, the relative neutron-induced soft error rate (SER) of bulk FinFET SRAMs compared to planar FETs is estimated based on drain area, collected charge, and critical charge using mixed-mode 3-D TCAD simulations.
Abstract: The relative neutron-induced soft-error rate (SER) of bulk FinFET SRAMs compared to planar SRAMs is estimated based on drain area, collected charge, and critical charge using mixed-mode 3-D TCAD simulations. The critical charges of the bulk FinFET and planar devices are comparable, with identical gate length, gate width, and gate oxide thickness. However, the charges collected by the bulk FinFET drain due to ion strikes are smaller than those by the planar FET drain. Bulk FinFETs are anticipated to exhibit lower SER sensitivity compared to planar FETs.
TL;DR: In this article, it was shown that the amount of parametric shift induced by the stress cycle becomes nearly identical to that recovered during the relaxation cycle, i.e., the parametric evolution under a fixed set of stress and recovery intervals is cyclic in nature.
Abstract: A major intrinsic limitation of the reaction-diffusion (R-D) model for negative-bias temperature instability (NBTI) is revealed through dynamic stress experiments. We found no evidence of self-limiting recovery, one of the key features of the transport-based R-D model, after repeating the stress and relaxation cycles alternately for many times. The amount of recovery per cycle of the parameter of interest (e.g., threshold voltage shift, change in the charge-pumping (CP) current, etc.) is shown to remain constant, independent of the number of stress/recovery cycles. Under repeated cycling of the test device between stress and recovery, it is also found that the amount of parametric shift induced by the stress cycle becomes nearly identical to that recovered during the relaxation cycle, i.e., the parametric evolution under a fixed set of stress and recovery intervals is cyclic in nature. In conjunction with the thermal activation result, this cyclic behavior of the dynamic NBTI is ascribed to an ensemble of switching hole traps having broad spectra of characteristic trapping and detrapping time constants. The same group of traps responds under a fixed set of experimental conditions, giving rise to the cyclic behavior. The interface state generation was also investigated using a CP current measurement and is found to be permanent within the range of timing examined. It is also shown that the variation in the power-law exponent of the as-measured change in the CP current with temperature could be consistently explained by considering the different thermal activation of the hole trapping and interface state components. In view of these new evidences, previous claims of consistency between the generation/recovery of the interface states and the R-D model or its dispersive counterpart must be reviewed.
TL;DR: In this article, a series of Pb-free die-attach technologies have been identified as possible alternatives to lead-based ones for high-temperature applications, and the fabrication sequence for each system and assesses their long-term reliability using accelerated thermal cycling and physics-of-failure modeling.
Abstract: The demand for electronics capable of operating at temperatures above the traditional 125°C limit continues to increase. Devices based on wide bandgap semiconductors have been demonstrated to operate at temperatures up to 500°C, but packaging remains the major hurdle to product development. Recent regulations, such as RoHS and WEEE, increase the complexity of the packaging task by prohibiting the use of certain materials, such as lead, in electronic products. Traditionally, lead has been widely used in high-temperature solder attach. In this paper, a series of Pb-free die-attach technologies have been identified as possible alternatives to Pb-based ones for high-temperature applications. This paper describes the fabrication sequence for each system and assesses their long-term reliability using accelerated thermal cycling and physics-of-failure modeling. The reliability of the lead-rich alloy was confirmed during this investigation, while early failures of the silver-filled epoxy demonstrated their inability to survive high temperatures. An empirical damage model was developed for the silver nanoparticle paste based on fatigue-induced failures. Encouraging reliability data have been presented for the gold-tin solid-liquid interdiffusion system where bond quality was demonstrated to be a critical factor in its failure mode and mechanism.
TL;DR: An overview on E SD protection designs with low parasitic capacitance for RF circuits in CMOS technology is presented and the comparisons among these ESD protection designs are discussed.
Abstract: CMOS technology has been widely used to implement radio-frequency integrated circuits (RF ICs). However, the thinner gate oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness of RF ICs. Therefore, on-chip ESD protection designs must be added at all input/output pads in RF circuits against ESD damages. To minimize the impacts from ESD protection circuit on RF performances, ESD protection circuit at input/output pads must be carefully designed. An overview on ESD protection designs with low parasitic capacitance for RF circuits in CMOS technology is presented in this paper. The comparisons among these ESD protection designs are also discussed. With the reduced parasitic capacitance, ESD protection circuit can be easily combined or co-designed with RF circuits. As the operating frequencies of RF circuits increase, on-chip ESD protection designs for RF applications will continuously be an important design task.
TL;DR: A straightforward GUI interactive simulation tool is presented that quickly calculates and displays energy bands, electric fields, potentials, and charge distributions for 1-D metal-multilayered-dielectrics-semiconductor stacks and Comparisons between the program and a finite-element Poisson-Schrodinger equation solver are performed to validate the program's accuracy.
Abstract: Novel devices incorporating multiple layers of new materials increase the complexity of device structures, particularly in field-effect transistors, capacitors, and nonvolatile memory (NVM). The mounting complexity of these devices increases the difficulty of generating energy band diagrams and performing device parameter calculations whether these calculations are done by hand, using spreadsheets, or via mathematical programs. Although finite-element Poisson-Schrodinger equation solvers are available to perform the calculations, the cost and time spent learning them can be a hindrance. A straightforward GUI interactive simulation tool is presented that quickly calculates and displays energy bands, electric fields, potentials, and charge distributions for 1-D metal-multilayered-dielectrics-semiconductor stacks. Fixed charge can be inserted into dielectric layers. The freeware program calculates device parameters, (e.g., effective oxide thickness, flat-band voltage (VFB), threshold voltage (Vt), stack capacitance) and layer parameters (e.g., capacitance, potential, electric field, tunneling distance). Calculated data can be exported. Using the simulation tool, trap-based flash NVM is examined. Device performance characteristics such as the Vt and VFB shifts of three different stacks are examined. Comparisons between the program and a finite-element Poisson-Schrodinger equation solver are performed to validate the program's accuracy.
TL;DR: In this paper, ball grid arrays (BGAs), quad flat packages, and surface mount resistors assembled with SAC305 (96.5%Sn+3.5Cu) and Sn 3.5Ag (965%sn+3 5Cu) solder pastes were subjected to thermal cycling from -40°C to 185°C.
Abstract: Applications with temperatures higher than the melting point of eutectic tin-lead solder (183°C) require high-melting-point solders. However, they are expensive and not widely available. With the adoption of lead-free legislation, first in Europe and then in many other countries, the electronics industry has transitioned from eutectic tin-lead to lead-free solders that have higher melting points. This higher melting point presents an opportunity for the manufacturers of high-temperature electronics to shift to mainstream lead-free solders. In this paper, ball grid arrays (BGAs), quad flat packages, and surface mount resistors assembled with SAC305 (96.5%Sn+3.0%Ag+0.5Cu) and Sn3.5Ag (96.5%Sn+3.5%Ag) solder pastes were subjected to thermal cycling from -40°C to 185°C. Commercially available electroless nickel immersion gold board finish was compared to custom Sn-based board finish designed for high temperatures. The data analysis showed that the type of solder paste and board finish used did not have an impact on the reliability of BGA solder joints. The failure analysis revealed the failure site to be on the package side of the solder joint. The evolution of intermetallic compounds after thermal cycling was analyzed.
TL;DR: In this article, the lifetime of sintered nanosilver electrode-pair patterns on an alumina substrate was analyzed using scanning electron microscopy and energy dispersive spectroscopy (EDS).
Abstract: The low-temperature joining of semiconductor chips by sintering of silver paste is emerging as an alternative lead-free solution for power electronics devices and modules working in a high-temperature environment. A promising die-attachment material that would enable the rapid implementation of the sintering process is nanoscale silver paste, which can be sintered at temperatures below 300°C without an external pressure. In this paper, we report our findings on the silver migration in sintered nanosilver electrode-pair patterns on an alumina substrate. The electrode pairs were biased at an electric field ranging from 10 to 100 V/mm and at a temperature between 250°C and 400°C in dry air. The leakage currents across the electrodes were measured as the silver patterns were tested in an oven. Silver dendrites formed across the electrode gap were observed under an optical microscope and analyzed using scanning electron microscopy and energy dispersive spectroscopy (EDS). The silver migration was found in the samples tested at 400°C, 350°C, 300°C, and 250°C. The measurements on the leakage current versus time were characterized by an initial incubation period, called “lifetime,” followed by a sharp rise as the silver dendrites were shorting the electrodes. A simple phenomenological model was derived to account for the observed dependence of lifetime on the electric field and temperature. The EDS mappings revealed the significant presence of oxygen on the positive electrode but the complete absence on the negative electrode. A mechanism involving the oxidation of silver and the dissociation of silver oxide at the anode was suggested. We suggest that the migration of a sintered nanosilver die attachment can be prevented in high-temperature applications through packaging or encapsulation to reduce the partial pressure of oxygen.
TL;DR: In this paper, a 3D TCAD mixed-mode modeling has identified a multiple-transistor charge collection mechanism that explains the experimental data, namely that angled strikes result in charge collection in the normally ON device that increases the restoring current on the struck device.
Abstract: Heavy-ion data from a 130-nm bulk CMOS process shows a counterproductive result in using a common single-event charge collection mitigation technique. Guard bands, which are well contacts that surround individual transistors, can reduce single-event pulsewidths for normal strikes, but increase them for angled strikes. Calibrated 3-D TCAD mixed-mode modeling has identified a multiple-transistor charge collection mechanism that explains the experimental data, namely that angled strikes result in charge collection in the normally ON device that increases the restoring current on the struck device.
TL;DR: In this paper, the authors measured the SET pulsewidths induced in a 65-nm bulk CMOS technology at temperatures ranging from 25°C to 100°C with an autonomous SET capture circuit.
Abstract: In this paper, heavy-ion-induced single-event transient (SET) pulsewidths measured in a 65-nm bulk CMOS technology at temperatures ranging from 25°C to 100°C with an autonomous SET capture circuit are presented. The experimental results for the SETs induced in two different inverter chain circuits indicate an increase in the average SET pulsewidth as a function of the operating temperature. Unique SET test structures were also designed to differentiate between SETs induced in an nMOS transistor and those induced in a pMOS transistor. The SET widths induced in a pMOS transistor increase more with temperature than the SETs induced in an nMOS transistor.
TL;DR: In this article, a new barrier material and process by chemical vapor deposition (CVD) of a Mn oxide layer using a bis(ethylcyclopentadienyl)manganese precursor was reported.
Abstract: A diffusion barrier layer of a few nanometers in thickness is required for a Cu/SiO2 interconnect structure for advanced integrated circuits (ICs). This paper reports a new barrier material and process by chemical vapor deposition (CVD) of a Mn oxide layer using a bis(ethylcyclopentadienyl)manganese precursor. A good adhesion was obtained when the MnOx layer was deposited below 300°C because of the small amount of carbon inclusion within the layer. The metal-oxide-semiconductor samples of Cu/MnOx/SiO2/p-Si showed a very low leakage current of less than 10-7 A/cm2 at 4 MV/cm and a negligible shift of the flat-band voltage after thermal annealing and bias temperature annealing. The obtained results indicated that the CVD-deposited MnOx is an excellent diffusion barrier layer for advanced ICs.
TL;DR: In this article, the critical degradation voltage of AlGaN/GaN high-electron mobility transistors during offstate electrical stress was determined as a function of Ni/Au gate dimensions (0.1-0.17 μm), drain bias voltage, and source/drain-gate contact distance.
Abstract: The critical degradation voltage of AlGaN/GaN high-electron mobility transistors during off-state electrical stress was determined as a function of Ni/Au gate dimensions (0.1-0.17 μm), drain bias voltage, and source/drain-gate contact distance. Devices with different gate lengths and gate-drain distances were found to exhibit the onset of degradation at different source-drain biases but similar electric field strengths, showing that the degradation mechanism is primarily field driven. The degradation field was calculated to be ~ 1.8 MV/cm by Automatically Tuned Linear Algebra Software simulations. Transmission electron microscopy imaging showed creation of defects under the gate after dc stress.
TL;DR: An integrated variability and reliability analysis method based on surrogate models that describe a parametrized complex analytic function for 65-nm NMOS and PMOS devices is introduced.
Abstract: This paper presents a reliability simulation framework based on surrogate modeling. A novel methodology has been developed, which integrates variability analysis with the reliability concepts by employing transistor drain-current surrogate models in terms of crucial process parameters, bias voltages, temperature, and time. Simulation techniques using these models enables exploration of the effects of time-based degradation on analog circuits. The analysis of a differential amplifier at the 65-nm technology node reveals that the dc current is reduced by around 10% in ten years. The tool is used to demonstrate how the biasing structures of analog circuits can be designed to boost aging resilience.
TL;DR: In this article, the effect of oxygen partial pressure on the migration kinetics of the sintered nanosilver at 400°C under an electrical field strength of 50 V/mm was investigated.
Abstract: The low-temperature joining technique of silver sintering is being actively pursued in the power electronics industry as a lead-free die-attach solution for packaging power devices and modules. However, one of the concerns of this technique is the migration of silver at a high temperature. Recently, we have reported our findings of the migration of a low-temperature sintered nanosilver in dry air at a temperature over 250°1C. In this paper, we report our results of the effect of oxygen partial pressure on the migration kinetics of the sintered nanosilver at 400°C under an electrical field strength of 50 V/mm. The range of the oxygen partial pressure tested was between <; 0.01 and 0.40 atm. The silver migration kinetics were monitored by measuring the leakage current across a metal-finger pattern, which allowed the determination of the "lifetime," or the onset time for significant leakage current developed across the two electrodes. With decreasing oxygen partial pressure, the lifetime increases exponentially. Our results suggest that the concern for silver migration in a high-temperature application of sintered silver die attach can be effectively remedied through packaging to keep oxygen away from the silver joints.
TL;DR: In this paper, the roles of substrate majority and minority carriers in triggering external latchup are elucidated, where the term external signifies that the substrate current injection occurs at a location away from the p-n-p-n structure.
Abstract: This paper elucidates the roles of substrate majority and minority carriers in triggering external latchup, where the term external signifies that the substrate current injection occurs at a location away from the p-n-p-n structure. Circuit-level models are presented that allow one to identify the worst case testing condition and to simulate the value of the latchup trigger current. The model captures the effect of guard rings. The simulation results are compared to measurement results, and good agreement is observed, for a variety of CMOS technologies.
TL;DR: In this paper, a time-dependent dielectric breakdown (TDDB) lifetime model predicting the impact of line-edge roughness (LER) on Cu interconnect reliability is proposed.
Abstract: A time-dependent dielectric breakdown (TDDB) lifetime model predicting the impact of line-edge roughness (LER) on Cu interconnect reliability is proposed. The structure, validity, and accuracy of the model are evaluated and discussed. The model is applied to an interconnect scaling scenario that includes conventional patterning and spacer-defined patterning of nanometer-scale Cu wires. LER-aware TDDB lifetime predictions are obtained from the model, and consequent recommendations on how to improve the TDDB lifetime of future interconnects are derived.
TL;DR: In this paper, the relationship between element level and chip level EM failure probability is discussed, and examples of EM evaluation of chip designs are provided to balance the two factors for chip design to achieve the best performance while maintaining chip-level EM reliability.
Abstract: Chip level electromigration (EM) reliability is determined by: 1) the element level EM failure probability used for design guideline generation; and 2) the distribution of EM elements against design limits. Balancing these two factors is critical for a chip design to achieve the best performance while maintaining chip level EM reliability. This paper discusses the relationship between element level and chip level EM failure probability and provides examples of EM evaluation of chip designs.
TL;DR: Wang et al. as mentioned in this paper proposed an accelerated stability test method to improve the long-term repeatability of the manufactured quartz flexible accelerometer from the product hierarchy, based on the analysis of the accelerometer's internal stress mechanism.
Abstract: The manufactured quartz flexible accelerometer has the serious problem of bad parametric repeatability. To solve this issue, this paper does systematic research about the accelerated stability test method to improve the long-term repeatability of the accelerometer from the product hierarchy. Proceeding from the analysis of the accelerometer's internal stress mechanism, it makes a positioning analysis of the causes of bad parametric repeatability and reveals what types of test stress make the accelerometer stable. After the main experimental factors are determined, the scope of these factors' level is obtained through enhancement tests. Based on previous research achievements, an accelerated stability testing scheme is worked out. By the accelerated stability exploratory test in the early period, this paper draws up the effective test method of accelerated stability and achieves the aim of making the accelerometer get into the steady state as soon as possible. This provides initial technical support for the enhancement of the accelerometer's long-term repeatability.
TL;DR: In this article, the authors investigated the effect of impurity doping and CoWP caps on grain boundary electromigration in damascene conductors and showed that the drift velocity exhibits a dependence on microstructure.
Abstract: We investigate electromigration transport mechanisms in Cu and Cu alloy damascene conductors. We show that the drift velocity exhibits a dependence on microstructure. We find that Cu-Al alloys exhibit a small increase in grain boundary diffusion activation energy compared to pure Cu and a reduction in the diffusion prefactor for Cu/cap interfacial transport. Cu-silicide- and CoWP-cap layers are both effective in reducing the interfacial component of electromigration primarily through increases in interface diffusion activation energy. The Cu silicide cap also impacts grain boundary electromigration as a result of silicon doping of grain boundaries during processing, while the CoWP cap has no measurable impact on grain boundary transport. The positive impact of Al doping and metallic-cap layers on electromigration is additive, suggesting the potential for impurity doping and metallic caps to be combined to optimize for reliability across the geometry ranges encountered in circuits.
TL;DR: A complete solution for a full 2-D queue is presented, which maps all the possible thermal noise fluctuations of electron populations in flip-flop inverters and results for the mean time to thermally induced error confirm the estimates given by truncated approximations.
Abstract: Thermally induced fluctuations in the logic state of a simple flip-flop occur on a timescale that renders them impossible to simulate through Monte Carlo methods. In a previous work, an analytical framework based on Markov chains and queue theory was introduced along with a symbolic solution for a truncated 1-D queue, diagonally connecting the two stable logic states in a two-dimensional (2-D) queue. In this paper, a complete solution for a full 2-D queue is presented, which maps all the possible thermal noise fluctuations of electron populations in flip-flop inverters. The results for the mean time to thermally induced error confirm the estimates given by truncated approximations. This formalism is also capable of computing arbitrary probability moments as well as steady-state distributions and transient behavior of the system. The full 2-D queue can also capture the statistics of other noise sources, like radiation-induced charge generation where the flip-flop can transiently reside in a queue state far from the diagonal connecting the two stable logic states of a flip-flop.
TL;DR: In this paper, an adaptive substrate bias design for low-noise amplifier (LNA) was proposed to reduce the sensitivity of noise figure and minimum noise figure subject to process variations and device aging.
Abstract: An adaptive substrate (body) bias design for variability and reliability for a CMOS low-noise amplifier (LNA) is analyzed. The proposed body biasing scheme provides a radio-frequency circuit that is resilient to process variations and device reliability. Small-signal models including substrate bias effect are developed for noise figure and small-signal power gain sensitivity. The cascode LNA operating at 24 GHz with the adaptive substrate bias scheme is compared with the LNA without body bias using the PTM 65-nm technology. The modeling and simulation results show that the adaptive substrate bias reduces the sensitivity of noise figure and minimum noise figure subject to process variations and device aging such as threshold voltage shift and electron mobility degradation.
TL;DR: In this article, a first-order reaction diffusion model for the negative bias temperature instability (NBTI) was proposed, which is similar to the one presented in this paper.
Abstract: The negative bias temperature instability (NBTI) is, arguably, the single most important reliability problem in present day metal-oxide-silicon field-effect transistor (MOSFET) technology. This paper presents a model for the NBTI which is radically different from the quite widely utilized reaction diffusion models which dominate the current day NBTI literature. The proposed model is relevant to technologically important nitrided oxide pMOSFETs. The model is clearly not, at least in its entirety, relevant to pure silicon dioxide gate pMOSFETs. The reaction diffusion models involve hydrogen/silicon bond breaking events at the silicon/silicon dioxide interface initiated by the presence of an interface hole, followed by the diffusion of a hydrogenic species from the interface as well as the potential rebonding of hydrogen and interface trap defect centers. This model does not invoke hydrogen in any form whatsoever but does simply account for the observed NBTI power law response with a reasonable, at least very plausible, assumption about defect distribution and provides a reasonably accurate value for this exponent. (Without making any assumption about defect distribution, the model still provides a time response semiquantitatively consistent with the observations, reasonable agreement considering the simplifying assumptions in the calculations.) The model also provides a reasonable explanation for the recovery which includes a simple explanation for the extremely rapid rate of recovery at short times. In addition, the model provides a very simple explanation why the introduction of nitrogen greatly enhances the NBTI. The model, as presented in this paper, should be viewed as a first-order approximation; it contains several simplifying assumptions. Finally, the model is consistent with recent electron paramagnetic resonance studies of NBTI defect chemistry in nitrided oxide pMOSFETs.
TL;DR: In this article, the effect of polymerization conversion and chemical aging on the warpage evolution of a bimaterial dummy package after molding and during the postmold curing (PMC) process were investigated by using a coupled chemical-thermomechanical modeling methodology.
Abstract: In this paper, the effect of the curing process on the warpage of an encapsulated electronic package is considered by using a coupled chemical-thermomechanical modeling methodology. A cure-dependent constitutive model that consists of a cure-kinetic model, a curing- and chemical-aging-induced shrinkage model, and a degree of cure-dependent viscoelastic relaxation model was developed and implemented in a numerical finite-element model for warpage simulation. Effects of polymerization conversion and chemical aging on the warpage evolution of a bimaterial dummy package after molding and during the postmold curing (PMC) process were investigated by using the proposed modeling methodology. Shadow Moire warpage analyses were also performed to validate the numerical results. It was found from the warpage analyses that the chemical aging, while contributing little to the overall cross linking during the PMC, has a significant effect on the package warpage. The coupled chemical-thermomechanical model can be applied for performing numerical optimization for the packaging process and the assembly reliability.
TL;DR: In this paper, a model for the minority carrier collection efficiency of a given substrate current injector and collector pair is presented, which captures the effects of spacing, supply voltage, temperature, and current level.
Abstract: The n-wells of the parasitic p-n-p-n devices found in a CMOS layout will collect excess minority carriers from the chip substrate, potentially triggering latchup. This paper presents a model for the minority carrier collection efficiency of a given substrate current injector and collector pair; the model captures the effects of spacing, supply voltage, temperature, and current level. The model further describes the quantitative reduction in collection efficiency obtained by using guard rings. A good fit of the model to measurement results is observed in four different CMOS technologies.
TL;DR: In this article, a new model to describe the CHC degradation behavior in n-channel metal-oxide field effect transistors, based on the dominant role of the gate voltage into the total CHC stress, is presented.
Abstract: In ultrascaled complimentary metal-oxide-semiconductor technologies, the lucky-electron model does not describe correctly Channel Hot-Carrier (CHC) degradation for typical transistor test conditions independently of the gate dielectric (SiO2 or high- k). A new model to describe the CHC degradation behavior in n-channel metal-oxide field-effect transistors, based on the dominant role of the gate voltage into the total CHC stress, is presented. This new model can be applicable to long- and short-channel transistors with high- k or SiO2 as a dielectric.
TL;DR: In this article, different gate biasing schemes that reduce the temperature drift of PA output power and power-added efficiency are evaluated, and a simple adaptive gate bias technique effectively provides temperature compensation of PA performances over a wide range of temperatures.
Abstract: Mixed-mode device and circuit simulation is used to examine device self-heating during power amplifier (PA) transient response. Lattice temperature increases with time and eventually saturates beyond the thermal time constant. Temperature variation on the effect of PA performances has been modeled and analyzed. Different gate biasing schemes that reduce the temperature drift of PA output power and power-added efficiency are evaluated. A simple adaptive gate bias technique effectively provides temperature compensation of PA performances over a wide range of temperatures.
TL;DR: In this paper, an optimized Si/SiGe stack channel with a Si cap layer was proposed to overcome the Ge diffusion and confine the channel carriers in the strained SiGe layer without the formation of a significant parasitic channel at the interface.
Abstract: The impact of the Si cap/SiGe layer on the Hf-based high-k /metal gate SiGe channel pMOSFET performance and reliability has been investigated. We proposed an optimized strain SiGe channel with a Si cap layer to overcome the Ge diffusion and confine the channel carriers in the strained SiGe layer without the formation of a significant parasitic channel at the interface. With this optimized Si/SiGe stack channel, a high-performance Hf-based high-k/metal gate SiGe pMOSFET can be obtained with an appropriate VTH (~0.3 V), low C -V hysteresis ( <; 5 mV), and better ION - IOFF , VTH rolloff, and VTH stability. By the way, the related interface trap density in the high-k gate stack layer can also be reduced, thus improving the device's NBTI and HCI stressing-induced reliability.
TL;DR: In this article, a unified study on the relationship between safe operating area (SOA) enhancement and unclamped inductive switching (UIS) behavior in an LDMOS is presented.
Abstract: This paper presents a unified study on the relationship between safe operating area (SOA) enhancement and unclamped inductive switching (UIS) behavior in an LDMOS. Popularized methods of SOA enhancement techniques are implemented, including a highly doped p+ bottom layer, n-adaptive layer, and drift extension. The effect that each enhancement has on SOA is first analyzed and shown, followed by the impact that it has on device ruggedness as measured through the UIS test. The energy absorbed during UIS, time in avalanche, and peak lattice temperature are each considered in evaluating ruggedness. Off-state breakdown voltages and on -resistances are also analyzed. The results indicate varying behavior during UIS, depending on each SOA enhancement technique used.