Showing papers in "IEEE Transactions on Device and Materials Reliability in 2018"

Understanding BTI in SiC MOSFETs and Its Impact on Circuit Operation

Abstract: The threshold voltage hysteresis in SiC power MOSFETs is rarely studied. This paper investigates the captureand emission-time constants of positive and negative charge trapped in the gate oxide and at the interface as a function of gate bias. We present a measurement technique which enables time-resolved measurement of the real ${V} _{\text {th}}$ during application-relevant bipolar ac high temperature gate stress. In addition, we use capture and emission time maps to explain the temperature dependence of $\Delta {\text V}_{\text {th}}$ after stress and are able to simulate $\Delta {\text V}_{\text {th}}$ after positive ac stress considering the full stress-history. Furthermore, we will show that the threshold voltage hysteresis has no harmful impact on switching operation in real applications.

Comparative Study of Reliability of Ferroelectric and Anti-Ferroelectric Memories

Abstract: With the discovery of the ferroelectric (FE) properties within HfO2, the scaling gap between state-of-the-art technology nodes and non-volatile memories based on FE materials can be bridged. In addition to non-volatility, new memory concepts should guarantee sufficient endurance and operation stability. However, in contrast to optimized perovskite based FEs, binary oxide based FE memories still show changes in the memory window (MW) followed by either hard breakdown or closure of the MW. Recently, we have shown that anti-FE (AFE) materials exhibit very stable and significantly higher endurance with respect to the FE counterparts. Inspired by the robustness and remarkable cycling performance of the AFE materials, we analyze the remaining reliability aspects of these devices. By characterizing the pure film properties of capacitor stacks and switching performance when integrated into devices, we compare and investigate temperature stability, imprint, retention, and variability of both FE and AFE memories. We investigate if the lower energetic barrier to be overcome together with partial switching and lower switching induced stress are responsible for the higher endurance of the AFE with respect to the FE based memories. By utilizing charge trapping and charge pumping tests together with leakage current spectroscopy in combination with comprehensive modeling we check that assumption. Moreover, we identify the interfacial buffer layer as the weakest link of these devices.

Output-Power Enhancement for Hot Spotted Polycrystalline Photovoltaic Solar Cells

Abstract: Hot spotting is a reliability problem in photovoltaic (PV) panels where a mismatched cell heats up significantly and degrades PV panel output-power performance. High PV cell temperature due to hot spotting can damage the cell encapsulate and lead to second breakdown, where both cause permanent damage to the PV panel. Therefore, the development of two hot-spot mitigation techniques is proposed using a simple and reliable method. PV hot spots in the examined PV system were inspected using the FLIR i5 thermal imaging camera. Multiple experiments have been tested during various environmental conditions, where the PV module $I - V$ curve was evaluated in each observed test to analyze the output-power performance before and after the activation of the proposed hot-spot mitigation techniques. One PV module affected by the hot spot was tested. The output power during high irradiance levels is increased to approximately 1.26 W after the activation of the first hot-spot mitigation technique. However, the second mitigation technique guarantees an increase in the power up to 3.97 W. An additional test has been examined during the partial shading condition. Both proposed techniques ensure a decrease in the shaded PV cell temperature; thus, there is an increase in PV output power.

Low Leakage Fully Half-Select-Free Robust SRAM Cells With BTI Reliability Analysis

Abstract: This paper presents two different topologies of 11T SRAM cells with fully half-select-free robust operation for bit-interleaving implementation. The proposed 11T-1 and 11T-2 cells successfully eliminate Read disturb and Write half-select disturb and also improve the Write-ability by using power-cutoff and write “0”/ “1” only techniques. The 11T-1 and 11T-2 cells achieve $1.83 \times $ and $1.7 \times $ higher write-yield while both achieve approximately $2 \times $ higher read-yield as compared with 6T cell (at ${V}_{DD} = 0.9$ V). The proposed 11T-1 cell also shows 13.6% higher mean Write-margin (WM) compared with existing 11T cell. Both the proposed cells successfully eliminate floating node condition encountered in earlier power cut-off cells during write half-select. Monte-Carlo simulation confirms low-voltage operation without any additional peripheral assist circuits. We also present a comparative analysis of Bias Temperature Instability reliability impacting the SRAM performance in a predictive 32nm high-k metal gate CMOS technology. Under static stress, the Read Static Noise Margin (RSNM) reduces for all cells. However, 11T-1 and 11T-2 cells improve RSNM by 2.7% and 3.3% under relaxed stress of 10/90. Moreover, the proposed 11T-1 (11T-2) cell improves WM by 7.2% (13.2%), reduces write power by 28.0% (20.4%) and leakage power by 85.7% (86.9%), degrades write delay by 38.1% (23.3%) without affecting read delay/power over a period of 108 seconds (approx. 3 years). The 11T-1 (11T-2) cell exhibits 4.8% higher (2% lower) area overhead as compared to earlier 11T cell. Hence, the proposed 11T cells are an excellent choice for reliable SRAM design at nanoscale amidst process variations and transistor aging effect and can also be used in bit-interleaving architecture to achieve multi-cell upset immunity.

Multiple Defects Cause Degradation After High Field Stress in AlGaN/GaN HEMTs

Abstract: Gate and drain bias dependences of hot carrier degradation are evaluated for AlGaN/GaN HEMTs fabricated via two different process methods. Both positive and negative threshold voltage $V_{\mathbf{th}}$ shifts are observed for each device type, depending on the mode and duration of the stress, indicating the presence of significant densities of donor-like and acceptor-like traps. Worst-case stress bias for transconductance degradation is the “ON” state for both device types. We find that transconductance degradation provides a more effective parameter to monitor defect buildup than $V_{\mathbf{th}}$ shifts, and that a single worst-case stressing bias condition cannot be defined for all varieties of AlGaN/GaN HEMTs. Low-frequency noise measurements versus temperature assist the identification of defects responsible for the observed degradation. Defect dehydrogenation and oxygen impurity centers are found to be particularly significant to the response of these devices.

Comparative Thermal and Structural Characterization of Sintered Nano-Silver and High-Lead Solder Die Attachments During Power Cycling

Abstract: 13.5 mm ${\times }\,\,$ 13.5 mm sintered nano-silver attachments for power devices onto AlN substrates were prepared at 250 °C and a pressure of 10 MPa for 5 min and compared with Pb5Sn solder joint die attachments under constant current power cycling with an initial temperature swing of 50 °C–175 °C. Both effective thermal resistance and microstructural evolution of the samples were monitored using transient thermal impedance measurement and nondestructive X-ray computed tomography at regular power cycling intervals. The results showed a gradual increase in the effective thermal resistance of the Pb5Sn solder joints from 0.047 to 0.133 K/W from zero to 41k power cycles, followed by a rapid escalation to 0.5018 K/W at 52k cycles. This was accompanied with the formation and development of oblique cracks within the Pb5Sn die attachments until delamination occurred at the solder/device and solder/substrate interfaces. By contrast, the effective thermal resistance of the sintered Ag joints remained almost constant at 0.040 K/W up to 116k power cycles. This was explained in terms of thermally induced continuation of densification of the sintered structure and the formation and development of networked vertical cracks within the sintered Ag die attachments, some of which further extended into the Cu tracks of the AlN substrate.

Analysis of Reduction in Lag Phenomena and Current Collapse in Field-Plate AlGaN/GaN HEMTs With High Acceptor Density in a Buffer Layer

Abstract: We make a 2-D transient analysis of field-plate AlGaN/GaN HEMTs with a semi-insulating buffer layer, where only a deep acceptor above the midgap is considered. The deep-acceptor density is varied between 1017 cm−3and $8 {\times 10}^{{17}}$ cm−3. It is studied how the deep-acceptor density and the field plate affect the buffer-related drain lag and gate lag, and current collapse. It is shown that the lags and current collapse are reduced by introducing a field plate. This reduction occurs because electron trapping by the deep acceptors is weakened by the field plate. It is also shown that without a field plate, the drain lag and current collapse increase with increasing the deep-acceptor density as expected, although the gate lag decreases when the deep-acceptor density becomes high in the region between $2{\times 10}^{{17}}$ cm−3and $8 {\times 10}^{{17}}$ cm−3. On the other hand, with a field plate, surprisingly, the lags and current collapse decrease when the deep-acceptor density becomes high. This is attributed to the fact that the reduction in drain lag and current collapse by introducing a field plate becomes more significant when the deep-acceptor density becomes higher.

Effect of Sintering Pressure on the Porosity and the Shear Strength of the Pressure-Assisted Silver Sintering Bonding

Abstract: The microstructure, thickness, porosity, and shear performance of the silver (Ag) sintering layers under different sintering pressures were investigated. Experimental results demonstrated that the thickness and the porosity of the sintering layer decreased when the sintering pressure varied from 5 MPa to 30 MPa. This densification phenomenon facilitated the enhancement of the Ag sintering layers. The shear strength was improved significantly from 44.19 MPa to 69.41 MPa when the sintering pressure increased from 5 MPa to 10 MPa. When the sintering pressure ranged from 10 MPa to 30 MPa, the shear strength presented a slow increase from 69.41 MPa to 73.38 MPa. According to the results of the failure analysis, fracture mode transformation was considered as the basic reason for this phenomenon. The increasing sintering pressure promoted the bonding of the nano-Ag particles during the sintering process. Consequently, the fracture of the sintered-Ag layer transformed from brittle fracture to ductile fracture because of the increasing sintering pressure. The delamination area between Cu and Ni layers coated on the bottom Mo plate was clearly enlarged with the increasing sintering pressure. The delamination between Cu and Ni layers coated on the bottom Mo plate turned to be the main failure mode when the sintering pressure was higher than 10 MPa.

A Review on Hot-Carrier-Induced Degradation of Lateral DMOS Transistor

Abstract: With the scaling of process node and increase of operation voltage, the electrical fields and impact ionization generation rates in lateral double-diffused MOS (LDMOS) transistors are obviously increased. As a result, a detailed characterization and understanding for long-term hot-carrier-induced (HCI) effect of LDMOS have been becoming more and more important. This review compares and summarizes the HCI damage locations and degradation mechanisms for all kinds of typical LDMOS devices under different stress conditions. Finally, generalized conclusions on HCI effect of LDMOS are deduced, and some special degradation influence factors brought by the device design technologies are also clarified.

The Impact of Fin Number on Device Performance and Reliability for Multi-Fin Tri-Gate n- and p-Type FinFET

Abstract: In this paper, the effect of carrier quantization on device characteristics and stress-induced device degradation for multifin high- ${\boldsymbol \kappa }$ /metal tri-gate n-type and p-type fin field-effect transistors (FinFETs) were investigated through electrical characterization and simulation. Carrier conduction in the steep Si fins of FinFETs is different for devices with different numbers of fins and affects device performance and reliability. For n-type FinFETs, devices with fewer fins inhibited the coupling effect between fins to exhibit superior device performance but underwent more severe hot carrier–induced device degradation. The coupling effect between fins reduced the equivalent electric field in the multifin devices and further inhibited impact ionization; thus, devices with more fins achieved superior reliability to single-fin devices after hot-carrier stress. For p-type FinFETs, a similar effect on performance was demonstrated but with lower sensitivity to hot-carrier stress-induced device degradation caused by lower hole mobility within the Si fin channel.

Feasibility of Room-Temperature GHz-THz Direct Detection in Graphene Through Hot-Carrier Effect

Abstract: Recent theories suggest that the photo thermoelectric effect dominates the photo response in graphene. Hot-carrier generation arising from carrier multiplication in graphene under the incident light is introduced as the main cause of this effect. Here, we investigate the possibility of GHz-THz direct detection in a graphene-based device through Hot-carrier effect. The proposed structure is a Schottky junction between graphene and Si. We have measured the optical properties of the junction under 86 GHz and 0.102 THz radiations at room temperature. We have repeated the experiments at cryogenic temperatures down to 150 K. The minimum responsivity of the junction is measured as $2\boldsymbol {\times } 10^{\mathbf{4}}$ V/W under 0.102 THz radiations at room temperature. This value increases five-fold at the cryogenic temperatures. We discuss the physics behind room temperature operation of the device based on the photo thermoelectric effect and the hot-carrier generation in graphene under the illuminations. Room temperature and direct detection of GHz and THz radiation in the graphene-Si junction can be practical evidence of hot-carrier generation in graphene under the incident illuminations.

Electromigration Check: Where the Design and Reliability Methodologies Meet

Abstract: Due to technology scaling, electromigration (EM) signoff has become increasingly difficult, mainly due to the use of inaccurate methods for EM assessment, such as the empirical Black’s model. Results of recent measurements performed on power grid-like structures isolated in the power grid environment have demonstrated that the weak link approach cannot accurately predict lifetime of the power grids. It calls for significant over-design, while, today, there is very little margin left for EM. Numerous observations clearly indicate that there is a need for a new EM checking approach that accurately models EM degradation using physics-based models, combined with a mesh model to account for redundancy, while being fast enough to be practically useful. In this paper, we present a novel approach for power grid EM checking using physics-based models that can account for process, voltage and temperature variations across the die. Existing physical models for EM in metal branches were extended to track EM degradation in multi-branch interconnect trees. Our results, for a number of IBM power grid benchmarks, confirm that Black’s model is overly inaccurate. The lifetimes found using our physics-based approach are on average 2.75x longer than those based on a Black’s model, as extended to handle mesh power grids. With a maximum runtime of 2.3 h among all the IBM benchmarks, our method appears to be suitable for large VLSI circuits.

Study of Long Term Drift of Aluminum Oxide Thin Film Capacitive Moisture Sensor

Abstract: Drift is an important phenomenon of capacitive humidity sensor, the most vital device in the commercial dew point meter. Due to drift in the output, most of the meters for critical applications require costly and time-consuming recalibration. Modeling of drift phenomenon for RH humidity sensors was reported in various literature. But to the best of our knowledge, there is no work reported so far about the drift of the sensors utilized for trace level moisture detection. This paper presents the mathematical model, the electrical equivalent circuits, and long-term drift analysis of the aged capacitive sensors for trace moisture sensing. The sensors were fabricated using porous alumina oxide thin film for detecting moisture in the range of 3 to 100 ppm. To study the long-term drift, experiments were performed under different operating conditions over a period of nearly one year. The response behaviors of the sensors were simulated with the help of the model. Comparing the model response with the experimental results, the proposed model can be used for drift analysis for an aged sensor, determination of hydration level and moisture condensation inside the pores. Experimental results showed that when a sensor was kept in drying agent, a maximum average drift of only 1.50% was observed but when a similar sensor was kept in open high humidity atmosphere, the maximum long-term drift was found to be ~11.20%.

Process Variation and NBTI Resilient Schmitt Trigger for Stable and Reliable Circuits

Abstract: Negative bias temperature instability (NBTI) is a major time-dependent reliability concern with the pMOS transistor at elevated temperature. NBTI in pMOS is the severe dominating factor of circuit reliability as it increases the threshold voltage with time. In this paper, an nMOS-only Schmitt trigger with a voltage booster (NST-VB) circuit is proposed. The use of only an nMOS transistor in the critical path of the Schmitt trigger circuit drastically reduces the effect of NBTI on the circuit and, hence, improves performance. The proposed circuit is less affected by both inter-die and intra-die process variations in consequence of an nMOS-only structure. Because of NBTI, the increase in delay for the proposed NST-VB circuit is only 0.47% compared to 7.2% and 1.47% for the conventional Schmitt trigger and nMOS inverter, respectively, after the stress time of three years. The proposed NST-VB circuit is also validated with an s27 benchmark circuit from the ISCAS’89 benchmark set and found that it has a lower effect of NBTI compared to CMOS and Schmitt trigger inverter circuits. For the viability of the proposed circuit, figure-of-merit (FOM) is used as a performance metric and it is found that the proposed circuit has ${15.11\times }$ improved FOM compared to the conventional Schmitt trigger circuit.

Effects of Thermo-Mechanical Fatigue and Low Cycle Fatigue Interaction on Performance of Solder Joints

Abstract: This paper demonstrates the feasibility of low cycle fatigue effects on the thermo-mechanical fatigue evolution in the solder joints of a power module. To achieve this goal, finite-element method (FEM) simulation and experimental studies have been carried out. One of the prepared samples was exposed to the sole thermal cycling while another one underwent frequent drop impacts, as an indicator of low cycle fatigue event, during the thermal cycling. The FEM results indicate that the thermal cycling leads to the accumulated creep strain in the solder joints. The amount of creep strain considerably increases when the drop impacts are coupled to the thermal cycling. This phenomenon is due to the additional peeling stress applied by drop impacts to the solder joints. It is also revealed that with an increase in the number of drop impacts, the rate of strain accumulation declines which may be due to the restriction of changes led by stress triaxiality. The fractography also validates that the sample exposed to both drop and thermal loadings shows an entire brittle fracture mode. Moreover, the EDS map shows that the elemental distribution heterogeneity and intermetallic growth were created under mutual effects of drop impacts and thermal cycle fatigue.

Failures of LEDs in Real-World Applications: A Review

Abstract: With this paper, we review several different failure mechanisms of commercial light emitting diodes operating in real-life applications. We consider both high power and mid power devices, which represent the biggest share of the market. Real-life applications are particularly interesting since they reveal potential reliability issues and weaknesses of the optoelectronic devices, which are not detected/studied during conventional laboratory testing, due to their extrinsic origin. The analyzed failures mechanisms are mainly due to: 1) electrical overstress (surge and hot plugging); 2) assembly issues; 3) mishandling; and 4) chemical contamination. The results presented within this paper provide relevant data for the improvement of the reliability and robustness of current solid-state lighting systems.

Evaluating the Impact of the Instruction Set on Microprocessor Reliability to Soft Errors

Abstract: Reliability in microprocessors is a concern. There are many techniques that add spatial and temporal redundancy, with the goal of increasing the error detection and correction capabilities of the system. In this paper, we present a methodology to estimate the intrinsic reliability of the instruction set architecture of a given processor. By analyzing the internal encoding of the instructions and their relations, an initial estimate of the silent data corruption rate that a certain architecture may suffer due to soft errors is obtained. The results provided by this methodology can be used to compare the intrinsic reliability of different processors and help decide the best protection technique in each case.

Self-Heating Assessment on Bulk FinFET Devices Through Characterization and Predictive Simulation

Abstract: This paper describes three different measurement methodologies for the electrical characterization of FinFET self-heating at wafer-level. Finite element simulations of heat transport are used to interpret heater-sensor temperature gradients and validate the measurements. The different sensor types were designed to use the threshold voltage ( ${V} _{\text {T}}$ ) of an adjacent FET, the forward bias ( ${V} _{\text {D}}$ ) of an adjacent pn-junction or the gate resistance ( ${R} _{\text {G}}$ ) of the device itself. We report that self-heating is underestimated by 35% when sensed at a neighboring device. We also confirm that heat from local and surrounding sources are additive.

Bending Performance of Flexible Organic Thin-Film Transistors With/Without Encapsulation Layer

Abstract: Flexible pentacene-based organic thin-film transistors (TFTs) were fabricated and their performance was investigated as a function of the bending radius and the thickness of the polydimethylsiloxane (PDMS) encapsulation layer. The TFTs were fabricated on a flexible polyimide film (film thickness: 75 $\mu \text{m}$ ), and encapsulated by a PDMS layer. Degradation of the device performance during application of a tensile bending stress of 3 mm was minimized by utilizing an encapsulation layer thickness of 75 $\mu \text{m}$ , because the mechanical strain on the pentacene layer was almost off-set (tensile strain was applied to the bottom layer of the pentacene, and compressive strain was applied to the top layer of pentacene). At the tensile bending stress of 3 mm, the performance of the non-encapsulated TFT was degraded, whereas the encapsulated device showed great stability. This flexibility and bending stability were enabled by the use of the 75- $\mu \text{m}$ PDMS encapsulation layer, due to the location of the pentacene active layer in the neutral region position. A mechanical reliability test was performed for 120 min with a bending radius of 3 mm, demonstrating that only the device with the 75- $\mu \text{m}$ thick encapsulation layer showed stable device performance over a stress time of 120 min.

A Double Error Correction Code for 32-Bit Data Words With Efficent Decoding

Abstract: There has been recent interest on designing double error correction (DEC) codes for 32-bit data words that support fast decoding as they can be useful to protect memories. To that end, solutions based on orthogonal Latin square codes have been recently presented that achieve fast decoding but require a large number of parity check bits. In this letter, a DEC code derived from difference set codes is presented. The proposed code is able to reduce the number of parity check bits needed at the cost of a slightly more complex decoding. Therefore, it provides memory designers with an additional option that can be useful when making trade-offs between memory size and speed.

Majority Voting-Based Reduced Precision Redundancy Adders

Abstract: Fault-tolerant systems are usually implemented with triple modular redundancy (TMR)-based protection techniques which has a huge area and power overhead. Previous works have shown that this overhead can be improved by using reduced precision redundancy (RPR)-based approaches for intrinsically precision-tolerant applications like image and video processing. The error detection and steering logic required in the RPR schemes utilize subtraction and comparisons which are more complex hardware operations than TMR voting. This overhead is affordable for complex hardware structures, for example, finite impulse response filters, but for simple structures like adders, it can be significant. In this letter, it is shown that combining the traditional TMR voting with the RPR brings up considerable savings in area and power budget when applied to very-large-scale integration adder circuits.

Rapid Solder Interconnect Fatigue Life Test Methodology for Predicting Thermomechanical Reliability

Abstract: A rapid reliability test methodology was devised for simulating mechanical stresses induced from thermal expansion induced shear in temperature cycling of flip-chip devices in order to de-convolute shear stress from thermal effects in typical environmental tests. Using controlled force application according to spring deflection, a test stand was created to mechanically apply shear stress to solder interconnects in flip chip devices at isothermal conditions. The shear stress was applied cyclically using a tribometer to simulate the mechanical stresses induced in the interconnects of a device during a thermal cycle while in operation or accelerated testing. In the mechanical application of shear, the control of loading and cyclic rate can be precisely controlled while monitoring key factors for observing crack propagation and damage. In doing so, this novel approach introduces the ability to directly correlate shear stress and plastic work accumulation (damage) to fatigue life in a generic device, utilizing help from finite element models alongside data acquisition. Using the obtained correlations, lifetime predictions through early stage design analysis are possible, paving the way for a-priori optimized design for thermomechanical reliability in flip-chip devices. The methodology presented herein creates the opportunity to eliminate costly lifetime testing on multiple electronic device designs/configurations, while also expediting any data collection needed for new materials or process related impacts to reliability.

Circuit-Level Technique to Design Variation- and Noise-Aware Reliable Dynamic Logic Gates

Abstract: In this paper, a novel approach to decrease the delay variations in dynamic logic topology is proposed. The proposed method is based on extending the Schmitt trigger characteristics to dynamic gates. A simple model of the proposed technique is derived to accurately approximate the extent to which variations in delay due to process, voltage, and temperature (PVT) fluctuations can be mitigated. Reliability analyses with PVT variations have been extensively performed on NAND/NOR logic implementations of the proposed methodology. Analyses reveal about 50% reduction in delay variability, with additional improvement in noise margin at an expense of slight increase in delay. The proposed approach was assessed by Monte Carlo simulations in the SPICE environment, and the analysis results support the theoretical proposal.

Characterization of the Effect of Pulse Quenching on Single-Event Transients in 65-nm Twin-Well and Triple-Well CMOS Technologies

Abstract: As chip technologies scale down in size, multiple adjacent logic nodes are often affected by a single high-energy ion strike. The so-called pulse quenching effect, induced by single-event charge sharing collection, has a significant effect on single-event transients (SETs). In this paper, the effect of pulse quenching on SETs is quantitatively characterized in 65-nm twin-well and triple-well CMOS technologies. Two groups of heavy ion experiments on two inverter chains were performed for the characterizations, and the effect of pulse quenching on SETs was quantitatively analyzed in detail.

Role of Plastic Behaviors of Ni 3 Sn 4 Intermetallic Compound on Solder Joint Reliability

Abstract: The study aims at investigating the influences of the elastoplastic behaviors of the micrometer-thick Ni3Sn4 intermetallic compound (IMC) observed in the Cu/Ni/Sn3.5Ag solder joints of 3-D chip stacking package on the solder joint reliability under accelerated thermal cycling (ATC). The IMC’s elastoplastic properties are characterized through the developed forward-reverse analysis algorithm, which integrates parametric finite element analysis (FEA) of instrumented indentation, dimensional analysis, and an experimental instrumented indentation test. The algorithm is first applied to characterize the elastoplastic behaviors of an electrodeposited Cu thin film, the results of which are compared with the known data, followed by a test on the thin Ni3Sn4IMC. The predicted elastoplastic properties are input to the ATC FEA model of the package to simulate the solder joint mechanical response, by which the corresponding fatigue life is assessed using a Coffin–Manson model. The simulation is validated against the experimental data. Besides, the prediction is compared with that without the plastic effect. Results show that despite bulk IMCs being normally elastic, brittle, and hard, the thin Ni3Sn4 IMC possesses a highly ductile (plastic) and strain-hardening behavior. Moreover, taking the plastic behavior of the thin Ni3Sn4 IMC into account helps improve the prediction of the solder joint fatigue life of the package.

A Low-Overhead Integrated Aging and SEU Sensor

Abstract: Aging has become a critical CMOS reliability issue in nanoscales. In general, the aging effect is exhibited as an increase in the delay of the combinational parts and robustness degradation of memory structures. To monitor the aging state of the combinational parts, this paper proposes an aging sensor that is combined with the flip-flops of a chip. The function of this sensor is based on monitoring the stability violation of the critical path output, before the rising edge of the clock signal. The precision of the proposed sensor is about $2.7 \times $ of the most accurate previously presented aging sensors. This is achieved by almost 33% less area overhead compared with state-of-the-art aging sensors. Furthermore, the presented sensor can detect and correct half of the single event upsets (SEUs), which lead to a bit-flip in the flip-flop. In addition, by utilizing the SEU detection circuitry, a scheme for reducing bias temperature instability, the most important aging process in the memory structures, is presented by balancing the duty cycle of the flip-flop transistors with negligible extra overhead.

Effects of Copper Migration on the Reliability of Through-Silicon Via (TSV)

Abstract: Non-destructive electrical characterization was performed to detect copper migration in a degraded through-silicon via structure after various stressing conditions, such as elevated temperature exposure, temperature cycling, and electrical biasing. They were performed either independently or as a combination with electrical bias for comparison. Variations in the electrical characteristics reflect the presence of copper. The electrical characteristics were also able to monitor the transport of copper ions from an applied electric field. Physical failure analysis was performed to verify the presence of migrated copper, correlating with the changes observed during electrical measurement. With this understanding, reliability assessments become possible where this paper seeks to value add to verify the influence of Cu migration on the conduction mechanism and time-dependent dielectric breakdown (TDDB) lifetime, in which there is currently a lack in understanding. The conduction mechanism was fitted with experimental data before and after degradation and it was deduced that the Poole–Frenkel conduction mechanism is the dominant mechanism after degradation. However, this is dependent on the copper oxidation state which was verified to change over time from Cu2O to CuO by X-ray photoelectron spectroscopy. TDDB experiments were also performed based on this understanding and found that the presence of copper may accelerate or decelerate time to failure. TDDB lifetime was fitted experimentally and is found to be in good agreement with the $\sqrt {E} $ model. It was verified experimentally by measuring the time to failure at low ${E}$ -field within reasonable failure time, rather than extrapolating from data at high field.

Improved Performance of Amorphous InGaZnO Thin-Film Transistor by Hf Incorporation in La 2 O 3 Gate Dielectric

Abstract: The effects of Hf incorporation in La2O3 gate dielectric on the electrical characteristics of amorphous InGaZnO thin-film transistor are studied. With an appropriate dose of Hf, the device performance can be significantly improved, resulting in high saturation mobility of 30.5 cm2V−1s−1, small subthreshold slope of 0.15 V/dec, and negligible hysteresis (0.05 V). These improvements are attributed to suppressed crystallization and enhanced moisture resistance of the gate dielectric (supported by transmission electron microscopy and atomic force microscopy respectively), both induced by the Hf incorporation. However, excessive Hf incorporation leads to device degradation, likely due to more oxygen vacancies generated in the gate dielectric as shown by X-ray photoelectron spectroscopy.

Impact of the NAND Flash Power Supply on Solid State Drives Reliability and Performance

Abstract: The NAND flash memory technology is the fundamental building block of storage systems like solid state drives. Their reliability drastically impacts the design choices of the error recovery flows exploited to improve drive’s performance, which progressively degrades as the number of bit errors to be corrected increases. Among the many causes producing errors, it is found that the NAND flash power supply plays a non-negligible role. In this paper, we will show how the drive’s performance degradation rate measured by the sustainable bandwidth, read latency, and quality of service metrics, heavily depends on the power supply. The results will show that by using a lower power supply in endeavor to reduce the energy consumption of the drive will yield a significant bandwidth (up to 44.4 kIOPS), latency (up to $504~\boldsymbol {\mu }\text{s}$ ), and quality-of-service (up to 1.5 ms) detriment. Counterintuitively, we will show that the overall energy consumption per byte will increase (up to 4.5 times) in specific working conditions of the drive.

A Fault Injection Platform Supporting Both SEU and Multiple SEUs for SRAM-Based FPGA

Abstract: A fault injection platform which supports both single event upset (SEU) and multiple SEUs for SRAM-based field programmable gate arrays (FPGA) is proposed. The fault injector can inject SEU or accumulated multiple SEUs and repair the SEUs by itself. The proposed fault injection platform is fast because the address generator can generate available value in real time. We show the error rates of the SEU test and multiple SEUs test. The experimental results indicate that SEU has an impact on the sensitivity of design to the next SEU in SRAM-based FPGA.