Showing papers in "IEEE Transactions on Electron Devices in 1975"

Electron and hole drift velocity measurements in silicon and their empirical relation to electric field and temperature

Abstract: The drift velocity of electrons and holes in silicon has been measured in a large range of the electric fields (from 3 . 102to 6 . 104V/cm) at temperatures up to 430 K. The experimental data have been fitted with a simple formula for the temperatures of interest. The mean square deviation was in all cases less than 3.8 percent. A more general formula has also been derived which allows to obtain by extrapolation drift velocity data at any temperature and electric field.

Characterization of positive photoresist

Abstract: This paper presents techniques for measuring a new set of parameters used to describe the image forming properties of positive photoresist [1]. Exposure is described by three optical parameters, A, B, and C, through which the process is modelled. Development is described in terms of a rate relationship R(M) between the rate of removal of photoresist in the developer and the degree of exposure of the photoresist. This set of functional parameters provides a complete description of positive photoresist exposure and development, and is the basis for the theoretical process models discussed in the accompanying papers.

Field-effect transistor versus analog transistor (static induction transistor)

Abstract: The reason why the usual FET shows the saturated characteristics has been shown that with increasing drain voltage, the effect of the negative feedback action, increases through a marked increase of the Series channel resistance in the neighborhood of the pinch-off voltage, under which condition the apparent transfercon-ductance G_{m'}= G_{m}/(1 + r_{s}.G_{m}) becomes G_{m'} \simeq r_{s}^{-1} . It is also pointed out that a transistor in analogy to the vacuum type proposed by Watanabe and Nishizawa in 1950, exhibits the nonsaturated build-up character only When the internal negative feedback action is as little as G_{m'} \simeq G_{m} . In this case, when the channel has not yet pinched off, the characteristics are ohmic and then the transistor can operate as a good variable resistor; on the other hand, when the channel has already pinched, the transistor shows the build-up characteristics similar to those of a vacuum tube triode as a result of the static induction from the drain. The transistor similar to that of the vacuum tube triode type is named "Static Induction Transistor," because its output character is based on the static induction as well as input characteristics. The SIT has the exponential characteristics in contrast with the "Analog Transistor" which is expected by Shockley to follow the space-charge conduction law. The SIT has already been ascertained to have low noise, low distortion, and high-power capability, and its fabrication has been already realized in the form of a high-power transistor (2 kW, 8 MHz), a high-frequency transistor (a few watts, UHF), and a high-speed thyristor. Microwave transistors and very high-speed integrated circuits are being constructed, as well as variable resistors.

Modeling projection printing of positive photoresists

Abstract: The accompanying papers "Optical Lithography" and "Characterization of Positive Photoresist" introduce the concepts of modeling using destruction of the photoactive inhibitor compound to describe exposure and a surface-limited removal rate to describe development together with the optical exposure parameters A, B, and C and a rate relationship, R(M), which characterize the photoresist for modeling purposes. This paper applies the model to, the projection exposure environment: exposure and development of photoresist are treated with a simulation model that allows computation of image surface profiles for positive photoresist exposed with a diffraction limited real image.

Theory of the MOS transistor in weak inversion-new method to determine the number of surface states

Abstract: The drain current I D versus gate voltage V G of an MOST operating in weak inversion, and the influence of surface potential fluctuations on this characteristic have been studied before [1], [2]. The purpose of this paper is to derive an expression of the drain current I D versus the drain voltage V D for devices with a channel length not smaller than 20 µm. It is demonstrated that the surface potential fluctuations do not affect the slope of the I D -V D curve, whereas the density N ss of surface states strongly influences the slope for small drain voltages. This yields a simple and useful technique to determine N ss on MOS transistors.

Optical lithography

Abstract: This is the first in a series of papers describing a theoretical process model for positive photoresist. This model, based upon a set of measurable parameters, can be used to calculate the response of photoresist to exposure and development in terms of image surface profiles. The model and its parameters are useful in many ways, from measuring quantitative differences between different resist materials to establishment of process sensitivities and optimization of the resist process within a manufacturing system. In this paper, the concepts of photoresist modeling are introduced by following the exposure and development of a photoresist film on silicon exposed by a uniform monochromatic light flux. This very simple example provides insight into the complex nature of the photoresist process for reflective substrates. The accompanying paper, "Characterization of Positive Photoresists," gives detail about measurement of the new photoresist parameters. It is supported by "In-Situ Measurement of Dielectric Thickness During Etching or Developing Processes" which discusses automated experimental techniques needed to establish photoresist development rates. These resist parameters provide a complete quantitative specification of the exposure and development properties of the resist. They also allow quantitative comparisons: lot to lot, material to material, and processing condition to processing condition. The fourth paper, "Modeling Projection Printing of Positive Photoresists," applies the process model to one technique of photoresist exposure. This paper contains the detailed mathematics of the model. The model is then used to calculate line-edge profiles For developed resist images.

Properties of ESFI MOS transistors due to the floating substrate and the finite volume

Abstract: The specific current-voltage characteristics of epitaxial silicon films on insulator (ESFI®) SOS MOS transistors are shown, discussed in comparison to bulk silicon MOST's, and explained by the differences in geometrical considerations, charge distribution, and operation mode, The ESFI MOST's are produced on silicon islands, in most applications, the electrical substrate is at floating potential. This results in two effects. At first a threshold voltage change occurs with increasing drain voltage, producing a kink in the current curve; if the drain voltage further increases, a parasitic bipolar transistor begins to work and effects another kink or bend in the curve. On the other hand, the finite vo|ume effects a strong dependence of the base width of the parasitic bipolar transistor on the drain voltage and causes a rise of the current amplification with the drain voltage. The finite volume below the gate oxide also limits the bulk-charge magnitudes with subsequent increase in mobile carrier charge, thereby increasing the transconductance. All these effects are also described theoretically; the I D -V D characteristics could be simulated by computer model based on the physical effects.

Single- and dual-axis lateral photodetectors of rectangular shape

Abstract: A 2-dimensional diffusion model of rectagular single-and dual-axis, lateral photodiodes is analyzed and the different underlying lateral effects are discussed for the small-signal (unbiased) and fully reverse-biased modes, with either infinite terminating impedances at midlateral point contacts or zero loading impedances at extended lateral contacts For the single-axis detector with two opposite extended contacts, previous results of the 1-dimensional model appear to remain valid, and the output current difference to sum ratio in the fully reverse-biased mode is a linear function of the position of a narrow incident light beam For the dual-axis detector with extended contacts at all four sides--except for small gaps at the vertices--an approximately linear relation has been found between the light spot position along an axis and the log ratio of the corresponding output currents The transient responses of these configurations are discussed, and the utility of operation in the small-signal mode is illustrated with some typical parameter values

The mirror-matrix tube: A novel light valve for projection displays

Abstract: A completely sealed-off electron beam-addressed light valve offering high reliability, low thermal impedance, and low-voltage operation is described. It is suitable for projection displays and is capable of producing bright high-contrast images with full gray-scale range and long-term storage. The light valve is contained as the faceplate in an otherwise standard, sealed-off 1½-in diameter vidicon tube and utilizes conventional focusing and deflection components. The target, which is fabricated of refractory materials using high-yield semiconductor-processing techniques, is composed of a dense matrix (500 elements/in) of aluminized silicon-dioxide membranes (~ 3000-A thickness) which are supported centrally on small silicon posts (4-5 µm high) above a transparent sapphire faceplate. These flat, stress-free oxide membranes can be deflected electrostatically (up to 4°) when addressed with the electron beam. Thus an intensity-modulated display of the deposited charge pattern on the "mirror matrix" is produced when this type of light valve is used in conjunction with reflective schlieren optical arrangement, Mechanical and optical considerations have led to a special 4-leaf geometry of the mirror elements, enabling operation at low-voltage levels (175 V) and a high optical gating efficiency (~ 50 percent) to be achieved. Large-screen (2½-by 3½-ft) displays with up to 35-fL highlight brightness ( ×5 screen gain), 15:1 contrast ratio, and 400 TV lines resolution have been demonstrated. In addition, single-frame displays (1/30-s writetime) with full gray scale storage (of many hours) have been achieved. Preliminary studies using higher density mirror matrices (1000 elements/in) show that the display resolution can be extended to 600 TV lines/picture height.

EBES: A practical electron lithographic system

Abstract: An electron beam exposure system (EBES) has proven to be practical and economic for generating high-quality fine-featured integrated circuit masks. It is also capable of exposing patterns directly on resist-coated silicon wafers and, when so used, is an effective tool with which to develop new semiconductor devices. EBES combines continuous translation of the mask or wafer substrate with periodic deflection of the electron beam in a raster-scan mode of exposure. Substrate position is monitored by means of laser interferometers. The strategy permits both the electronic and mechanical subsystems to work well within their limits of capability and contributes to system reliability. It also permits the system to be stepped up to higher resolution and faster exposure as brighter electron sources, more sensitive resist, and faster data processing techniques are developed.

Device physics of integrated injection logic

Abstract: After a brief review of relevant device parameters, characterizing the inversely operating multicollector n-p-n transistor and the lateral p-n-p transistor which make up an I^{2}L basic cell, some electronic circuit properties of this gate are discussed quantitively. Analytic expressions are derived for the transfer characteristics, the noise margin and the propagation delay time per gate in relation to the cell geometry, fan-out, doping profiles, and recombination properties. These expressions are compared with experimental and numerical circuit simulation results.

Series resistance effects in semiconductor CV profiling

Abstract: The effects of series resistance on semiconductor doping profiles obtained by conventional CV analysis are discussed, and it is shown that this resistance can cause extremely large errors in the profiles. It is demonstrated that the existence of such errors can be inferred from suitable RF phase angle measurements obtained during the CV profiling process, and that this information can be used to correct distorted profiles. A theoretical analysis and several computer simulations are presented in order to illustrate the nature of the problem and the methods by which accurate profiles can be obtained. All of the behavior predicted by computer simulations is verified by experimental examples.

A 6 × 6-in 20-lpi electroluminescent display panel

Abstract: Over the last two years, we have been working on a solution of the solid-state display addressing problem which consists of building the addressing circuits (and eventually, also scanning or decoding circuits) directly on the panel, and fully integrated with the particular display medium. The technique utilized for this approach is that of a vacuum-deposited thin-film transistor matrix. In this paper, we report on the design, construction, and performance of a 12 000 element EL panel, suitable for alphanumeric, vectorgraphic, and monochrome TV image presentation. The basic circuit, repeated at every picture element, consists of an X-Y-addressed logic transistor, a power transistor, and a storage capacitor. The entire circuit was fabricated through multiple evaporations in a multisource system using one pumpdown cycle. The finished thin-film circuit is covered with a sprayed EL-phosphor. An evaporated Au/PbO layer forms the continuous top electrode. The entire display panel is finally sealed with a glass cover plate. Reproducible fabrication of good-quality displays was achieved, with >99 percent of the elements operational. Excellent alphanumeric displays with very few defects were demonstrated. Contrast ratios >50:1 (ON:OFF under dark ambient) were obtained. Power consumption under typical alphanumeric display conditions was below 1 W, with a peak brightness of 40 fL.

Sintered ohmic contacts to n-and p-type GaAs

Abstract: Previously, all known ohmic contacts to n-GaAs have involved a so-called "alloying" procedure which consists of melting a Au-Ge eutectic or Sn-based alloy films on GaAs. We describe here a new contact metallization scheme consisting of Pd/Ge/n-GaAs which requires sintering rather than melting in order to produce ohmic contacts. The sintering is done at temperatures ranging from 350°C, 15 min to 500°C, 2 h depending on the doping level of n-GaAs (1018-1016cm-3. For n-1016cm-3GaAs, a specific contact resistance of 3 × 10-4Ω.cm2was achieved. Sintering leads to the formation of some PdGe and intermetallics associated with the Pd/GaAs interaction, namely, PdAs 2 and PdGa. Ohmic behavior is attributed to a combination of the doping action of Ge (as donor) and fast in-diffusion kinetics of Pd. Sintered contacts to n+and p+GaAs (N D.A ∼ 1018cm-8) made by Au, Pt, and Ti Were also investigated for ohmic behavior. Each of these three metals was at least partially effective in forming ohmic contacts to p+GaAs; the degree of effectiveness increases on going from Ti to Au to Pt. It is proposed that a reasonable guideline to follow When searching for ohmic contacts is X m ≳ X d where X m is the width of the metallurgical junction and X d is the ideal depletion layer width. This condition should favor ohmic contacts by promoting a micro 3-dimensional current flow at the conductor-semiconductor interface and thereby maximizing field-emission probability.

Deep-channel MOS transistor

Abstract: A new type of ion-implanted MOS transistor is described. The transistor functions, for example, as an integrating nondestructively readable photosensor and its technology is fully compatible with the advanced MOS integrated circuits.

Surface potential equilibration method of setting charge in charge-coupled devices

Abstract: A method of setting charge in a charge-coupled device (CCD) is described whereby the input diode is suitably pulsed and an amount of charge is retained in a potential well under the first transfer electrode. It is shown that, within limits defined by the operating potentials of the device, the sizes of the generated charge packets are linearly dependent on the voltage difference between the first transfer electrode and the input gate. They are also independent of threshold voltage. The method has important applications in all CCD's where it is necessary to obtain a linear low noise charge input that is uniform from one device to another. The linearity has been demonstrated with a 64-element CCD which with a sinusoidal input shows second and third harmonics to be 40 dB down from the fundamental. Measured rms input noise was above the minimum theoretically achievable value but was still 80 dB down from the peak signal level. The electrode area was 2000 μm2. For a comprehensive review on CCD's and input circuits, see [10].

Experimental characterization of transfer Efficiency in charge-coupled devices

Abstract: The most important characteristic of a charge-coupled device is its charge transfer efficiency (CTE). There are three basic types of loss which degrade CTE: fixed loss, proportional loss, and nonlinear loss. Examples are given of each type of loss and techniques for measurement of all three types of loss are described. A method of determining the minimum fat zero which eliminates fixed loss is shown and an experiment is presented which confirms that fixed loss due to surface states can be completely eliminated by the use of a fat zero. The effect of interelectrode gaps on CTE is discussed in detail. A nonlinear loss model is used to describe the dispersion due to barriers in the gaps and the very detrimental effect of wells in the gap region is shown. The techniques presented in the analysis of these losses are very general and can be used whenever a detailed description of the transfer loss mechanism is required.

Video detection of millimeter waves with glow discharge tubes: Part I—Physical description; part II—Experimental results

Abstract: An experimental program was undertaken with the goal of realizing a fast, inexpensive millimeter wave glow discharge video detector. The work performed led to the realization of an economical commercial glow tube that, when biased properly, exhibits a sensitivity quite comparable to that of the crystal diode detector. As a result of this work, an anomalous mode plus a new mode of detection utilizing a sensing electrode external to the glow tube, with considerable improvement in NEP, were observed. In this paper, Part I describes the detection mechanism and physical characteristics of a glow discharge found to be important in the detection of millimeter waves and Part II the results of experiments concerning effects of biasing and gas type and pressure upon sensitivity.

In-situ measurement of dielectric thickness during etching or developing processes

Abstract: A system has been developed which permits the measurement of dielectric film thicknesses in-situ during development or etching processes. This can be extended to growth or deposition processes. Two examples of its uses are presented: the determination of the thickness of phosphosilicate glass layers on silicon dioxide coated silicon wafers by making use of the etch rate differences, and the monitoring of photoresist thickness during development to characterize the photoresist development process.

Modeling of an ion-implanted silicon-gate depletion-mode IGFET

Abstract: A dc model is-presented for the ion-implemented silicon-gate depletion-mode IGFET from which the device terminal behavior can be determined. The device equations are derived based on the concept of a finite semiconductor capacitance in the channel region whereby the depth of the implanted channel is taken into account. The model parameter is shown to be easily measurable experimentally. The validity of the resulting model is demonstrated by showing good agreement between calculated and measured results obtained from fabricated devices, It is believed that this model lends itself well to the circuit design problem using depletion mode IGFET's.

InP Schottky-gate field-effect transistors

Abstract: MESFET's with gates 1 µm long were fabricated in LPE layers of InP on Cr-doped InP substrates. The quality of the LPE material is characterized by an electron concentration of 4 × 1015cm-3with a mobility of 2.6 × 104cm2V-1s-1at 77 K for growths from undoped melts. The devices have current gain cutoff frequencies of 20 GHZ or somewhat larger. This value is greater than that of the best analogous GaAs MESFET bya factor of 1.5. A factor of 1.3 is predicted on the basis of a simple theory. The highest power gain cutoff frequency, f max , for the InP device is 33 GHz which is somewhat smaller than that of the best analogous GaAs device. The lowest minimum noise figure at 10 GHz for these first InP devices is 3.9 dB with an associated gain of 4.8 dB. The best result for the GaAs counterpart is 3.2 dB with an associated gain of 7.8 dB. The power gain of the InP device suffers compared to the GaAs device because of degenerative feedback resulting from a large gate-to-drain capacitance and because of a small output resistance. If the magnitudes of these two equivalent circuit elements were the same for MESFET's in the two materials, f max for the InP device would be more than double its present value.

Microwave properties of nonlinear MIS and Schottky-barrier microstrip

Abstract: It is shown that metal-insulatior-semiconductor (MIS) and Schottky-barrier microstrip structures having substrate resistivities within a certain range propagate slow waves with phase velocities that are dependent upon the instantaneous voltage at each point along the line. This and other useful properties of these microstrips can be used advantageously in a number of microwave devices. Loss measurements for the MIS microstrip structure confirm the predictred frequency dependence of the attenuation constant. While the levels of measured attenuation presently achieved are fairly high (4.5 dB/cm at 1 GHz), several methods for reducing the attenuation are proposed. A number of devices are discussed, including an electronically variable phase shifter for which attenuation and phase-shift measurements are presented.

A magnetic-particles display

Abstract: A new type of flat-panel ambient-illuminated display is described. Images in this display are formed by magnetically controlling the orientations of small spherical multicolored magnetic particles. A demonstration model is shown and the possibility for application to television is studied. It is estimated that for a 9 × 12-cm black-and-white screen with built-in magnetic memory and 500 × 500 sequential matrix addressing the display panel can be driven at TV rates with an average current of 0.27 A and dissipation of 0.26 W. Contrast ratios up to 40:1 seem achievable with continuously variable grays. The display also features a nonvolatile memory which can be very desirable for some applications. Methods for fabricating this display are also discussed.

Reduction of photoresist standing-wave effects by post-exposure bake

Abstract: A process is described for reducing the residual effects of standing waves upon exposed and developed lines in positive photoresist films.

Liquid phase epitaxy of GaP by a temperature difference method under controlled vapor pressure

Abstract: A series of experiments have been done in which the properties of GaP grown by liquid phase epitaxy (LPE) have been varied by providing an additional source of phosphorus via the vapor phase. The quality of the crystals, as judged from gross defect features observed in etched cross sections, is a function of the amount of phosphorus added to the vapor phase.

Bipolar transistor modeling of avalanche generation for computer circuit simulation

Abstract: An avalanche generation model is developed and incorporated into computer circuit analysis programs SLIC and NICAP. A modified form of Miller's empirical expression for generation is found to agree well with measured data for Western Electric and commercial n-p-n transistors. Measurement techniques and parameter determination for the three model coefficients are discussed. Equation constraints appropriate for computer implementation are presented.

Limitations of the CV technique for ion-implanted profiles

Abstract: The CV profiling technique is reviewed and its validity and limitations are investigated, with special attention given to the case where the method is extended to the study of ion-implanted impurity distributions. A theoretical analysis is described which yields information about the dependence of CV measurements on impurity profile. The inverse problem is then considered and the results demonstrate that the depletion approximation formulas commonly used for the reduction of CV data to give doping profiles are misleading when applied to substrates with rapidly varying profiles as are generally the case for ion-implanted substrates. Examples of the profiles obtained for various shaped impurity distributions are given.

Calculation of the diffusion curvature related avalanche breakdown in high-voltage planar p-n junctions

Abstract: Avalanche multiplication calculations are performed in high-voltage planar p-n junctions to determine breakdown voltage limitations imposed by curvature effects. The issue of choice of ionization coefficient for avalanche multiplication is discussed. From the calculations, a series of design curves and equations are generated which relate the breakdown voltage and peak electric field to those of an ideal junction of the same doping profile, the critical parameters being the substrate doping concentration, the diffusion profile, and the ratio of the radius of curvature to the substrate depletion width for the ideal one-dimensional case. With appropriate distance normalization, these curves and equations can be reduced to a single curve and a single equation. The agreement between theory and experiment is consistently good provided the correct ionization coefficients are used in the theory.

Two-dimensional computer simulation for switching a bipolar transistor out of saturation

Abstract: A two-dimensional numerical analysis for the turnoff of a bipolar transistor from high injection level (V BE = 900 mV) is carried out. V BC is being kept constant at 1 V. Distributions of potential, electron, and hole density are interpreted and lead to a subdivision of the total transient time into four time regions, each governed by a single phenomenon. These phenomena are 1) fast discharge of the sidewall transistor, 2) the "lateral wave" which has the dominating influence in the total switching time, 3) the vertical discharge, and 4) the emitter discharge. The transient behavior is essentially ruled by two-dimensional lateral effects. Hence one-dimensional models are not adequate for switching a transistor out of saturation.

High speed replication of submicron features on large areas by X-ray lithography

Abstract: To achieve the high throughput necessary for a practical X-ray lithographic system, we have devised a new overall approach to X-ray lithography based on the use of X-rays with wavelengths of 4-6 A rather than the 8.34-A wavelength used in previous work. The principal advantage of the shorter wavelengths is that they allow a system to have X-ray windows so that large area patterns can be replicated under ambient conditions. In addition, the shorter wavelengths simplify the selection of mask substrate materials; thus we have developed a new X-ray mask structure using an optically transparent Mylar substrate. This permits realignment to be done by optical means. We also report results obtained with a new negative resist with high sensitivity to the shorter wavelength X-rays. We have achieved the replication of submicron size features using a 4.6-A rhodium X-ray source, a Mylar mask with 7000-A thick gold patterns, and the new resist, and have demonstrated the practicality of this system by the fabrication of propagating magnetic bubble structures with small features.