Showing papers in "IEEE Transactions on Electron Devices in 1976"
TL;DR: The design of two-dimensicn circuit assemblies, a novel design in which ceramic wafers with one to four passive components per wafer were stacked and interconnected with vertical riser wires, was developed.
Abstract: T BACKGROUND HE FIRST electronic equipments were composed of a few dozen components and could readily be asselnbled by hand-soldering techniques. Each component mas manufactured separately by a process optimized for the purpose. As electronic equipment became more complex, shortcomings in this procedure began to appear. The cost of the equipment increased more rapidly than the cornponent count, and equipment reliability suffered a corlesponding decrease. Because of their interest in complex electronic system, the problem was particularly apparent to the militav y. Each B-29 required nearly a thousand vacuum tubes a ~ l d tens of thousands of passive devices. Its electronics equipments were among the most complex systems in being at the time. By the end of World War I1 it was apparent that future systems would be limited by the cost, bulk, and reliability of the electronics. One of the first attempts to simplify the manufacturing process was carried out under National Bureau of Sta’qdards sponsorship. Their proximity fuse requirements necessitated compact rugged electronic subsystems. The Centralab Division of Globe-Union, Inc. proposed a design in which ceramic substrates would carry metal interco:?nections and chip capacitors, with miniaturized vacuum tubes attached. This proposal was developed by Rubenstein, Ehlers, Sherwood, and White of Centralab [l], and was probably the first attempt to form components in sit^ After the war, NBS and Centralab continued to work in this area. The Centralab effort, under R. L. Wolff and A. S. Khouri, developed high-volume screening techniqu(3s for production. Centralab built substantial quantities ~ a f amplifiers for hearing aid applications, with several dozen passive components and three or four tube sockets for active device attachment. They further simplified the concept by the use of a substrate with a high dielectric constant, permitting the fabrication of low cost RC net,works for radio and television applications. About 14.0 million circuits of this type were produced by 1962. The NBS effort, originally led by Brunetti and later by Franklin , also continued to develop two-dimensicn (2-D) circuit assemblies. A complete in-house fabricatien capability was established. In the early 1 9 5 0 ’ ~ ~ Robe::t Henry of this group, working under Navy sponsorshila, abandoned the 2-D concept and produced a novel design in which ceramic wafers with one to four passive components per wafer were stacked and interconnected with vertical riser wires. A tube socket was mounted above tk.e
TL;DR: In this paper, two mechanisms have been found to be responsible for the changes in barrier height: 1) the removal of positive charges from the oxide, and 2) metallurgical reactions between the Al and Si.
Abstract: Experimental observations (electrical characteristics and in depth Auger analysis) have been made of the interface behavior in aluminum-silicon contacts. The barrier heights of these contacts (φ bn for n-type, φ bp for p-type silicon) are sensitive to heat treatments (HT) that are a part of normal integrated circuit processing. If oxide layers (≃20 A) are present in the Al-Si interface, φ bn can be as low as 0.45 eV and φ bp as high as 0.75 eV. One can obtain reproducible barrier heights φ bp ≃ 0.7 eV and φ bp ≃ 0.5 eV by HT at T ≤ 300deg;C. As the temperature of HT is increased (up to ≃ 550deg;C) φ bn can reach ≃ 0.9 eV and φ bp drop to < 0.35 eV. The HT at higher temperatures are accompanied by changes in the Al and Si profiles across the interface region. Two mechanisms have been found to be responsible for the changes in barrier height: 1) the removal of positive charges from the oxide, and 2) metallurgical reactions between the Al and Si. These two mechanisms have been separated and their individual behaviors qualified.
TL;DR: In this article, a new idea for using a protecting layer over the dielectric layer which isolates the electrodes from the gas was examined and good results were obtained, besides stability, a considerable improvement of operating characteristics was achieved, including lowvoltage operation capability.
Abstract: One of the important problems in the development of ac plasma panels is to produce panels that maintain stable characteristics for a long time. A new idea for using a protecting layer over the dielectric layer which isolates the electrodes from the gas was examined and good results were obtained. Moreover, besides stability, a considerable improvement of operating characteristics was achieved, including low-voltage operation capability. Sputtering of the protecting layer, which is thought to govern the life of plasma panels, occurs even to heat-resisting oxides of large binding energy, but the sputtering rate appears to be so slow that it hardly affects the panel life. Also, the rate of decomposition accompanying sputtering is small. The problem of cracks in the protecting layer, which is the cause of defective life characteristics in such respects as migration of the lead component of the dielectric layer onto the protecting layer and the direct exposure of the dielectric-layer glass to the discharge, was solved by process-technique improvements. This paper describes the merit of using a protecting layer, required performance for this layer, and experimental results, and discusses voltage stability and the results of selection of materials for it.
TL;DR: In this paper, a cross-sectional view of a CMOS RAM with poly-Si gates and tungsten second metal was obtained by using transmission electron microscopy (TEM).
Abstract: Accurate cross-sectional views of large scale integrated circuits are useful for failure analysis and process evaluation. We have successfully prepared thin sections of finished devices cut perpendicular to the plane of the chip and examined them using transmission electron microscopy. We describe the sectioning procedure and show some cross-sectional views from memory cells of a CMOS RAM with poly-Si gates and tungsten second metal. Examples include micrographs of sections through 1) an IGFET showing the gate edges and the poly-Si grain size distribution, 2) metal to Si, and metal to poly-Si contacts, and 3) poly-Si runners. Each circuit element examined was uniquely identified by mapping the cross section through adjacent memory cells and noting the sequence of elements intersected. This demonstrated ability to examine cross sections of finished devices, consisting of multilayers of materials with different densities, hardness, etc., should prove useful whenever detailed device geometries, crystalline structures, etc., need to be examined in a manner which is relatively free of experimental artifacts.
TL;DR: In this article, it is pointed out that the few milestones related in this article are only those that at the present time the writer feels are more important, without implying completeness or even absolute soundness in his judgment in selecting them.
Abstract: T HAS been less than seventeen years since D. Kahng and M. M. Atalla [l] of Bell Telephone Laboratories reported the first demonstration of an Si-Si02 MOS transistor. Even so, the annual sales of MOS based semiconductor components are expected to surpass one billion dollars in the U.S. alone. The impact on our daily lives imparted by these MOS based IC’s is just beginning to be felt. This tremendous explosion has been caused by many innovations and countless numbers of perhaps small but indispensable contributions by many unsung heroes. It is clear then that to list every single landmark, every twist and turn on the road would be just about impossible, even if one had unlimited time to dig into the history and unlimited space in this issue to describe them. It is hoped then that readers will understand that the few milestones related in this article are only those that at the present time the writer feels are more important, without implying completeness or even absolute soundness in his judgment in selecting them. It should also be remarked that what can now be recognized as the more significant milestones did not necessarily stand out and appear so at the times they occurred. Long before the invention of the transistor, the so-called “field. effect,” that is, a conductance change in a solid induced by application of transverse electric field, was the subject of intensive studies by various people. In fact, in the course of these studies, the discovery of transistor action itself was made . As early as the 1920’s and 1930’s, proposals ,  on amplifying devices based on “field effect” were made, however, with little apparent understanding of the physical phenomena. An unequivocal demonstration of the field effect was made by Shockley and Pearson in 1948 in their classic paper  in which they showed that an appreciable modulation of conductance in the surface region of a semiconductor occurred. The “field effect“ was subsequently applied to various but essentially similar amplifying device configurations by numerous people. These devices, however, relied on what was recognized as majority (carrier modulation. That is, the transverse electric field caused the majority carrier density to be modulated in a semiconductor bar which in turn resulted in conductance changes between two suitably located ohmic contacts. It is straightforward to show that useful devices based on this principle are achievable only under severe geometrical restrictions. Namely, the ratio
TL;DR: In this paper, it was shown that with increasing γ i of the dielectric panel material the firing voltage of an ac gas discharge display panel decreased, under the condition that the secondary electrons became greater than unity and unstable self-sustained emission was observed.
Abstract: From the measurement of the ion-induced secondary electron emission yield γ i it was shown that with increasing γ i of the dielectric panel material the firing voltage of an ac gas discharge display panel decreased. The measurement of the energy distributflon of the secondary electrons showed that the dielectric material with higher γ i has lower most-probable energy (MPE), and half-width (HW) values. The energy distribution introduced by Stolz in the ease of secondary electrons emitted from a metal was applied to the dielectric panel material and solved by using a computer. From this result, it was shown that the lower the electron affinity of the dielectric panel material, the higher is the γ i . Under the condition when γ i became greater than unity, unstable self-sustained emission was observed even though the primary ion beam was cut off.
TL;DR: In this paper, the idealized concept of thermal resistance as applied to power transistors is discussed and various electrical methods for measuring the junction temperature (thermal resistance) of transistors with the emphasis placed on the emitter-only switching measurement technique, which is the preferred standard method of measurement.
Abstract: The idealized concept of thermal resistance as applied to power transistors is discussed. This concept must be used with care because two of the basic assumptions made in applying the concept to these devices are not valid. Contrary to these assumptions, it is shown that 1) the junction temperature of a power transistor is never spatially uniform, and 2) no unique value of thermal resistance can be defined for all operating conditions. Also, various electrical methods for measuring the junction temperature (thermal resistance) of power transistors are discussed with the emphasis placed on the emitter-only switching measurement technique, which is the preferred standard method of measurement. In addition, the generation and meaning of forward-biased safe-operating-area (SOA) limits are discussed, and it is shown that because of the presence of current crowding and the associated hotspots, the specified SOA limits often permit devices to be operated at dangerously high junction temperatures. Electrical measurement methods capable of determining the peak junction temperature as well as determining the onset of current crowding are described, and it is shown how these methods might be used for the generation of improved SOA limits.
TL;DR: In this article, a two-dimensional finite-element simulation of a GaAs MESFET is presented to determine the drain current and transconductance as well as the two dimensional voltage, electron density, and electric-field distributions.
Abstract: Results of a two-dimensional finite-element simulation of a GaAs MESFET are presented. The simulation is used to determine the drain current and transconductance as well as the two-dimensional voltage, electron density, and electric-field distributions. It is shown that placement of a compensated doping region in the high electric-field region between gate and drain increases the drain current and transconductance by reducing the velocity-saturation effect. The transconductance and drain conductance of the MESFET in the saturation region of devices having different channel heights are compared with previous analysis.
TL;DR: The n-p-n and p-n-p high-voltage transistors were developed by using semi-insulating polycrystalline-silicon (SIPOS) films for the surface passivation as discussed by the authors.
Abstract: The n-p-n and p-n-p high-voltage transistors showing high reliabilities have been developed by using semi-insulating polycrystalline-silicon (SIPOS) films for the surface passivation. SIPOS films are chemically vapor-deposited polycrystalline-silicon doped with oxygen or nitrogen atoms. The films employed for the surface passivation of high-voltage transistors are composed of triple layers, which are oxygen-doped SIPOS films of 0.5-µm thickness to stabilize the silicon interface, nitrogen-doped SIPOS films of 0.15-µm thickness to prevent water or sodium ions from reaching the silicon surface, and silicon dioxide films to prevent dielectric breakdown of the SIPOS films under very high-voltage operation. The n-p-n and p-n-p SIPOS transistors rated at 800 and 2500 V have been produced in planar-like structures with field-limiting rings. These transistors showed highly reliable characteristics, because the passivating SIPOS layer provides a good protection against ionic contamination and externally applied electric fields. Furthermore, 10-kV n-p-n SIPOS transistors with multiple rings have been fabricated and found that operation is stable.
TL;DR: In this article, a two-dimensional numerical analysis of GaAs junction-gate FET's is performed and it is found that a GaAs FET exhibits either of the following three types of characteristics depending upon device geometry and doping concentration.
Abstract: Stability criteria of GaAs junction-gate FET's are studied by two-dimensional numerical analysis. The analysis covers the wide range of device geometry from the state of the art FET to the so-called Gunn effect digital devices. It is found that a GaAs FET exhibits either of the following three types of characteristics depending upon device geometry and doping concentration. First, for a thin channel with high doping concentration, the device tends to behave as a normal junction-gate FET with saturating current-voltage characteristics. This is even true when the n-l (device length) and n.d (device thickness) products exceed the previously accepted criteria for Gunn oscillation. Second, a stable negative resistance (SNR) is observed in devices with a moderate channel thickness. Third, for a thick channel, the device exhibits a Gunn oscillation with the domain propagating from the gate edge to the drain. These three categories of behavior are mapped on the nd plane with the help of simple analytic considerations. The map is found to compare well with experimental results.
TL;DR: Bardeen and Brattain this article proposed a surface-state shield that blocked the field from the semiconductor's interior, but this shield failed after only six days and was replaced by the junction transistor.
Abstract: The failure in 1945 of experiments proposed by Shockley, on what today would be called thin-film field-effect transistors, was a creative failure that stimulated Bardeen in early 1946 to propose that a surface-state shield blocked the field from the semiconductor's interior. Bell Laboratories' "transistor group to be" for the next eighteen months focused, not on practical, but on scientific aspects of the failure. Focus on the practical resumed (with a step-function increase, lasting several months, in "the will to think" about new concepts of semiconductor amplifiers, as measured by the rate of filling of laboratory notebook pages by Bardeen, Brattain, and Shockley) on 17 November 1947, when in his surface-state research, Brattain penetrated the shield by applying the field through an electrolyte. Within six days, patentable field-effect transistor inventions were conceived. Although useless as devices, these inventions were creative failures used by Bardeen and Brattain to discover the point-contact transistor three weeks later. Five weeks after this discovery, Shockley conceived the junction transistor while designing "imref" experiments on the point-contact transistor's inversion layer so that in 1951, the point-contact transistor in its turn became a creative failure when replaced by the junction transistor whose conception it had aided. But the path of thought to the conception of the junction transistor and the subsequent path to its practical realization are proven to be highly indirect by historical research on laboratory notebook entries. Specifically, Shockley's conception of the junction transistor was delayed by at least four months because he missed opportunities, obvious by hindsight, to recognize the possibility of minority carrier injection. The author hopes that the presentation of details of his limitations in making this important invention may help readers to accept their own limitations and, thereby, to become more persistent and, hence, creative.
TL;DR: In this article, a two-dimensional mathematical model is developed to predict the internal behavior of power transistors operating under steady-state conditions, which includes the internal self-heating effects in the transistors and is applicable to predict transistor behavior under high current and high-voltage operating conditions.
Abstract: A two-dimensional mathematical model is developed to predict the internal behavior of power transistors operating under steady-state conditions. This model includes the internal self-heating effects in power transistors and is applicable to predict the transistor behavior under high-current and high-voltage operating conditions. The complete set of partial differential equations governing the bipolar semiconductor device behavior under nonisothermal conditions is solved by numerical techniques without assuming internal junctions and other conventional approximations. Input parameters for this model are the dimension of the device, doping profile, mobility expressions, generation-recombination model, and the boundary conditions for external contacts. Computer results of the analysis of a typical power transistor design are presented for specified operating conditions. The current density, electrostatic potential, carrier charge density, and temperature distribution plots within the transistor structure illustrate the combined effect of the electrothermal interaction, base conductivity modulation, current crowding, base pushout, space charge layer widening, and current spreading phenomena in power transistors.
TL;DR: In this paper, it is shown that Implanted-diffused As layers in Si have been well-characterized and have been used in fabricating lowvoltage n-p junctions.
Abstract: Implanted-diffused As layers in Si have been well-characterized and have been used in fabricating low-voltage n-p junctions. It is shown that these As layers form linearly graded junctions with a uniform B-doped background (ρ ≃ 0.006 Ω.cm). The grade constant of the As profile at the junction is known sufficiently well as a function of As dose, diffusion time, and temperature to allow quantitative use of existing tunneling and avalanche theories for the calculation of the reverse I-V curves. Following a verification of the calculated I-V curves and their temperature dependence as a function of grade constant, calculated curves are presented which correlate As implant dose and diffusion with junction breakdown voltage, breakdown impedance, and temperature coefficient of reverse voltage. The temperature coefficient is shown to change from negative to positive as the transition from tunneling to avalanche occurs. In addition, the relative importance of tunneling and multiplied-generation current as a function of current density is elucidated for any particular As layer grade constant.
TL;DR: In this article, the authors discuss the early history of gas discharge displays and their contributions to both forms of display with particular emphasis on the conception and early history in the ac display.
Abstract: Gas discharge displays (or plasma displays, as they are now frequently called) have evolved into two distinct forms. In dc displays, exciting electrodes are immersed in the gas, and currents are usually unidirectional. In ac displays, electrodes are separated from the gas by dielectrics. Contributions to both forms of display are discussed with particular emphasis on the conception and early history of the ac Display.
TL;DR: The transistor was discovered at Bell Laboratories in 1947, but only a few even within the Labs who knew about it for some months due to a decision of management to maintain close security for a period as mentioned in this paper.
Abstract: HEN the transistor was discovered at Bell Laboratories there were few even within the Labs who knew about it for some months due to a decision of management to maintain close security for a period. John Bardeen and Walter Brattain [l],  made their earthshaki:ng observations on December 23,1947; the first public demo’nstration of the invention and announcement of the discovery was not made until June 30,1948. In the interim period only those who were assigned to the project by research management were told the facts. I was at Bell Labs at this time and had been there for many years. Though I was not in the physics semiconductor group, I learned a bit about the invention in the early part of 1948, due to my having deposited pyrolytically. silicon, germanium, and germanium-silicon alloy films on ceramic tubes during World War 11. Some of these experimental samples turned out to be of interest to Shockley in trying some of his ideas of how to make a field-effect tramistor. Bardeen and Brattain’s discovery was very exciting news, perhaps even more so for me than for many others because I had long nourished an interest in germanium. that had started with my undertaking graduate study a t Brown University under Prof. Charles A. Kraus, American Chemical Society president, and Willard Gibbs, Franklin and Priestley Medalist, who was one of the two outstanding U. S. experts on germanium at that ime. My master’s and doctor’s theses were on germanium. It was a material studied only for its scientific interest; its complete uselessness fascinated’ and challenged me. My concentration on this shiny metallic-appearing material during my graduate school days resulted in a continuing personal sentimental attachment for germanium, which, to me, a t least, was and is an exotic element. This deep but little known personal attachment influenced me from time to time over an eighteen-year period after leaving Brown University to seek some way of capitalizing on this knowledge and interest acquired years before. The opportunity to enter a career of creative research and innovation, concerned particularly with electronic materials, I owe to Dr. Robert R. Williams and Dr. Robert M. Burns, who headed Bell Labs chemical research. When they invited me to come to work at Bell Laboratories, I accepted and went there in 1930. M.y initial studies a t Bell began as a member of the Chemical Research Department. In 1933 I transferred to the Electro-Optical Department reporting to its head,
TL;DR: The most closely guarded secret in England at that time was the fact that a chain of radar stations had been br: ilt along the country's east and south coasts for the detection of approaching aircraft, and those of us who had Brit.number.
Abstract: number.of exciting names; but it was to be a nuclear physics laboratory wi t‘h a 60-in cyclotron and not a microwave laboratory. In fsct there was really no interest in microwaves until the SUI:EImer of 1939. Such new words as klystron, rhumbatron, and velocity modulation arose in papers by Hansen and the Varian Brothers, and these intriguing new concepts wcre discussed at colloquia in the department. This interest would almost certainly have been juw a passing phase had it not also been painfully obvious t‘k at what is now called the second world war was about to br1ea.k out and that all thought of building the cyclotron wol..Id have to be put aside. The most closely guarded secret in England at that tjiine was the fact that a chain of radar stations had been br: ilt along the country’s east and south coasts for the detection of approaching aircraft, and those of us who had Brit. Eih nationality were told of its existence by Oliphant, who Itlad visited one of these secret stations with Cockroft, of .Ihe Cavendish, and with Appleton and Tizard and Wats“~Watt. Moreover, we were invited to spend six weeks of Ihe summer vacation at one of these stations but “would. vve please not tell anyone about it!” Such was security th!m. War did start within a month of joining our radar sttit.ion but during this time we had complete access to all d-~e circuit diagrams and were even allowed to switch off to make minor modifications, which of course always m.de its performance worse. But now we were all interested in the possibility of producing microwaves. We had seen how very large pon c:rs at 10-m wavelength could be produced by pulsed operation of relatively small tubes, and the prospect of doing thii3 at microwave frequencies for airborne and shipborne use was most exciting, but apparently impossible. So we all returned to Birmingham to try.
TL;DR: In this article, it is shown that radioactivity problems do not interfere for resistivities above approximately 5 Ω-cm and that lattice radiation defects can be annealed out to the extent that they appear harmless for all major applications.
Abstract: The limitations of conventional melt doping of phosphorus in silicon are discussed in relation to the obtainable homogeneity. Due to "theoretical-design" possibilities and increased manufacturing yield for power components based on n-type silicon, the method of thermal neutron irradiation doping has been developed for large scale production of floatzone silicon of homogeneous resistivity. It is shown that radioactivity problems do not interfere for resistivities above approximately 5Ω- cm and that lattice radiation defects can be annealed out to the extent that they appear harmless for all major applications. The doping homogeneity is discussed in view of the influencing nuclear reactor characteristics and the choice of starting material. Doping variations less than 1 percent across slices of up to 80-mm diameter are demonstrated to be obtainable with production results typically 3-10 percent. The minority carrier lifetime of neutron-doped silicon is shown to lie in the range of 100-1000 µs.
TL;DR: In this article, the write and erase properties of a rewritable and nonvolatile avalanche-injection-type memory are investigated and the memory transistor has the stacked-gate structure of a floating gate and a control gate, which reduces the avalanche breakdown voltage of the drain junction and accelerates electron injection into the floating gate.
Abstract: Design theory and experimental results of the WRITE and ERASE properties of a rewritable and nonvolatile avalanche-injection-type memory are reported. The memory transistor has the stacked-gate structure of a floating gate and a control gate. The threshold-voltage shift of the transistor due to injected charge is controlled by applied potential on the control gate which reduces the avalanche breakdown voltage of the drain junction and accelerates electron injection into the floating gate. The writing time is about 20 µs for a single transistor and is less than 5 s for a fully decoded 2048-bit memory with appropriate duty cycles of programming pulses. Erasure of the memory is accomplished either by ultraviolet light irradiation onto the floating gate or by electric field emission of electrons from the floating gate to the control gate. Electrical erasing is theoretically analyzed and successfully compared with experimental results on the 2K bit memory. Memory retention is also investigated and a charge-escaping model is proposed.
TL;DR: In this article, it was shown that the barrier height of metal-thin insulator-p-silicon diodes can be greatly enhanced by the presence of positive charge in the interfacial layer.
Abstract: Calculations are presented which indicate that the barrier height of metal-thin insulator-p-silicon diodes can be greatly enhanced by the presence of positive charge in the interfacial layer. Application of the model to recent MIS silicon solar cell data suggests that oxide charge densities of 3-4 × 1012charges.cm-2could be responsible for the high performance of the reported cells.
TL;DR: In this paper, a new type of voltage breakdown occurring in high-voltage D-MOS transistors is described, which is due to an avalanche phenomenon appearing close to the n+region, due to the very high field induced in this NIOS structure in nonequilibrium.
Abstract: A new type of voltage breakdown occurring in high-voltage D-MOS transistors is described. This effect severely reduces the high-voltage capability of these devices when the gate field plate is extended through the drift region toward overlapping the n+drain contact region. The breakdown is shown to be due to an avalanche phenomenon appearing close to the n+region, due to the very high field induced in this NIOS structure in nonequilibrium. A first-order theory is developed to confirm the conclusions of the experimental study.
TL;DR: In this paper, a design consideration for an X-band GaAs power FET, features of the fabrication process, and electrical characteristics of the FET are described, and the resulting devices can produce 0.7-W and 1.6-W saturation output power at 10 GHz and 8 GHz, respectively.
Abstract: A design consideration for an X-band GaAs power FET, features of the fabrication process, and electrical characteristics of the FET are described. Interdigitated 53 source and 52 drain electrodes and an overlaid gate electrode for connecting 104 Schottky gates in parallel have been introduced to achieve a 1.5-µm-long and 5200-µm-wide gate FET. A sheet grounding technique has been developed in order to minimize the common source lead inductance (L 8 = 50 pH). The resulting devices can produce 0.7-W and 1.6-W saturation output power at 10 GHz and 8 GHz, respectively. At 6 GHz, a linear gain of 7 dB, an output power of 0.85 W at 1-dB gain compression and 30-percent power added efficiency can be achieved. The intercept point for third-order intermodulation products is 37.5 dBm at 6.2 GHz.
TL;DR: In this article, an anistropic etching in ternary mixtures of KOH, H 2 O, and ethyl glycol is used to create SiC nucleation sites, which in turn facilitates the formation of a tetrahedral structure on the cell surface.
Abstract: High-efficiency silicon solar cells have been reported that use a surface alteration to reduce reflection. The process here reported purposely alters the cell surface with an anistropic etching in ternary mixtures of KOH, H 2 O, and ethyl glycol. Wafers were "sensitized" with a carbon compound to insure etching uniformity. It is suggested that the organic compound creates SiC nucleation sites, which in turn facilitates the formation of a tetrahedral structure on the cell surface. This structure promotes multiple interaction of the light beam between millions of pyramids per square centimeter on the surface. The surface geometry increases the light absorption and reduces reflectivity, thus increasing the cell efficiency.
TL;DR: In this article, a model for the drain conductance of J-FET's in the hot electron range is proposed based on a physical picture revealed through two-dimensional numerical analysis, which shows that the electron concentration changes gradually at the boundary of a depleted region which is defined by a conventional theory.
Abstract: A new model is proposed for the drain conductance of J-FET's in the hot electron range. The model is based on a physical picture revealed through two-dimensional numerical analysis. The two-dimensional analysis shows that the electron concentration changes gradually at the boundary of a depleted region which is defined by a conventional theory. Because of this gradual change, electrons can remain after the pinch-off and contribute to the drain current. Although the high electric field causes the electron velocity to saturate, the drift velocity vector rotates into the x axis (source-to-drain) with the increase in the drain voltage. The increase in the x component V x of the drift velocity gives rise to a small increase in drain current, that is, a finite drain conductance. The proposed model takes into account the above two essential features, gradual change in electron distribution, and the rotation of the velocity vector. This model is constructed in a single formulation which describes the current-voltage characteristics from the linear to the saturated drain-current region. Theoretical calculations agree quite well with the experiment on GaAs Schottky barrier gate FET's.
TL;DR: In this article, it is shown that the reverse bias second breakdown potential of a transistor is completely specified by the single parameter V p which is the voltage necessary for avalanche injection, and that the filamentary currents that result from this can in most cases result in device failure.
Abstract: Second breakdown in power transistors continues to be an actively discussed subject. Although there is general agreement that the lateral thermal instability model adequately explains forward bias second breakdown, it fails to explain the reverse bias failure mechanism. The thermal initiation and electrical initiation processes have been successful in explaining only some aspects of this phenomena. This paper studies the subject of reverse bias second breakdown both experimentally and analytically. It is seen that there is excellent correlation between theory and experiment. The conclusion of this investigation is that avalanche injection is the triggering mechanism. Further, the filamentary currents that result from this can in most cases result in device failure. It is also concluded that under fixed circuit conditions, the reverse bias second breakdown potential of a transistor is completely specified by the single parameter V p which is the voltage necessary for avalanche injection.
TL;DR: In this paper, a 2-SCR-3-diode controlled bridge was used as a 2hp dc motor speed control for a 2.5-DOF DC motor.
Abstract: A new technique of bonding copper directly to ceramic, employing the copper-copper oxide eutectic melt, is described. Scanning electron micrographs (SEM) and EDAX are used to study the details of this bond. A specific utilization of these techniques is portrayed in a 2-SCR-3-diode controlled bridge. This bridge is used as a 2-hp dc motor speed control. The advantages of using these techniques over previous methods (thick film or moly-manganese) lie in the ability to bond almost any thickness of high-conductivity copper to ceramics (Al 2 O 3 , BeO, BN, ZnO, etc.) silica, dissimilar metals, or to copper itself. Incidental benefits, described in the report, include bonding copper lead frames instead of screen printing, lack of high thermal and electrical resistivity interface layers, and simplicity of manufacture. Ceramic properties found to influence bond quality were: 1) Topology in terms of a fractured surface due to lapping and/or die sticking. 2) Degree of intergranular bond strength. 3) Cleanliness of surface and degree of unbonded particulate matter (powder) on the surface. 4) Grain size. The bonding agent is characterized as a field of bonded Cu 2 O nodules precipitated from the Cu-Cu 2 O eutectic melt with a density much higher than expected from the 4.7-percent Cu 2 O (by volume) contained in the eutectic mixture. Mechanisms to explain this behavior are described. The bond strength is noted to depend on the nodule density and the bond strength of the Cu 2 O to copper and is higher than any other bonding method.
TL;DR: In this paper, the design considerations for charge-transfer split-electrode transversal filters are discussed, and the relationship of these parameters to filter performance and accuracy is described.
Abstract: Some of the design considerations for charge-transfer split-electrode transversal filters are discussed. Clock frequency, filter length, and chip area are important design parameters. The relationship of these parameters to filter performance and accuracy is described. Both random and tap weight quantization errors are considered, and the optimum filter length is related to tap weight error. A parallel charge-transfer channel, which balances both capacitance and background charge, and a coupling diffusion between split electrodes greatly improves accuracy. A one-phase clock is used to simplify the readout circuitry. Two off-chip readout circuits are described, and the performance of two low-pass filters using these readout circuits is given. Signal to noise ratios of 90 dB/kHz and an overall linearity of 60 dB have been achieved with this readout circuitry.
TL;DR: In this article, the authors established guidelines to determine, for a given device type, which lifetime killer should be used to provide optimal performance when compared to gold and showed that when the switching wave form involves low injection recombination tails, gold is a better choice than platinum when the turnoff is governed mainly by the high injection lifetime.
Abstract: Both platinum and gold have been used to reduce lifetimes in fast recovery silicon power devices. There are substantial differences between the energy levels introduced by these impurities. Both impurities introduce acceptor levels which act to reduce hole lifetimes in n-type silicon; however, the gold acceptor is much deeper (E c - 0.54 eV) than the corresponding platinum acceptor (E c - 0.26 eV). In p-type material, on the other hand, the two impurities are quite similar; gold introduces a donor at E v + 0.35 eV, while the platinum donor is at E v + 0.32 eV. In terms of basic physics, this paper establishes guidelines to determine, for a given device type, which lifetime killer should be used to provide optimal performance. Platinum offers improved high-temperature properties and turn-on performance when compared to gold and is a better selection for devices which are switched so rapidly that the turn-off is governed mainly by the high injection lifetime. However, when the switching wave form involves low injection recombination tails, gold is a better choice than platinum.
TL;DR: In this article, the photovoltage and photocurrent of a strongly illuminated p-n junction solar cell were derived by solving the ambipolar diffusion equation, and a complete boundary condition was derived for the junction, which was valid for all levels of injection.
Abstract: Expressions for the photovoltage and photocurrent of a strongly illuminated p-n junction solar cell are derived by solving the ambipolar diffusion equation. A complete boundary condition is derived for the junction, which is valid for all levels of injection. In the open-circuit case, results are in agreement with those given by earlier theories, while in the short-circuit case, the current is found to saturate at the ratio of the diffusion potential to the internal resistance. Results are used to explain the experimental results of earlier workers.
TL;DR: In this article, a collective transport-noise theory is given for the effects caused by generation-recombination current via traps in the space charge region of a p-n junction.
Abstract: A collective transport-noise theory is given for the effects caused by generation-recombination current via traps in the space-charge region of a p-n junction. Langevin noise sources are added to the standard kinetic equations, which are subsequently solved for the current noise. No hypotheses are made on the coupling of the g-r current to the external circuit. In particular, Ramo's theorem does not apply, though similar transport factors emerge automatically as a consequence of the inclusion of displacement current. With the assumption that the free carrier transit times are very short, exact agreement with Lauritzen's  previous results, based on a probabilistic approach, is found. In addition, the admittance is computed from the same equations and is shown to be frequency dependent, contrary to standard assumptions made for the computation of emitter efficiency. Consistency with Nyquist's theorem is obtained for the low and high frequency regime. The noise reduction factors for forward biased junctions are discussed.