Showing papers in "IEEE Transactions on Electron Devices in 1985"
TL;DR: In this paper, a physical model involving the breaking of the ≡ Si s H bonds was proposed to explain the observed time dependence of MOSFET degradation and the observed channel field.
Abstract: Evidence suggests that MOSFET degradation is due to interface-states generation by electrons having 3.7 eV and higher energies. This critical energy and the observed time dependence is explained with physical model involving the breaking of the ≡ Si s H bonds. The device lifetime τ is proportional to I_{sub}^{-2.9}I_{d}^{1.9}\Delta V_{t}^{1.5} . If I sub is large because of small L or large V d , etc., τ will be small. I sub (and possibly light emission) is thus a powerful predictor of τ. The proportionality constant has been found to vary by a factor of 100 for different technologies, offering hope for substantially better reliability through future improvements in dielectric /interface technologies. A simple physical model can relate the channel field E m to all the device parameters and bias voltages. Its use in interpreting and guiding hot-electron scaling are described. LDD structures can reduce E m and I sub and, when properly designed, reduce device degradation.
1,029 citations
TL;DR: In this article, a quantitative model for oxide breakdown based on impact ionization and hole trapping at the cathode is presented and shown to agree well with the experimental J - t and time-to-breakdown, (t BD ) results.
Abstract: The breakdown of thin oxides (7.9-32 nm) subjected to high-field current injection is investigated in this study. The physical mechanism of breakdown is found to be localized field enhancement at the cathode interface due to hole trapping. The source of this hole trapping is believed to be impact ionization in the SiO 2 . A quantitative model for oxide breakdown based on impact ionization and hole trapping at the cathode is presented and shown to agree well with the experimental J - t and time-to-breakdown, (t BD ) results. We observe that log t BD varies linearly with 1/ E rather than with E as commonly assumed. The field acceleration factor, i.e., the slope of the log t BD versus 1/ E plot, is approximately 140 decades per centimeter per megavolt for the 7.9 nm oxide, with approximately 25 percent of this coming from the field dependence of the impact ionization coefficient and the remainder from the Fowler-Nordheim current dependence on 1/ E . Based on this model, oxide wearout performance might be improved by process changes that reduce interface hole trapping, such as radiation-hard processing, in addition to the reduction of particulate contamination and crystal defects.
426 citations
TL;DR: In this article, a model for interconnection time delay is developed that includes the effects of scaling transistor, interconnection, and chip dimensions, and propagation delays of aluminum, WSi 2, and polysilicon lines are compared.
Abstract: The propagation delay of interconnection lines is a major factor in determining the performance Of VLSI circuits because the RC time delay of these lines increases rapidly as chip size is increased and cross-sectional interconnection dimensions are reduced. In this paper, a model for interconnection time delay is developed that includes the effects of scaling transistor, interconnection, and chip dimensions. The delays of aluminum, WSi 2 , and polysilicon lines are compared, and propagation delays in future VLSI circuits are projected. Properly scaled multilevel conductors, repeaters, cascaded drivers, and cascaded driver/ repeater combinations are investigated as potential methods for reducing propagation delay. The model yields optimal cross-sectional interconnection dimensions and driver/repeater configurations that can lower propagation delays by more than an order of magnitude in MOSFET circuits.
400 citations
TL;DR: In this article, a multielectrode recording array for use in studies of information processing in the central nervous system and in the closed-loop control of neural prostheses is presented.
Abstract: This paper reports the development of a multielectrode recording array for use in studies of information processing in the central nervous system and in the closed-loop control of neural prostheses. The probe utilizes a silicon supporting carrier which is defined using a deep boron diffusion and an anisotropic etch stop. This substrate supports an array of polysilicon or tantalum thin-film conductors insulated above and below with silicon nitride and silicon dioxide. Typical probe dimensions include a length of 3 mm, shank width of 50 µm, and a thickness of 15 µm. These structures are capable of simultaneous high-amplitude multichannel recording of neural activity in the cortex. The probe fabrication process requires only four masks and is single-sided using wafers of normal thickness, resulting in yields which exceed 80 percent. The process is also compatible with the inclusion of on-chip MOS circuitry for signal amplification and multiplexing. A complete ten-channel signal processor which requires only three external probe leads is being developed.
318 citations
TL;DR: In this paper, a comparison of hot-carrier degradation experiments with simulations of hot electron and hole emission into the oxide was made, and it was shown that both the emission of holes and of electrons are essential to explain the dominant generation of negative charge by a new degradation mechanism.
Abstract: This paper presents a comparison of hot-carrier degradation experiments with simulations of hot electron and hole emission into the oxide. It is shown that both the emission of holes and of electrons are essential to explain the dominant generation of negative charge by a new degradation mechanism. Moreover, a peak of positive-charge generation at a gate voltage close to threshold was found in our experiments which is due to hole trapping. A simple degradation model based on the calculated electron and hole emission is presented which gives a very good description of the observed behavior of degradation effects.
298 citations
PARC1
TL;DR: In this paper, a study of the operation of surface and buried-mode p-channel FET's was conducted, where the surface-channel devices were found to be more resistant to short-channel effects than their buried-channel counterparts independent of background doping concentration.
Abstract: A study of the operation of surface- and buried-mode p-channel FET's is conducted. The buried-channel devices are fabricated using n-type polysilicon gates while the surface-channel devices employ p-type polysilicon gates. Using devices with different channel lengths (20 to 0.4 µm), threshold voltage lowering, subthreshold characteristics, transconductance, punchthrough, and body effects are compared over a wide range of background doping concentrations. In the study surface-channel devices were found to be more resistant to short-channel effects than their buried-channel counterparts independent of background doping concentration. Two-dimensional computer simulation revealed that buried-channel devices are more subject to drain-induced barrier lowering and bulk punchthrough. The body effect for the surface-channel device is lower than its counterpart at low background doping concentrations whereas the buried-channel device has a lower body effect at high background doping levels. The effective carrier mobility of buried-channel devices was found greater than that of surface devices. The net difference in the transconductance, however, is offset by the high parasitic diffusion resistance.
293 citations
TL;DR: The anomalous leakage current I L in LPCVD polysilicon MOSFETs is attributed to field emission via grain-boundary traps in the (front) surface depletion region at the drain, and an analytic model that describes the strong dependences of I L on the gate and drain voltages is developed.
Abstract: The anomalous leakage current I L in LPCVD polysilicon MOSFET's is attributed to field emission via grain-boundary traps in the (front) surface depletion region at the drain, and an analytic model that describes the strong dependences of I L on the gate and drain voltages is developed. The model predictions are consistent with measured current-voltage characteristics. Physical insight afforded by the model implies device design modifications to control and reduce I L , and indicates when the back-surface leakage component is significant.
275 citations
TL;DR: In this article, an algorithm to include the Pauli exclusion principle in the Ensemble Monte Carlo method was presented, which indicates that significant changes in the transport properties of GaAs have to be expected when degenerate conditions are reached.
Abstract: An algorithm to include the Pauli exclusion principle in the Ensemble Monte Carlo method is presented. The results indicate that significant changes in the transport properties of GaAs have to be expected when degenerate conditions are reached. Important repercussions should be found in the modeling of microwave devices, where one often deals with highly doped regions.
261 citations
TL;DR: In this paper, a design methodology was developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools.
Abstract: Building on nearly two decades of reported results for MOSFET's fabricated in small-grain polycrystalline silicon, a design methodology is developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools. Design criteria and device performance are discussed, grain boundary characterization techniques are described, technological issues pertinent to VLSI implementation are investigated, and long-term device reliability is studied. The potential applications of the polysilicon MOSFET's in high-density dRAM and sRAM are explored. The successful implementation of an experimental stacked CMOS 64K static RAM proves the utility of these devices for three-dimensional integration in a VLSI environment.
231 citations
IBM1
TL;DR: In this paper, the authors compared three standard approaches: transient excitation followed by Fourier decomposition, incremental charge partitioning, and sinusoidal steady-state analysis, and concluded that SSA is the superior approach by providing accurate, rigorously correct results with reasonable computational cost and programming commitment.
Abstract: Techniques for ascertaining the small-signal behavior of semiconductor devices in the context of numerical device simulation are discussed. Three standard approaches to this problem will be compared: (i) transient excitation followed by Fourier decomposition, (ii) incremental charge partitioning, and (iii) sinusoidal steady-state analysis. Sinusoidal steady-state analysis is shown to be the superior approach by providing accurate, rigorously correct results with reasonable computational cost and programming commitment.
212 citations
TL;DR: In this paper, the authors present an extensive review of thermal nitridation of Si and SiO 2, and show that very thin thermal silicon nitride and nitroxide films can be used as gate dielectrics for future highly scaled-down VLSI devices.
Abstract: This paper presents an extensive review of our work on thermal nitridation of Si and SiO 2 . High-quality ultrathin films of silicon nitride and nitrided-oxide (nitroxide) have been thermally grown in ammonia atmosphere in a cold-wall RF-heated reactor and in a lamp-heated system. The growth kinetics and their dependence on processing time and temperature have been studied from very short to long nitridation times. The kinetics of thermal nitridation of SiO 2 in ammonia ambient have also been studied. In nitroxide, nitrogen-rich layers are formed at the surface and interface at a very early stage of the nitridation. Then the nitridation reaction mainly goes on in the bulk region with the surface and near interface nitrogen content remaining fairly constant. Our results also indicate the formation of an oxygen-rich layer at the interface underneath the nitrogen-rich layer whose thickness increases slowly with nitridation time. The nitride and nitroxide films were analyzed using Auger electron spectroscopy, grazing angle Rutherford backscattering, and etch rate measurements. MIS devices were fabricated using these films as gate insulators and were electrically characterized using I - V, C - V , time-dependent breakdown, trapping, and dielectric breakdown techniques. Breakdown, conduction, and C-V measurements on metal-insulator semiconductor (MIS) structures fabricated with these films show that very thin thermal silicon nitride and nitroxide films can be used as gate dielectrics for future highly scaled-down VLSI devices. The electrical characterization results also indicate extremely low trapping in the nitride films. The reliability of ultrathin nitride was observed to be far superior to SiO 2 and nitroxide due to its much less trapping. Studies show that the interface transition from nitride to silicon is almost abrupt and the morphology and roughness of the interface are comparable to the SiO 2 -Si interfaces.
TL;DR: A homogeneous silica optical fiber with its coating and cladding removed will interact with its surroundings via evanescent-wave modes at the interface, where a fluorescently labeled antigen or antibody competes for the binding sites on the immobilized bio-molecules thereby providing a competitive binding fluoro-immunoassay.
Abstract: A homogeneous silica optical fiber with its coating and cladding removed will interact with its surroundings via evanescent-wave modes at the interface. Antibody or antigen molecules can be covalently linked to the silica-fiber surface. The immobilized biomolecules will bind complementary antigen or antibody from a surrounding solution. If the bound antigen or antibody is fluorescent, a fluoro-immunoassay can be performed. The sensitivity of such a sensor is enhanced in a competitive immunoassay mode, where a fluorescently labeled antigen or antibody competes for the binding sites on the immobilized bio-molecules, thereby providing a competitive binding fluoro-immunoassay. Such sensors have the potential for remote unattended pseudocontinuous monitoring of biomolecules.
TL;DR: An overview of the physical principles and numerical methods used to solve the coupled system of non-linear partial differential equations that model the transient behavior of silicon VLSI device structures and a simple data structure for nonsymmetric matrices with symmetric nonzero structures is presented.
Abstract: In this paper, we present an overview of the physical principles and numerical methods used to solve the coupled system of non-linear partial differential equations that model the transient behavior of silicon VLSI device structures. We also describe how the same techniques are applicable to circuit simulation. A composite linear multistep formula is introduced as the time-integration scheme. Newton-iterative methods are exploited to solve the nonlinear equations that arise at each time step. We also present a simple data structure for nonsymmetric matrices with symmetric nonzero structures that facilitates iterative or direct methods with substantial efficiency gains over other storage schemes. Several computational examples, including a CMOS latchup problem, are presented and discussed.
TL;DR: A new approach to the problem of extracting clock from NRZ data is described, both simple and self correcting, that holds the clock in the center of the data eye.
Abstract: Conventional approaches to the problem of extracting clock from NRZ data do not automatically hold the clock in the center of the data eye. Other means must be used to keep the clock properly centered in the eye at the decision flip-flop. A new approach to the problem is described. The circuit is both simple and self correcting.
TL;DR: In this article, a compact model for bipolar transistors which includes quasi-saturation effects is presented, and the assumptions used in the formulation of this model are clearly stated and justified, and a step-by-step derivation of the model equations is presented.
Abstract: This paper describes a compact model for bipolar transistors which includes quasi-saturation effects The assumptions used in the formulation of this model are clearly stated and justified, and a step by step derivation of the model equations is presented These equations model both de and charge storage effects Parameter extraction techniques are qualitatively described and the compact model is evaluated using detailed physical simulations of a high voltage bipolar transistor In addition, simulations employing this model are compared with measurements and are found to be in excellent agreement
TL;DR: In this article, a 160 × 244 element IR-CCD image sensor was developed with PtSi Schottky-barrier detectors (SBD's) for thermal imaging in the 30-50 µm IR band.
Abstract: A 160 × 244 element IR-CCD image sensor was developed with PtSi Schottky-barrier detectors (SBD's) for thermal imaging in the 30-50-µm IR band This imager has 80 × 40 µm2pixels, a fill factor of 39 percent, and a chip size of 584 × 464 mil2 It produces excellent quality thermal imaging with noise-equivalent temperature (NEΔT) of less than 01 K for operation at 30 frames/s with standard-TV-interlace f/23 optics, and one-point offset-type uniformity corrector This paper describes the design, construction, and performance of 160 × 244 element IR-CCD imager and the characteristics of the PtSi Schottky-barrier detector elements
TL;DR: In this paper, a rectangular-grooved MOSFET (RMOS) was proposed, in which the vertical channels are provided along the sidewalls of the rectangular grooves formed by a reactive ion-beam etching (RIBE) technique.
Abstract: A new vertical power MOSFET structure called rectangular-grooved MOSFET (RMOS) is proposed, in which the vertical channels are provided along the sidewalls of the rectangular grooves formed by a reactive ion-beam etching (RIBE) technique. The structure is characterized by reduced ON-resistance and high packing density. The relationship between the ON-resistance and the packing density in the new structure is calculated. It is demonstrated that the structure essentially possesses a lower ON-resistance per unit area than VMOS and DMOS structures. Experimental results are also described in detail.
TL;DR: In this paper, a self-aligned titanium silicide process was developed for VLSI applications with sheet resistances of 1.0-2.0 Ω/square.
Abstract: A manufacturable self-aligned titanium silicide process which simultaneously silicides both polysilicon gates and junctions has been developed for VLSI applications. The process produces silicided gates and junctions with sheet resistances of 1.0-2.0 Ω/square. This paper describes the application of the self-aligned titanium silicide process to NMOS VLSI circuits of the 64K SRAM class with 1-µm gate lengths. Comparison of circuit yield data and test structure parameters from devices fabricated with and without the silicidation process has demonstrated that the self-aligned silicide process is compatible with both VLSI NMOS and CMOS technologies. The self-aligned titanium silicide process has some very significant manufacturing advantages over the more conventional deposited silicide on polysilicon technologies. In particular, the problems associated with etching and depositing a polycide gate stack are eliminated with the self-aligned process since the polycide etch is replaced with a much more straightforward polysilicon only etch. As gate lengths, gate oxide thicknesses, and source-drain junction depths are scaled, linewidth control, etch selectivity to the underlying gate oxide, and cross-sectional profile control become more critical. The stringent etch requirements are more easily satisfied with the self-aligned silicide process.
TL;DR: In this article, the electron and hole impact ionization coefficients in (100) GaAs have been determined using photomultiplication measurements performed on specially fabricated p+-n diode structures having active region carrier concentrations from 1.1 X 1017 to 2.2 X 1015 cm-3.
Abstract: The electron and hole impact ionization coefficients in (100) GaAs have been determined using photomultiplication measurements performed on specially fabricated p+-n diode structures having active region carrier concentrations from 1.1 X 1017 to 2.2 X 1015 cm-3. These structures are designed to permit pure electron and hole injection in the same diodes. In diodes having heavy p+ doping, the effects of electron dead space have been observed. This dead-space region corresponds to the distance required for an injected carrier to accelerate ballistically to the impact ionization threshold energy, and a method to include this phenomenon in the calculation of α and β from the experimental multiplication data is presented. Agreement among the results from all these structures is obtained with an electron threshold energy of 1.7 eV, and the corrected data are also in agreement with data obtained from device structures designed to eliminate dead-space effects. The measured ratio of α/β in GaAs is found to decrease from 2.4 at 2.2 X 105 V/cm to 1.0 at 6.25 X 105 V/cm. Avalanche noise measurements performed at 30 MHz on the same devices under both electron and hole injection yield a keff of 0.6 and a k'eff of 1.7, respectively, in agreement with the values of these parameters obtained from the photocurrent results.
TL;DR: In this paper, the design of a relative humidity sensor is studied in which the principle of operation is based on the change of dielectric constant of a thin film of polyimide.
Abstract: The design of a relative humidity sensor is studied in which the principle of operation is based on the change of dielectric constant of a thin film of polyimide. The design of the sensor is established in such a way that it would be suitable for an integrated-circuit type of fabrication. The studies have shown that the experimental data are described well by the use of the Looyenga equation for dielectric constant behavior coupled with the Dubinin equation to describe the absorption as a function of relative humidity.
TL;DR: In this article, two semiclassical ballistic transport models for thin films developed in 1971 treat the problem of "hot-electron" internal photoemission in Schottky-barrier diode IR detectors.
Abstract: Two semiclassical ballistic transport models for thin films developed in 1971 treat the problem of "hot-electron" internal photoemission in Schottky-barrier diode IR detectors. Both formulations take into account multiple scattering from the surfaces as well as hot-electron-phonon and hot-electron-cold-electron collisions in the bulk. The models are compared for the case of uniform absorption and one of the models is then extended. The extensions incorporate the effect on internal quantum yield of small energy losses from electron-phonon collisions. Also, it is no longer assumed that the fraction removed by capture is small which insures that the yield cannot exceed the theoretical upper limit. The results are illustrated by Fowler plots over a range of scattering parameters and thicknesses germane to Schottky diodes of current interest, PtSi/Si and Pd 2 Si/Si. The main new features of the plots include curvature for photon energies close to the barrier energy due to phonon collision thermalization and roll-off at higher excitation energies whenever the yield is comparable in magnitude to the theoretical limit. The model is in good agreement with earlier Monte Carlo computations.
TL;DR: In this paper, the authors investigated both step stress breakdown and time-dependent dielectric breakdown (TDDB) which exhibited two distinguished slopes in Weibull plots and demonstrated that the intermediate breakdown mode (B mode) in the breakdown histogram corresponded to the steep slope in the short time range of the TDDB plot.
Abstract: To evaluate the reliability of thin thermally grown oxide films, we investigated both step stress breakdown and time-dependent dielectric breakdown (TDDB) which exhibited two distinguished slopes in Weibull plots. It is demonstrated that the intermediate breakdown mode ( B mode) in the breakdown histogram corresponded to the steep slope in the short time range of the TDDB plot. The steep slope is observed in the shorter time range with stress field and temperature. The electric field acceleration factor decreases with decreasing the oxide thickness. The TDDB data give us minimum voltage in the step stress breakdown histogram necessary to guarantee the device operation for 10 years. Comparison between the breakdown histogram and the minimum voltage indicates that the B mode defect should be decreased. Major origins of the B mode defect are oxygen microprecipitates and metallic contamination in the Si substrates. We found that both high-temperature preoxidation annealing and phosphorus diffusion into the back side of wafers greatly increase time to failure of thin thermally grown SiO 2 films because of decreasing both the number of oxygen microprecipitates and metallic contamination level.
TL;DR: In this paper, a vapor-sensing method has been developed which is compatible with monolithic silicon microelectronics technology, and electronic conductance changes caused by vapor interactions with very thin films of organic semiconductors are shown to be sensitive, reproducible, rapid and stable chemical detectors.
Abstract: A vapor-sensing method has been developed which is compatible with monolithic silicon microelectronics technology. Specifically, electronic conductance changes caused by vapor interactions with very thin films of organic semiconductors are shown to be sensitive, reproducible, rapid, and stable chemical detectors. Functionalized copper phthalocyanine multilayer films deposited by the Langmuir-Blodgett technique onto planar microelectrode arrays can easily detect ammonia at sub-ppm concentration levels.
TL;DR: In this article, a four-terminal small-signal dc-to-high-frequency model, valid in weak, moderate, and strong inversion regimes, for the intrinsic part of the long-channel MOS transistor is presented.
Abstract: This paper presents a four-terminal small-signal dc-to-high-frequency model, valid in weak, moderate, and strong inversion regimes, for the intrinsic part of the long-channel MOS transistor. A charge-sheet approximation is used. Basic MOSFET equations are separated into parts corresponding to dc and ac small-signal components. The former are used to evaluate the drain current under dc conditions; the latter, describing the "transmission-line" behavior of the MOSFET, are solved to arrive at a complete set of admittance parameters. Based on different approximations of these parameters, various models are presented, each of different upper frequency limit of validity. For each model parameter, a single continuous expression is used which is valid in all regions of operation (weak inversion, moderate inversion, strong inversion; nonsaturation and saturation). The frequency range of validity of these models and the inadequacies of the quasistatic models at high frequencies are discussed. It is shown that at low frequencies the high-frequency model reduces to a quasistatic model which is widely verified by experimental results; at high frequencies the model agrees with available measurements.
TL;DR: In this article, the critical steps of IC fabrication are simulated by one-and two-dimensional computer programs using advanced physical models, dealing with an arbitrary number of physical quantities such as concentrations of dopants, vacancies, interstitials and clusters, the electrostatic potential, and so on.
Abstract: Critical steps of IC fabrication are simulated by one- and two-dimensional computer programs using advanced physical models. Our codes deal with an arbitrary number of physical quantities such as concentrations of dopants, vacancies, interstitials and clusters, the electrostatic potential, and so on. Furthermore, they easily permit the exchange or variation of the physical models under consideration. As typical applications phenomena of coupled diffusion in one and two dimensions and dynamic arsenic clustering are investigated. The differences caused by the models of the zero space-charge approximation and the solution of the exact Poisson equation are studied by examples of As-B diffusion with various doping concentrations at different temperatures. A dynamic cluster model developed for the simulation of thermally annealed As implantations is compared to measured data of laser annealing experiments. A short outline of the mathematical and the numerical problems is given to show the amount of sophistication necessary for up-to-date process simulation.
TL;DR: An automated system has been developed to obtain the process statistical variations and extract SPICE model parameters for a large number of MOS devices, and a linear approximation for the yield body boundary is used to make an accurate prediction of parametric yield.
Abstract: Large statistical variations are often found in the performance of VLSI circuits; as a result, only a fraction of the circuits manufactured may meet performance goals An automated system has been developed to obtain the process statistical variations and extract SPICE model parameters for a large number of MOS devices Device length and width, oxide capacitance, and flat-band voltage are shown to be the principal process factors responsible for the statistical variation of device characteristics Intradie variations are much smaller than the interdie variations, therefore, only the interdie variations are responsible for variations in circuit performance This accurate and simple statistical modeling approach uses only four statistical variables, and thus enables the development of a very computationally efficient statistical parametric yield estimator (SPYE) A linear approximation for the yield body boundary is used to make an accurate prediction of parametric yield With the addition of temperature and supply voltage as operating condition variables, a maximum of seven simulations are required; only slightly more than the three to five required for "worst case analysis" The method has also been adapted statistical parametric specification of standard cells; performance ranges of circuit building blocks can be characterized once the statistical variations of process-dependent parameters are known Predicted performance variations from SPYE have been compared with measured variations in delay and power consumption for a 7000-gate n-MOS inverter chain Agreement with the mean delay and power are better than 5 percent where SPICE model parameters were obtained from the same slice used for circuit characterization Excellent agreement was obtained in the predicted spread in the circuit delay and power consumption using measured variations in the statistical variables
TL;DR: In this article, the tradeoffs between using primary or complementary filters are considered and checkerboard geometries are compared to stripe and horizontally staggered sampling, and the constraints imposed by the sensor architecture and the need for interlaced readout are examined.
Abstract: Color images can be obtained from a single solid-state sensor by covering the photosites with a repetitive pattern of color filters. This paper reviews the major issues in selecting appropriate filter patterns and compares different one-chip camera approaches. The processing used to decode the color signals and form acomposite television signal is discussed. The tradeoffs between using primary or complementary filters are considered. Checkerboard geometries are shown to be superior to stripe geometries, and the advantages of horizontally staggered sampling are explained. The constraints imposed by the sensor architecture and by the need for interlaced readout are examined.
TL;DR: In this article, the influence of the main technological parameters on the noise figure and associated gain for operating frequencies up to 60 GHz is given for TEGFET's and MESFETs.
Abstract: Noise modeling in TEGFET's which provides good results in agreement with the experimental findings is presented. The influence of the main technological parameters on the noise figure and associated gain is given for operating frequencies up to 60 GHz. A comparison between TEGFET's and MESFET's is carried out. A new method for calculating the noise and gain performances of FET's is then proposed.
TL;DR: In this article, the role and effects of both electron and hole injection are discussed, and a model of the mean time to failure for NMOS devices fabricated with two different source-drain diffusions is also presented.
Abstract: The high drain-effect transistor characteristic observed after hot-carrier injection and trapping in the oxide has been found to be due to the uneven trapped-carrier distribution near the drain, which causes the threshold voltage to vary as a function of drain voltage. A discussion of the role and effects of both electron and hole injection is presented. The nonlinear distribution of carriers trapped in the gate oxide is described. One result is that the nonuniform surface band bending causes the subthreshold leakage to be an exponential function of the drain voltage. The combined increase in threshold voltage, subthreshold leakage, and a decrease in subthreshold slope will translate into slower circuit speed and higher standby power dissipation [37] in CMOS circuits. An experimental model of the mean time to failure, for NMOS devices fabricated with two different source-drain diffusions, is also presented. For the first time, the model has been extended to include the channel-length dependence. The model assumes a reliability criterion of less than a 10-mV threshold-voltage shift in 100 000 h of operation. Experimental results and subsequent calculations show that for 350-A gate-oxide devices at 5.0 V operation, 2.5 µm is the minimum electrical channel-length device which can be fabricated using a traditional source-drain process. Conversely, submicrometer electrical channel-length devices can be fabricated using an arsenic-phosphorous "graded" source-drain process, even at 5.5-V operation.
TL;DR: In this paper, an exact SOI device simulator applicable to prediction of the transistor characteristics in high-current region is developed, where the basic Poisson's and current continuity equations are numerically solved under steady-state condition.
Abstract: An exact SOI device simulator applicable to prediction of the transistor characteristics in high-current region is developed. In the simulator, the basic two-dimensional Poisson's and current continuity equations are numerically solved under steady-state condition. To obtain a stable and rapid convergence in the numerical scheme, a newly developed alternative step solving method is implemented. Using this simulator, the drain current kink effect, a typical phenomenon for substrate-floating devices, is exactly simulated for the first time. The physical mechanism of this phenomenon is also clarified. The simulated results indicate that kink effects are suppressed by using low-lifetime SOI substrates.