Showing papers in "IEEE Transactions on Electron Devices in 1986"

A generalized theory of an electrolyte-insulator-semiconductor field-effect transistor

Abstract: A model of surface ionization and complexation of surface hydroxyl groups on the gate insulator surface is adapted in conjunction with electronic device physics to arrive at a generalized theory for the current-voltage characteristics of an electrolyte-insulator-semiconductor field-effect transistor (EISFET) in electrolyte solutions. EISFET's that employ thermally grown silicon dioxide were tested in simple electrolytes that contain Na+, K+, and Li+ions titrated in a p H range from 2 to 9. Experimental results show good agreement with the theory. The model successfully explains p H sensitivity, as well as the ion interference effect, of the EISFET working as a p H sensor. From this model, it is conluded that, among all the electrolyte parameters associated with an EISFET, the surface site density of the hydroxyl groups N s and the separation of surface ionization constants \Delta pK are the primary factors to consider when employing EISFET's as p H sensors. For high sensitivity and good selectivity, large N s and small \Delta pK values are required.

High-frequency noise measurements on FET's with small dimensions

Abstract: A low-noise high-frequency transresistance amplifier has been used to accurately measure broad-band noise in MOSFET's with small widths and submicrometer channel lengths The technique allows noise characterization up to frequencies of 100 MHz of the small devices available as process test arrays from different fabrication lines The noise in the different portions of the I-V characteristics of submicrometer MOSFET's has been characterized and shown to be greater by factors of 2 to 4 than the noise expected from long-channel noise theory

Resonant-microbridge vapor sensor

Abstract: A novel integrated vapor sensor is described that incorporates a polycrystalline silicon microbridge coated with a thin polymer film The microbridge is resonated electrostatically and its vibration is detected capacitively using an integrated NMOS circuit Vapor uptake by the polymer increases the mass-loading on the microbridge, thereby perturbing the first resonant frequency of the microbridge In the prototype device, a 150-nm-thick layer of negative photoresist coats a 153-µm-long 135-µm-thick polycrystalline silicon microbridge The phase between the excitation and output voltages at resonance is monitored as the sensor output signal Exposure to saturated xylene vapor produces a phase shift of -8° with a response time of less than 7 min

MOS-Controlled thyristors—A new class of power devices

Abstract: A new class of power devices is described that is based on an optimal combination of MOS and thyristor elements. Devices of this class function in the ON-state and OFF-state in a manner indistinguishable from a thyristor yet can switch from on-to-off or off-to-on by applying a voltage to its MOS gate. Thus, the devices exhibit extremely low forward drop, high surge current capability, and enjoy negative thermal feedback. To turn off the device, one activates the gate so that FET's are turned on to effectively short one of the emitting junctions of the thyristor. These FET's need only block a maximum of about 1 V when off and carry a sizable current for about 1 µs when on. To turn on the device, any of the normal methods may be employed. However, it is most convenient to use the same MOS gate electrode (and polysilicon layer) and a voltage of the opposite polarity to turn on the thyristor with another FET-just as if it were a normal MOS gated thyristor. The current density that can be turned off depends on the density and effective resistance of the turn-off FET's while turn-on speed and di/ dt rating depend on the initial turn-on area, which in turn depends on the density of the ON-FET's. If the OFF-gate voltage is maintained during the desired OFF-state period, the device has, effectively, an infinite dv/dt capability. Switching speed is most similar to, but somewhat faster than, that of gate turn-off thyristors (GTO's) and, as in other bipolar devices, depends chiefly on carrier recombination time, device thickness, and turn-off di/dt .

The delta-doped field-effect transistor (δFET)

Abstract: A field-effect transistor (FET) using a two-dimensional electron gas (2DEG) as an electron channel is fabricated from GaAs grown by molecular-beam epitaxy. The doping profile of the field-effect transistor is described by the Dirac delta (δ) function. The subband structure of δ-doped GaAs is calculated. The characteristics of the δFET are a high concentration of the 2DEG, a high breakdown voltage of the Schottky contact, a narrow distance of the 2DEG from the gate, and a high transconductance. These properties are analyzed. Preliminary results for the extrinsic transconductance and for the transit frequency are obtained from δFET's having nonoptimized structures.

Analysis and modeling of floating-gate EEPROM cells

Abstract: Floating-gate MOS devices using thin tunnel oxide are becoming an acceptable standard in electrically erasable nonvolatile memory. Theoretical and experimental analysis of WRITE/ERASE characteristics for this type of memory cell are presented. A simplified device model is given based on the concept of coupling ratios. The WRITE operation is adequately represented by the simplified model. The ERASE operation is complicated due to formation of depletion layers in the transistor's channel and under the tunnel oxide. Experimental investigation of these effects is described, and they are included in a detailed cell model. In certain cell structures, a hole current can flow from the drain into the substrate during the ERASE oepration. This effect is shown to be associated with positive charge trapping in the tunnel oxide and threshold window opening. An experimental investigation of these phenomena is described, and a recommendation is made to avoid them by an appropriate cell design.

The limiting efficiency of silicon solar cells under concentrated sunlight

Abstract: The intrinsic limits on the energy conversion efficiency of silicon solar cells when used under concentrated sunlight are calculated. It is shown that Auger recombination processes are even more important under concentrated sunlight than nonconcentrated sunlight. However, light trapping can be far more effective under concentrated light due to the better defined direction of incident light. As a result of these effects, the limiting efficiency lies in tile 36-37-percent range regardless of concentration ratio compared to the limiting value of 29.8 percent for a nonconcentrating cell with isotropic response.

The n-channel SiGe/Si modulation-doped field-effect transistor

Abstract: At the heterointerface of Si 1-x Ge x /Si the existence of two-dimensional carrier gas has recently been demonstrated. The electrons are confined inside the large-gap material Si. We report the first fabrication of n-channel modulation-doped SiGe/Si hetero field-effect transistors by use of molecular-beam epitaxial growth. Though neither layer sequence nor parasitic resistances were optimized, these first transistors exhibit an extrinsic transconductance of 40 mS/mm for a gate length of 1.6 µm. This value is higher than that of conventional Si MESFET's of comparable carrier concentration. Technological processing steps and device evaluation are described.

Physics, technology, and modeling of polysilicon emitter contacts for VLSI bipolar transistors

Abstract: The physics of minority-carrier injection into polysilicon-contacted emitters has been studied through a series of experiments correlating the base current of the transistor to the structure of the polysilicon/single-crystal silicon interface. Most of the relevant material and processing parameters have been examined. In addition, a novel approach has been taken in the modeling of transport in these emitters to quantify the minority-carrier blocking properties of the polysilicon contacts. Experimental results show that extremely low values of base current can be obtained for devices etched in HF prior to the polysilicon deposition, i.e., devices with only a remnant "native" oxide layer at the polysilicon/single-crystal silicon interface. For these devices, the base current is mainly determined by the recombination and blocking of minority carriers at the polysilicon/monosilicon interface. A number of competing mechanisms exist in several domains of doping, temperature, and time which influence the properties of this interface. One of these mechanisms is the blocking of minority carriers by the native oxide layer itself. The uniformity and, consequently, the blocking characteristics of this layer were found to be strongly affected by the polysilicon doping level and thermal treatment.

Analysis of the gate-voltage-dependent series resistance of MOSFET's

Abstract: The intrinsic parasitic series resistance that occurs near the channel end of a MOSFET is analyzed. This new model includes the effects due to the unavoidable doping gradient near the metallurgical junction. It is assumed that current first conducts through the accumulation layer before spreading into the bulk region, and thus the spreading (injection) resistance and the accumulation layer resistance have to be considered in series and both are gate-voltage dependent. More importantly, they are shown to be a strong function of the steepness of the doping profile. The model quantitatively predicts these resistance components for a given process, and it emphasizes the necessity for a steep junction profile in order to minimize the series resistance of MOSFET's.

Inversion-layer capacitance and mobility of very thin gate-Oxide MOSFET's

Abstract: Inversion-layer capacitance has been experimentally characterized and identified to be the main cause of the second-order thickness-dependence of MOSFET characteristics. Field-dependent channel mobilities of both electrons and holes were independent of gate-oxide thicknesses from 50 to 450 A, e.g., there is no evidence of the alleged mobility degradation in very thin gate-oxide MOSFET's. Subthreshold slope, insignificantly affected by the inversion-layer capacitance, follows the simple theory down to ∼ 35 A of oxide thickness. The empirical equations for inversion-layer Capacitance and mobilities versus electric field are proposed.

Characterization of InGaAs/AlGaAs pseudomorphic modulation-doped field-effect transistors

Abstract: High-performance pseudomorphic In y Ga 1-y As/Al 015 - Ga 085 As ( 005 \le y \le 02 ) MODFET's grown by MBE have been characterized at dc (300 and 77 K) and RF frequencies Transconductances as high as 310 and 380 mS/mm and drain currents as high as 290 and 310 mA/mm were obtained at 300 and 77 K, respectively, for 1-µm gate lengths and 3-µm source-drain spacing devices Lack of persistent trapping effects, I-V collapse, and threshold voltage shifts observed with these devices are attributed to the use of low mole fraction Al x Ga 1-x As while still maintaining 2DEG concentrations of about 13 × 1012cm-2 Detailed microwave S-parameter measurements indicate a current gain cut-off frequency Of 245 GHz When y = 020 , which is as much as 100 percent better than similar GaAs/AlGaAs MODFET structures, and a maximum frequency of oscillation of 40 GHz These superior results are in part due to the higher electron velocity of InGaAs as compared with GaAs Velocity field measurement performed up to 3 kV/cm using the magnetoresistance method indicates an electron saturation velocity of greater than 17 × 107cm/s at 77 K for y = 015 , which is 20 percent higher than GaAs/AlGaAs MODFET's of similar structure

On the low-temperature degradation of (AlGa)As/GaAs modulation-doped field-effect transistors

Abstract: A comprehensive study of the anomalous low-temperature behavior of modulation,doped (Al, Ga)As/GaAs field-effect transistors is reported, Experiments on the effect of bias stress on the current-voltage characteristics in lateral resistors, 1-µm gate FET's, and a novel dual-gate tester are presented along with the results of freeze-out, optical spectroscopy, and trapping kinetics experiments. Both modulation-doped (Al, Ga)As/GaAs heterostructures and isolated (Al, Ga)As layers are examined. The results delineate the conditions under which threshold shift and I-V collapse occur. Based on these results a detailed physical model which explains these effects is proposed. One important conclusion of this work is that the collapse is not related to hot electron injection from the high mobility channel, as suggested earlier, but is a property of a highly doped AlGaAs layer under bias.

A new integrated silicon gate technology combining bipolar linear, CMOS logic, and DMOS power parts

Abstract: This paper describes a new mixed technology, called Multipower BCD, that, starting from the merging of the VDMOS silicon gate process with the conventional junction isolation process, allows the integration on a single chip of bipolar linear, CMOS logic, and DMOS power functions. The architecture of the process was chosen to optimize the power part, which generally occupies the most chip area. With the DMOS device, many other signal components have been obtained whose electrical and structural characteristics are discussed in relation to some process variables. Many test vehicles have been processed to evaluate the different structures and a first electrical application of the technology is indicated.

Variation of lateral doping as a field terminator for high-voltage power devices

Abstract: In this brief a new concept for high-voltage planar junctions is presented. The necessary widening of the space-charge region at the junction surface is obtained by implantation through small openings in the oxide mask and subsequent drive-in, leading to a controlled smeared-out dopant distribution. Compared to other planar junctions, this concept also yields a gain in active chip area. Experimental results show the validity of the concept.

A silicon-thermopile-based infrared sensing array for use in automated manufacturing

Abstract: This paper describes a new low-cost infrared detector array that has been realized using standard silicon MOS process technology and micromachining. This array uses thermopiles as infrared detecting elements and multiple layers of silicon oxide and silicon nitride for diaphragm windows measuring 0.4 mm × 0.7 mm × 1.3 µm. Each thermopile consists of 40 polysilicon-gold thermocouples. A high fill factor for this array structure has been achieved by using the boron etch-stop technique to provide 20-µm thick silicon support rims. The array shows a response time of less than 10 ms, a responsivity of 12 V/ W; and a broad-band input spectral sensitivity. The process is compatible with silicon MOS devices, and a 16 × 2 staggered array with on-chip multiplexers has been designed for applications in process monitoring. The array theoretically achieves an NETD of 0.9°C and an MRTD of 1.4°C at a spatial frequency of 0.2 Hz/mrad in a typical imaging system.

Study of the quasi-saturation effect in VDMOS transistors

Abstract: The quasi-saturation effect in VDMOS transistors is studied in detail. It is shown that such behavior is due to carrier velocity saturation in the JFET region of the device. Two-dimensional numerical simulation is carried out to study the quasi-saturation effect and its relation to different device design parameters. Experimental results over a wide range of voltage and current levels are used to verify calculated dc characteristics. In addition, the design constraint on p-body spacing in order to avoid the quasi-saturation effect is defined.

A MODFET dc model with improved pinchoff and saturation characteristics

Abstract: We present an analytical dc model for the MODFET that offers several improvements over existing models. An enhanced version of the model makes use of a new approximation of the two-dimensional electron gas (2DEG) concentration versus gate-to-channel voltage, which models both the subthreshold region and the gradual saturation of carriers due to the onset of AlGaAs charge modulation. Even in this more accurate model there are no complicated numerical calculations involved; at most what is required is finding a single root of a function of one variable. We propose an electron velocity-field curve that combines the observed field-dependent mobility in the 2DEG, and the sharp velocity saturation in GaAs. We use a two-region Grebene-Ghandhi model with floating boundary for the channel. The quasi-linear region on the source side is treated by the gradual channel approximation and extends toward the drain up to a point where the field reaches its threshold for velocity saturation. Between this point and the drain-side end of the channel, the potential is determined by the two-dimensional Poisson equation in the AlGaAs region. The resuiting I-V characteristics and their slopes are continuous. The model predicts a maximum transconductance and a finite intrinsic output conductance in the saturated region, two features experimentally observed but not predicted by previous models. In the limit of very short gate lengths the model approaches the saturated velocity model, while in the limit of very long gate lengths it approaches the classical gradual channel model.

Polycrystalline-silicon device technology for large-area electronics

Abstract: The process sequence used to fabricate post-hydrogenated polycrystalline silicon thin-film devices has a dramatic impact on performance. A near-optimal process for devices that have hole mobilities of up to 50 cm2/V . s and electron mobilities of 70 cm2/V . s is demonstrated. These observed mobilities are substantially higher than previous literature reports. Implantation of boron or phosphorus into the polycrystalline-silicon device channel after the gate-oxidation step allows threshold-voltage tailoring for achievement of either enhancement-or depletion-mode operation of n- and p-channel devices. These results indicate that CMOS or NMOS logic could be fabricated using polycrystalline-silicon devices. Devices with steam-grown gate oxides have reduced channel mobility in comparison with devices oxidized in dry O 2 at the same temperature. Possible mechanisms for the variation in performance with oxidation conditions are discussed.

Surface influence on the conductance DLTS spectra of GaAs MESFET's

Abstract: The observation of hole traps in small-signal GaAs MESFET's has been extensively reported in the literature. Previously these have been attributed to trapping at the active layer-substrate interface. Evidence is presented here, based on conductance DLTS and low-field low-frequency transconductance dispersion measurements on MESFET's of various geometries, to suggest that the main contribution to the "hole trap-like" spectrum in conductance DLTS is not bulk hole traps. Instead we believe that this phenomenon arises from changes in the population of surface states in the ungated access regions of the device, resulting in modulation of the surface depletion layer in series with the gate depletion region.

Location of 1/f noise sources in BJT's and HBJT's—I. theory

Abstract: The most general case of 1/f noise in transistors can be described by three independent noise current generators: i be between base and emitter, i bc between base and collector, and i ec between emitter and collector By short-circuiting the base and the collector to ground and comparing the base and collector noise spectra S_{IB}(f) and S_{IC}(f) for the case of zero feedback from the emitter with the base and collector noise spectra S'_{IB}(f) and S'_{IC}(f) for the case of strong feedback from the emitter, one can evaluate the relative strength of the three noise sources By measuring the current dependence of S_{IB}(f) , S_{IC}(f) , S'_{IB}(f) , and S'_{IC}(f) , one can assign physical processes to the current generators i bc , i be , and i ec It is the aim of this paper to demonstrate theoretically a simple method for locating 1/f noise sources in BJT's and HBJT's by comparing the base and collector 1/f noise for the cases without and with strong emitter feedback In later papers we shall demonstrate experimentally how this method is applied to practical situations

Junction termination extension for near-ideal breakdown voltage in p-n junctions

Abstract: Extremely high breakdown voltages with very low leakage current have been achieved in plane and planar p-n junctions by using an ion-implanted junction extension for precise control of the depletion region charge in the junction termination. A theory is presented that shows a greatly improved control of both the peak surface and bulk electric fields in reverse biased p-n junctions. Experimental results show breakdown voltages greater than 95 percent of the ideal breakdown voltage with lower leakage currents than corresponding unimplanted devices. As an example, plane-junction moat-etch-terminated diodes with a normal breakdown voltage of 1050 V and a 0.5-mA leakage current become 1400 V (1450 ideal) devices with a 5-µA leakage current. Planar junctions, which broke down at 300 V, blocked as much as 1400 V if JTE terminated. Since planar junctions are of the greatest interest, we incorporated multiple field ring, field plate, and JTE terminations on a mask set and fabricated and tested thousands of devices. The results clearly showed that the ideal breakdown voltage can be achieved with less than 200 µm with JTE, where the same area would lead to 30 to 45 percent of the ideal with field rings and up to 40 to 50 percent of the ideal when used with field rings combined with field plates. Eight rings, even combined with a field plate, yielded less than 80 percent of the ideal breakdown voltage and required about 400 µm of device periphery.

Transmission line models for lossy waveguide interconnections in VLSI

Abstract: At high frequencies the waveguide nature of interconnections in VLSI circuits becomes important. Moreover, losses in interconnection are a major feature, not a perturbation. Here it is shown that even for such lossy waveguide structures an exactly equivalent RLGC transmission line can be found. Equations are given determining these transmission line parameters in terms of the waveguide propagation constant and complex average power, and also in terms of integrals over the electric and magnetic field varibles. The resulting L , C , and G parameters differ from the usual static values when losses are important, and R is not restricted to the usual formula based upon a perturbation treatment of the skin effect. Consequently, semiconductor substrates can be treated. "Current" and "voltage" are found to have an abstract meaning in the equivalent transmission line. For a waveguide in a medium where conductivity and permittivity vary with position (such as a many-layered medium) an explicit formula relating "current" and "voltage" to weighted averages of transverse waveguide fields is given. A brief discussion of the reformulation of Thevenin equivalent circuit parameters in terms of reflection coefficients avoids terms such as "open circuit voltage" that are difficult to interpret for the equivalent transmission line. The framework presented allows construction of equivalent circuits for lossy waveguide interconnections, drivers, and terminations that provide correct spatial dependence in the direction of propagation and correct power relations despite the abstract nature of "current" and "voltage" in these lines.

A 30-ps Si bipolar IC using super self-aligned process technology

Abstract: A new 30-ps Si bipolar IC technology has been developed by scaling down a bipolar transistor's lateral geometry and forming shallow junctions. The n-p-n transistor has a 0.35-µm-wide emitter and a 1.57-µm-wide base region fabricated using super self-aligned process technology (SST) with 1-µm rule optical lithography. The f T values achieved for this device are 13.7 GHz at a collector-emitter voltage of 1 V and 17.1 GHz at 3 V. Propagation delay times (fan-in = fan-out = 1) of 30 ps/gate at 1.48 mW/gate for nonthreshold logic and 50 ps/ gate at 1.46 mW/gate for low-level current mode logic have been achieved.

A versatile 700-1200-V IC process for analog and switching applications

Abstract: An IC process with a wide range of devices up to 1200 V is described. In addition to low-voltage bipolars and CMOS and 230-V VDMOS it provides 700-V high-side LDMOS, HV-PMOS (EPMOS) and low-voltage circuitry, low-side 1200-V LDMOS and 700-V LIGBT (lateral insulated-gate bipolar transistor), as well as 700-V interconnection. These features have been realized by using a substrate of higher resistance in a 250-300-V IC process and by adaptation in the Resurf structure for lateral DMOS. Application examples for flyback and half-bridge power conversion and as a power-bridge driver are given. >

Observation of hot-hole injection in NMOS transistors using a modified floating-gate technique

Abstract: A modified floating-gate technique for measuring small gate currents in MOSFET's with very high resolution (0.01 fA) is described. Using this technique, gate oxide currents due to hot-carrier injection are measured in n-channel MOSFET's. The conventional negative channel hot-electron gate oxide current is observed near V_{g} = V_{d} and a small positive gate current occurs at low V g . We argue that the dependencies of this small positive current on V g and gate length, together with results from a separate floating-source experiment, are consistent only with hot-hole injection.

The effect of distributed series resistance on the dark and illuminated current—Voltage characteristics of solar cells

Abstract: Distributed series resistance effects in solar cells are analyzed and the correctness of representing these by a lumped parameter is discussed for any conditions of bias and illumination In addition to a general mathematical methodology, analytical expressions are derived to simplify the estimation of series resistance effects on the dark and illuminated J-V characteristics of the cell The equivalent series resistance (r s ) in the dark is found to decrease with current density J from r_{b} + r_{e}/3 at small J to ( r_{e} r_{b})^{1/2} at very high J , where r e and r b are the emitter layer and base region resistances, respectively For illuminated conditions r s depends on J as well, being maximum near short-circuit and minimum near open-circuit; however, r s further depends on the photogenerated current J L : its short-circuit value increases with J L from r_{b} + r_{e}/3 to r_{b} + r_{e}/2 and the open-circuit value decreases with J L from r_{b} + r_{e}/3 to (r_{e}r_{b})^{1/2} The variability of r s is therefore related to the relative importance of r b and r_{e};r_{b} plays the role of attenuating this variability, a situation not well recognized previously Previous theoretical and experimental work is critically reviewed throughout this paper

MODFET Ensemble Monte Carlo model including the quasi-two-dimensional electron gas

Abstract: We present an ensemble Monte Carlo model for the modulation-doped field-effect transistor in which quantization in the conduction channel is included using a two-subband triangular-well approximation. The subband population is investigated under different bias conditions in order to evaluate the influence of quantum effects on the electron conduction. It is found that, according to the model, the subband population may be severely reduced at high drain voltages, and that the appearance of stray conduction paths across the AlGaAs region may be a source of performance degradation.

IIIB-8 titanium disilicide contact resistivity and its impact on 1-µm CMOS circuit performance

Abstract: A major feature of modern 1-µm CMOS technology is the use of TiSi 2 -clad diffusions with effective sheet resistances of typically 1 Ω /square. However, until now very little attention has been given to the contact resistance between the TiSi 2 and the underlying diffusions which form the source and drain of the active transistors. Our experimental results have shown that, depending on process conditions, the specific contact resistivity from silicide to n-diffusion varies by six orders of magnitude. In this work it is demonstrated that unless proper care is taken with respect to junction doping concentrations and post-silicide processing to minimize the silicide to diffusion contact resistance, the use of silicided diffusions actually can be detrimental to circuit performance instead of the intended performance enhancement. In this paper we will present: 1) a novel method to evaluate silicide to diffusion contact resistance using only two masks, 2) an outline of the process conditions that yield a minimum contact resistance, 3)circuit simulations showing the impact of this work on circuit performance, and 4) results showing that the modulation of the contact resistance at high current levels can distort the MOS linear region current-voltage characteristics.

Hot-electron effects on channel thermal noise in fine-line NMOS field-effect transistors

Abstract: Submicrometer NMOSFET's exhibit excess channel thermal noise. This excess noise increases with an increase in drain-to-source voltage and a decrease in channel length. A strong correlation between high electric field and excess noise strongly suggests hot electrons as being responsible for this excess noise.