Showing papers in "IEEE Transactions on Electron Devices in 1987"

Analytical methods for the extraction of solar-cell single- and double-diode model parameters from I-V characteristics

Abstract: Analytical solutions for the rapid extraction of single- and double-diode model parameters from experimental data are described. The resulting parameters' values are shown to have less than 10 percent error for most solar cells. Error contours are also illustrated to define the range of validity of these methods.

Measurement and Interpretation of stress in aluminum-based metallization as a function of thermal history

Abstract: Mechanical stress in interconnections is a problem of growing importance in VLSI devices. The origins of this stress are discussed, and a measurement technique based on the determination of wafer curvature with a laser scanning device is described. The changes in stress observed during thermal cycles are interpreted quantitatively in terms of a simple model of elastic and plastic strain in the metal. The effects of changes in deposition conditions, film composition, and film structure are discussed.

GaAs FET device and circuit simulation in SPICE

Abstract: We have developed a GaAs FET model suitable for SPICE Circuit simulations. The dc equations are accurate to about 1 percent of the maximum drain current. A simple but accurate interpolation formula for drain current as a function of gate-to-source voltage connects the square-law behavior just above pinchoff and the square-root law for larger values of the drain current. The ac equations, with charge-storage elements, describe the variation of the gate-to-source and gate-to-drain capacitances as the drain-to-source voltage approaches zero and when this voltage becomes negative. Under normal operating conditions the gate-to-source capacitance is much larger than the gate-to-drain capacitance. At zero drain-to-source voltage both capacitances are about equal. For negative drain-to-source voltages the original source acts like a drain and vice versa. Consequently the normally large gate-to-source capacitance becomes small and acts like a gate-to-drain capacitance. In order to model these effect it is necessary to realize that, contrary to conventional SPICE usage, there are no separate gate-to-source and gate-to-drain charges, but that there is only one gate Charge which is a function of gate-to-source and gate-to-drain voltages. The present treatment Of these capacitances permits simulations-in which the drain-to-source voltage reverses polarity, as occurs in pass-gate circuits.

Two-dimensional thermal oxidation of silicon—I. Experiments

Abstract: With continued miniaturization and the development of new devices, the highly nonuniform oxidation of two-dimensional non-planar silicon structures is playing an increasingly important role. An understanding of this subject has been limited by insufficient experimental data and difficulties in two-dimensional numerical simulation. This paper introduces a unique experimental approach in which extensive data were obtained concerning the oxidation of cylindrical silicon structures of controlled radii of curvature. It is quantitatively demonstrated that the oxidation of curved silicon surfaces is retarded at low temperatures and sharp curvatures, and that the retardation is more severe on concave than convex structures. These observations will be interpreted using a physical model based on stress effects on oxide growth parameters. The theoretical analysis and modeling will be reported in detail in a separate paper [1].

Gate-voltage-dependent effective channel length and series resistance of LDD MOSFET's

Abstract: A measurement algorithm to extract the effective channel length and source-drain series resistance of MOSFET's is presented. This extraction algorithm is applicable to both conventional and LDD MOSFET's. It is shown that the effective channel length and the source-drain series resistance of an LDD device are gate-voltage dependent. The effective channel length of an LDD device is not necessarily the metallurgical junction separation between the source and drain as it is commonly seen in a conventional device. A more generalized interpretation of effective channel length is introduced to understand the physical meaning of this gate-voltage dependence. The result also indicates that the effective channel length and source-drain resistance are two inseparable device parameters regardless of LDD or conventional FET's.

Ion-sensing devices with silicon nitride and borosilicate glass insulators

Abstract: Ion-sensitive field-effect transistors (ISFET's) with silicon dioxide, silicon nitride, and borosilicate glass as the active gate material were fabricated and tested for pH-sensing applications. The borosilicate glass and silicon nitride devices were found to have a linear potential/pH response and previous theories of ISFET function were inadequate to explain this. A two-site theory is presented that can explain the features of the potential/pH response of both silicon nitride and borosilicate glass ISFETs. The model is easily extended to any two-site system.

An SOI voltage-controlled bipolar-MOS device

Abstract: This paper describes a new operation mode of the SOI MOSFET. Connecting the floating substrate to the gate in a short-channel SOI MOSFET allows lateral bipolar current to be added to the MOS channel current and thereby enhances the current drive capability of the device. Part of the bipolar current emitted by the source terminal merges into the channel before reaching the drain, which renders the base width substantially shorter than the gate length. This novel operating mode of a short-channel SOI transistor is particularly attractive for high-speed operation, since the device is capable of both reduced voltage swing operation and high current drive, n-p-n and p-n-p devices, as well as complementary inverters have been successfully fabricated.

Scaling limits in batch-fabricated silicon pressure sensors

Abstract: The scaling properties of silicon capacitive and piezoresistive pressure sensors are described. An evaluation of the various noise mechanisms and pressure offsets in the scaled devices is presented, including Brownian noise, electrical noise, electrostatic pressure variations and pressure offset due to resistor mismatch. The analysis of diaphragm deflection includes the effects of intrinsic stress and the transition from plate theory to membrane theory. Both ultraminiature and ultrasensitive sensors are considered. Ultraminiature piezoresistive sensors with diaphragms measuring 100 µm in length and resolving 1 mmHg should be possible using present technology as well as ultrasensitive capacitive sensors that resolve 1 µmHg.

Relationship between measured and intrinsic transconductances of FET's

Abstract: In exploratory study of FET's, such as the study of deep-submicrometer-channel FET's, carrier transport quantities are extracted from the measured transconductance of a FET. The extraction requires that the intrinsic transconductance of the device be calculated from the measured one, which is generally degraded by source and drain parasitic resistances. We have derived an equation that allows the calculation of the intrinsic transconductance of a FET from the measured transconductance, under the assumption that source and drain series resistances are independent of bias. The derivation does not assume zero drain conductance, nor does it involve any specific FET model. Therefore, the derived equation works in both saturation and linear regions of a FET, regardless of its channel length. The equation was tested by adding external resistors in series with source or drain of ultra-short-channel MOSFET's. Within the accuracy of the measurements, experimental results have proved that the equation is correct.

A study of photon emission from n-channel MOSFET's

Abstract: It is known that an n-channel MOSFET, operating in the saturation region, is accompanied by visible light emission. The spectral distribution of this emitted light is reported in this paper for the first time. It behaves as exp (-α . hv) under various bias conditions (α: constant); the energy state of hot electrons is described as a Maxwell-Boltzmann distribution. The hot-electron temperature in an n-channel MOSFET is experimentally evaluated from the photon spectrum analysis. As compared with the electric field strength calculated by two-dimensional simulation, the hot-electron temperature is found to be determined as a function of the electric field strength in the drain avalanche region.

Thermal analysis of electromigration test structures

Abstract: Analytical expressions are derived for estimating the temperature profile along a straight-line resistor test structure due to the joule heating generated by a high current-density stress, such as is used in accelerated stress tests to characterize metallizations for electromigration. It is shown how an improved estimate of the mean metallization stress temperature may be made and how the thickness and thermal conductivity of the underlying electrical insulator affect the temperature profile of the metallization. Recommendations for the design of electromigration test structures are developed that will promote reduced temperature gradients in the metallization during stress testing and improved reproducibility of electromigration characterizations.

Modeling and measurement of contact resistances

Abstract: This paper presents a generalized model of ohmic contacts and a unified approach for the accurate extraction of specific contact resistivity (ρ c ) for ohmic contacts from measured contact resistance using the cross bridge Kelvin resistor, the contact end resistor, and the tranmsission line tap resistor test structures. A general three-dimensional (3-D) model of the contacts has been developed from the first principles and has been reduced to 2-D, 1-D, and 0-D (one lump) models with the necessary approximations. It is shown that the conventional I-D models overestimate the value of ρ c because of the parasitic resistance due to 2-D current flow around the periphery of the contact window. Using 2-D simulations, we have accurately modeled the current crowding effects and have extracted accurate values of ρ c independent of contact size and the test structure type. A theory of scaling of contacts has been developed and is applied to commonly used structures. A universal set of curves has been derived for each particular contact resistance test structure and, given the geometry of the structure, these allow accurate determination of ρ c , Without the actual use of the 2-D simulator. Experimental and theoretical accuracy of the three test structures has been compared. Accurate values of ρ c for various contact materials to n+and ρ+Si have been determined. The data confirm that in the past researchers have overestimated ρ c , and that ρ c will not limit device performance even with submicrometer design rules.

A semi-empirical model of the MOSFET inversion layer mobility for low-temperature operation

Abstract: This paper reports on a semi-empirical model of the mobility in the inversion layer of enhancement-type MOSFET's operated at low temperatures. The n-channel model is based on three different scattering mechanisms important at cryogenic temperatures--phonon, Coulomb, and surface roughness scattering. It is shown that the degradation of the mobility with the vertical field is accelerated at low temperatures and has a different functional form compared to that at the above room temperature. The p-channel model is the extension of a high-temperature model. The simple analytical expression presented here is suitable for use in a circuit simulation program like SPICE. The definition and the temperature dependence of the effective normal field are reexamined for both n- and p-channel devices.

Recombination in highly injected silicon

Abstract: Recent advances in solar cells designed to operate under high-level injection conditions have produced devices that are approaching some of the limits imposed by the fundamental band-to-band Auger recombination in Silicon. A device has been optimized to study this recombination by using the fabrication technology developed for point-contact solar cells. Using both steady-state and transient measurements, the recombination rates in high-resistivity Si in the injected carrier density range of 1015to 2 × 1017carriers / cm3were investigated. The coefficient of the recombination, which depends on the carrier density cubed, is found to be 1.66 × 10-30cm6/s ± 15 percent. This result is four times higher than the ambipolar Auger coefficient commonly used in the modeling of devices that operate in this injected carrier density range and lowers the expected limit efficiencies for silicon solar cells.

Resonant tunneling device with multiple negative differential resistance: Digital and signal processing applications with reduced circuit complexity

Abstract: A new approach to obtain multiple peaks in the current-voltage characteristic of a resonant-tunneling (RT) device is demonstrated. The peaks are generated using only the ground state resonance of the quantum well rather than several states, as in conventional RT devices. The separation between the peaks is voltage tunable and also the peak currents can be made nearly equal, which is necessary to use the device in a variety of circuit applications. A functional device operating at 100 K, with two peaks in the I-V has been fabricated. The first practical demonstration of circuits for frequency multiplication by a factor of five, a three-state memory and a 4-bit parity generator, using a single functional RT device each, is also reported. The use of multiple-peak RT devices in these circuits results in an order of magnitude reduction in the number component per function over conventional techniques.

The relationship between Oxide charge and device degradation: A comparative study of n- and p- channel MOSFET's

Abstract: We present a comparative study of device degradation for conventional n- and p-channel MOSFET's. The experimentally determined features of degradation are investigated with a 2-D simulation including fast and slow interface states as well as channel mobility degradation due to Coulomb scattering off these charges. Three different models concerning kind and spatial distribution are studied. We present a model that self-consistently describes the observed experimental features in the pentode and subthreshold regimes of the device. Furthermore, the substrate current is included in this analysis.

The impact of intrinsic series resistance on MOSFET scaling

Abstract: The intrinsic parasitic series resistance associated with the practical structure of a MOSFET is examined. The components considered include contact resistance, diffusion sheet resistance, spreading (injection) resistance, and accumulation layer resistance. The impact of the total resistance on MOSFET scaling is assessed, down to a channel length of 0.15 µm. The results show that, contrary to what has been claimed before, the transconductance and current of a MOSFET continue to increase as the channel length is miniaturized, although the degradation percentage-wise compared to an ideal device without series resistance continues to increase. Based on the degraded I-V characteristics and their effects on an inverter, it is shown here that for NMOS or PMOS digital circuits, the maximum degradation in speed due to series resistance is 20-35 percent compared to ideal scaling for the shortest channel considered. For CMOS circuits, the maximum degradation is reduced to 7-15 percent. In absolute terms, a loss of speed in either case due to miniaturization of channel length is not expected even down to 0.15 µm.

The spectral p-n junction model for tandem solar-cell design

Abstract: Tandem solar cells can have significantly higher efficiencies than single-junction solar cells because they convert a larger fraction of the incident solar spectrum to electricity. For the design of tandem solar cells the spectral p-n junction model is proposed. It is based on tabulated standard spectra, on the fit of experimentally achieved open-circuit voltages, and assumes a quantum efficiency of unity. By consistent treatment of the energy gap in the diode equation, the model can be quantitatively applied to all tandem solar-cell systems. The special form and use of the reverse saturation current density is discussed in detail. The spectral p-n junction model is rigorously applied based on accepted standard spectra. The tandem solar-cell performance limits based on the model are calculated. A quantitative expression for the increase in efficiency under concentration is derived. Choosing materials with optimum bandgaps, a two-solar-cell two-terminal tandem system can achieve a theoretical maximum efficiency of 38.2-percent (AM1.5 global). A two-solar-cell four-terminal tandem system can have a maximum efficiency of 39.1 percent at the same spectrum. This four-terminal system allows more freedom in choosing the most efficient bandgap combinations. Assuming realistic losses, a configuration consisting of a Si solar cell on the bottom and a solar cell with a bandgap, E g = 1.85 eV on the top, a maximum efficiency of 32.1 percent (AM1.5 global) can be predicted. Increased efficiency can be obtained from a three-solar-cell six-terminal tandem system. With an optimum bandgap combination the theoretical maximum efficiency is 44.5 percent (AM1.5 global) for the three-solar-cell system. The limits predicted by the model are discussed for tabulated standard spectra. The highest achievable efficiency is 57.3 percent (AM1.5 global) without concentration of the incident light. The increase in efficiency under concentration is evaluated, and it is found that the relative change of the efficiency at any concentration X is linear with In (X).

An ultra-low on-resistance power MOSFET fabricated by using a fully self-aligned process

Abstract: An ultra-low on-resistance power MOSFET fabricated by use of a fully self-aligned process is demonstrated. The feature of the new process is that most of the processing steps, such as channel formation, gate definition, and contact-hole opening, are carried out through a single masking step. This permits a remarkable increase in packing density, and thereby conducts the reduction of the channel resistance. A gate width per unit area of 50 cm /mm2has been implemented by using the new process with a 4-µm-pitch layout rule. This value is at least four times larger than that of the conventional VDMOSFET. The experimentally fabricated device, which possesses a total gate width of 480 cm in a 3.8 mm × 4.0 mm chip, exhibited an on-resistance of 9 mΩ and a breakdown voltage of 30 V. The resulting on-resistance area product of 137 mΩ .mm2is the smallest value ever reported.

Submicrometer-channel CMOS for low-temperature operation

Abstract: A 0.5-µm-channel CMOS design optimized for liquid-nitrogen temperature operation is described. Thin gate oxide (12.5 nm) and dual polysilicon work functions (n+-poly gate for n-channel and p+-poly for p-channel transistors) are used. The power supply voltage is chosen to be 2.5 V based on performance, hot-carrier effects, and power dissipation considerations. The doping profiles of the channel and the background (substrate or well) are chosen to optimize the mobility, substrate sensitivity, and junction capacitance with minimum process complexity. The reduced supply voltage enables the use of silicided shallow arsenic and boron junctions, without any intentional junction grading, to control short-channel effects and to reduce the parasitic series resistance at 77 K. The same self-aligned silicide over the polysilicon gate electrode reduces the sheet resistance (as low as 1 Ω/sq at 77 K) and provides the strapping between the gates of the complementary transistors. The design has been demonstrated by a simple n-well/p-substrate CMOS process with very good device characteristics and ring-oscillator performance at 77 K.

Hot-electron-induced punchthrough (HEIP) effect in submicrometer PMOSFET's

Abstract: Degradation of device characterisitics due to hot-carrier injection in submicrometer PMOSFET has been investigated. We found that in submicrometer p-channel transistors the punchthrough voltage is seriously reduced due to hot-electon-induced punchthrough (HEIP). A worst case analysis of the experimental data shows substantially reduced lifetime due to HEIP.

Self-aligned UMOSFET's with a specific on-resistance of 1 mΩ.cm 2

Abstract: This paper describes an improved UMOSFET with an ultralow specific on-resistance. This device utilizes a self-aligned process that permits closely spaced vertical trench gates with a unit cell of 6 µm. This allows for a remarkable increase of channel density and, therefore, reduces the on-resistance per unit area significantly. Experimental devices have been fabricated, and a specific on-resistance of 1.0 mΩ . cm2with a breakdown voltage of 30 V has been achieved. This specific on-resistance is the lowest value ever reported for FET's.

Electrical and physical characteristics of thin nitrided oxides prepared by rapid thermal nitridation

Abstract: Ultrathin oxides (5-12 nm) were nitrided by lamp-heated rapid thermal annealing in ammonia at temperatures of 900-1150°C for 5-300 s. Elemental depth profiles were measured by Auger electron spectroscopy (AES) and secondary ion mass spectroscopy (SIMS). Both the nitrogen concentration measured by AES and the hydrogen one measured by SIMS for a nitrided oxide are found to increase monotonically as nitridation proceeds. The AES depth profiles of oxygen show that the Si-SiO 2 interface does not move during nitridation. Dependences of midgap interface state density ( D_{it}_{m} ) and fixed charge density (N f ) on nitridation temperature and on oxide thickness were studied. For a given temperature, both D_{it}_{m} and (N f ) are found to show turnarounds as nitridation time increases in a similar manner: at first both increase, reach respective maxima at a certain nitridation time t_{\max} , and then decrease gradually. The ( D_{it}_{m} ) and (N f ) increase more rapidly and the t_{\max} is shorter as the nitridation temperature is raised or the oxide film is thinner. The maximum of D_{it}_{m} increases as the oxide film is thinner. A two-step model is newly proposed to explain the turn-around behaviors of D_{it}_{m} and N f : the first step is defect formation as a result of nitrogen incorporation and the second step is reduction of the defects by an annealing-type process. The simulation reproduces the turnaround behaviors very well.

Two-dimensional hot-electron models for short-gate-length GaAs MESFET's

Abstract: A detailed hot-electron device model suitable for modeling short-gate-length GaAs MESFET's is described. A two-dimensional numerical simulation is used to solve a set of semiclassical carrier transport equations, including a full rigorous solution of the energy conservation equation. The importance of the hot-electron effects is demonstrated and in particular the role of the electron temperature gradient in addition to velocity overshoot is emphasized. The influence of doping and mobility profiles are investigated and found to have a very significant effect on the device characteristics. The model is applied to a range of submicrometer-gate-length devices and is shown to be useful for characterizing devices with gate lengths down to less than 0.1 µm. The dependence of saturated drain current on gate length is quantified.

Hot-electron effects in Silicon-on-insulator n-channel MOSFET's

Abstract: Hot-electron degradation has been measured in short-channel bulk and SOI MOSFET's. The presence of a floating substrate in the SOI devices appears to increase the drain-saturation voltage and, therefore, to reduce the drain electric field. This effect is even further enhanced when thin fully depleted films are considered. Electrical stress measurements and device modeling suggest that hot-electron degradation should be smaller in SOI MOSFET's than in their bulk counterparts.

Hot-carrier-injected oxide region and hot-electron trapping as the main cause in Si nMOSFET degradation

Abstract: The gate oxide region affected by injected hot electrons and/or holes along the channel is experimentally determined. The oxide region varies with bias conditions, and the device degradation rate is correlated with the change in the hot-carrier injected region. Based on these results, the following degradation mechanism is proposed: 1) The degradations in transconductance, threshold voltage, and subthreshold slope can be caused mainly by trapped electrons, but not generated interface states. 2) Enhanced degradation due to both hot-electron and hole injections is caused by electrons trapped in neutral centers produced by hot-hole injection.

Transport and related properties of (Ga, Al)As/GaAs double heterostructure bipolar junction transistors

Abstract: This paper presents a study of the transport and related properties of GaAs double heterostructure bipolar junction transistors with GaAlAs emitters and collectors utilizing both graded and abrupt junctions. By studying the temperature dependence of current-voltage characteristics, the recombination mechanisms in the transition regions associated with the base-emitter, the base-collector junction, and the quasi-neutral base region have been quantitatively separated. The junction corresponding to growth of GaAs on GaAlAs is found to have higher nonradiative recombination. For abrupt junctions, it also shows a lower barrier for electron injection than does the GaAlAs/GaAs junction. At mid-1018cm-3base doping, the junctions show ideal emission/ diffusion transport at high currents, recombination-dominated transport in a medium current range, and transport with a characteristic energy greater than twice the thermal energy at very low currents. Due to excess recombination current in the devices, the offset voltage is shown to be sensitive to the ratio of emitter and collector junction areas. At low temperatures, transport across the injecting interface of abrupt devices is dominated by tunneling and in the quasi-neutral base by diffusion. The devices exhibit gain at temperatures as low as 4.2 K. The current gain below 77 K appears to be limited by radiative recombination lifetime, and at higher temperatures by nonradiative recombination and injection efficiency. Transistors with current gains of 300 to 500 have been achieved at small emitter dimensions of 1.6 µm × 4.0 µm and at current densities exceeding 105A . cm-2. At current densities of 100 A . cm-2, some of the transistors exhibited gains approaching 100. These devices had an offset voltage of less than 100 mV. Self-aligned devices have also been fabricated and show current gains of 20 to 50 at similar dimensions. In the inverted configuration, gains of up to 50 were observed for non-self-aligned transistors. The dependence of device Characteristics upon the structure indicates that surface effects are minimal. The negative resistance exhibited by these devices at high currents is shown to be due to temperature effects resuiting from the 10-µs or lower thermal time constants.

A self-aligned CoSi 2 interconnection and contact technology for VLSI applications

Abstract: Cobalt silicide is investigated in view of possible application in a self-aligned technology. Extremely smooth, highly conductive CoSi 2 films are obtained using rapid thermal processing for silicide formation starting from deposited cobalt layers (on Si). The phase formation is studied by XRD and RBS. No lateral silicide formation is observed at contact edges. The influence of Si consumption and dopant behavior on diode performance is studied. Shallow arsenic (0.15 µm deep) and boron (0.3 µm deep) junctions are successfully silicided. Very low contact resistances are obtained between the silicide and n+ and p+ regions. MOS transistors were fabricated with CoSi 2 on the source, drain, and gate. An increase in current driving capability is noticed while no degradation of other electrical parameters due to the silicide processing steps is observed. At some critical points, comparison is made with the TiSi 2 process.

Substrate current at cryogenic temperatures: Measurements and a two-dimensional model for CMOS technology

Abstract: This work characterizes the temperature, channel length, and voltage dependences of substrate current, and presents a local model describing this behavior using Shockley's lucky electron (LE) model as a basis. For n-channel (p-channel) devices, the model is extended using a Maxwell-Boltzmann (MB) distribution of hot-electron (hole) energies above (below) the conduction (valence) band minimum (maximum). The model has been implemented in CADDET, a 2-D device simulator, and is able to explain all of the important features of substrate current which have been reported to date. The model is discussed in the context of works which look at both the local and physical nature of the impact ionization phenomenon. Based on this discussion, the model's parameters are shown to have a solid physical basis, requiring no reliance on curve fitting. The agreement between data and simulations thus enhances physical understanding of substrate current in MOSFET's, and warrants confident design of CMOS technologies for cryogenic operation.

Interconnection and electromigration scaling theory

Abstract: Interconnections will become the limit in performance and reliability at submicrometer dimensions. Long-distance interconnections are defined using models based on resistivity, and it is found that more than half of the interconnections will become categorized as such at 0.5-µm feature sizes. The resistivity of even less resistive materials, therefore, will become important. A model for analyzing the trends of material usage for interconnections and for projecting design rules is presented. Electromigration is the driving force away from the lowest resistivity silicon compatible material, namely aluminum. Replacements such as gold, however, have technological problems and the resistivity of refractory metals will be too high for a large fraction of the interconnections. Layered structures are one possible solution to the problems of electromigration and hillocks.