Showing papers in "IEEE Transactions on Electron Devices in 1988"
TL;DR: In this paper, the authors proposed a simplified mathematical formulation made possible by the symmetry in cylindrical structures, and compared with experimental data, possible applications, and limitations of the model are also discussed.
Abstract: For pt.I see ibid., vol.ED-34, p.1008-17 (May 1987). The authors propose that the stress from two-dimensional oxide deformation affects the kinetic parameter in the Deal-Grove model (1965). In particular, the viscous stress associated with the nonuniform deformation of the oxide is identified as the fundamental force of retardation. In this model, the stress normal to the Si-SiO/sub 2/ interface reduces the surface reaction rate in both convex and concave surfaces, whereas the stress in the bulk of the oxide (compressive for concave and tensile for convex surfaces) is responsible for the thinner oxides on the concave structures. The model is described by a simplified mathematical formulation made possible by the symmetry in cylindrical structures. Comparisons with experimental data, possible applications, and limitations of the model are also discussed. >
423 citations
TL;DR: In this article, the degradation behavior of n-channel transistors under alternating injection conditions is discussed and fully explained based on the static stress degradation model for both channel types using the charge-pumping technique.
Abstract: A model is derived using the charge-pumping technique for the evaluation of the interface characteristics, in combination with the behavior of the drain and the substrate currents after degradation For n-channel transistors the degradation is mainly caused by the generation of interface traps Only in the region of hole injection (V/sub g/ approximately=V/sub t/) is the degradation dominated by the trapped holes, which mask the effect of the generated interface traps The degradation of p-channel transistors, although completely different at first sight, occurs by the same mechanisms For this case, the degradation is caused by trapped negative charge, which masks the influence of the interface traps The latter are nevertheless generated in comparable amounts as in n-channel transistors Based on these insights, improved procedures for accelerated-lifetime experiments are proposed for both channel types Finally, the peculiar degradation behavior of n-channel transistors under alternating injection conditions is discussed and fully explained based on the static stress degradation model >
415 citations
TL;DR: In this article, a technique of predicting the lifetime of an oxide to different voltages, different oxide areas, and different temperatures is presented using the defect density model in which defects are modeled as effective oxide thinning, many reliability parameters such as yield, failure rate and screen time/screen yield can be predicted.
Abstract: A technique of predicting the lifetime of an oxide to different voltages, different oxide areas, and different temperatures is presented. Using the defect density model in which defects are modeled as effective oxide thinning, many reliability parameters such as yield, failure rate, and screen time/screen yield can be predicted. This modeling procedure is applicable to both wafer-level and long-term reliability tests. Process improvements including defect gettering and alternative dielectrics such as chemical-vapor-deposited oxides are evaluated in the format of defect density as a function of effective oxide thinning. >
367 citations
TL;DR: In this article, movable pin-joints, gears, springs, cranks, and slider structures with dimensions measured in micrometers have been fabricated using silicon microfabrication technology.
Abstract: Movable pin-joints, gears, springs, cranks, and slider structures with dimensions measured in micrometers have been fabricated using silicon microfabrication technology. These micromechanical structures, which have important transducer applications, are batch-fabricated with an IC-compatible process. The movable mechanical elements are built on layers that are later removed so that they are freed for translation and rotation. An undercut-and-refill technique, which makes use of the high surface mobility of silicon atoms undergoing chemical vapor deposition, is used to refill undercut regions in order to form restraining flanges. Typical element sizes and masses are measured in micrometers and nanograms. The process provides the tiny structures in an assembled form avoiding the nearly impossible challenge of handling such small elements individually. >
318 citations
TL;DR: In this paper, a cantilever-type micromachined silicon actuator based on the bimetal effect used extensively for the fabrication of temperature-controlled electrical switches is described.
Abstract: A cantilever-type micromachined silicon actuator based on the bimetal effect used extensively for the fabrication of temperature-controlled electrical switches is described. The silicon actuator consists of a Si-metal sandwich layer and an integrated poly-Si heating resistor as a driving element. Due to the low heat capacity of the transducer element, a high temperature increase per input power unit can be achieved. For a (Si-Au)-cantilever-type actuator, 500- mu m long and several micrometers thick, a specific deflection of approximately 0.1 mu m/K at the free end has been measured. The design considerations, fabrication process, and experimental results of the actuator are discussed. >
315 citations
TL;DR: In this article, the authors proposed that the oxide leakage originates from localized defect-related weak spots where the insulator has experienced significant deterioration from electrical stress, and the leakage conduction mechanism appears to be thermally assisted tunneling through the locally reduced injection barrier.
Abstract: Very thin thermal oxides are shown to exhibit a failure mode that is undetected by conventional breakdown tests. This failure mode appears in the form of excessive leakage current at low field and is induced by high-field stresses. The stress-induced oxide leakage is permanent and stable with time and thermal annealing. It becomes the dominant failure mode of thin oxides because it always precedes destructive breakdown. Experimental results and theoretical calculations show that the leakage current is not caused by positive charge generation and accumulation in the oxide. It is proposed that the oxide leakage originates from localized defect-related weak spots where the insulator has experienced significant deterioration from electrical stress. The leakage conduction mechanism appears to be thermally assisted tunneling through the locally reduced injection barrier, and the model seems to be consistent with both I-V measurements at temperatures from 77 K to 250 degrees C and theoretical calculations. >
277 citations
TL;DR: In this paper, a microsensor that uses ultrasonic Lamb waves propagating in a thin plate supported by a silicon die is presented, which can operate as a microphone, biosensor, chemical vapor or gas detector, scale, pressure sensor, densitometer, radiometer or thermometer.
Abstract: Initial experimental, analytical, and numerical evaluations of a microsensor that uses ultrasonic Lamb waves propagating in a thin plate supported by a silicon die are presented. Changes of oscillator frequency indicate magnitudes of the variables sensed. Because it is sensitive to many measurands, the device could operate as a microphone, biosensor, chemical vapor or gas detector, scale, pressure sensor, densitometer, radiometer, or thermometer. Because it is based on the use of Lamb waves, the sensor has selective response and sensitive operation in the low-megahertz frequency range in vacuum, in a gas, or while immersed in a liquid. >
264 citations
TL;DR: In this paper, a planar polysilicon mechanism incorporating lower and higher kinematic pairs (or joints) was described, which is compatible with silicon microfabrication technology.
Abstract: The integrated fabrication of planar polysilicon mechanisms incorporating lower and higher kinematic pairs (or joints) is described. The two lower kinematic pairs (revolute and prismatic) commonly used in macrorobotic systems are compatible with silicon microfabrication technology. The mechanisms are fabricated by surface micromachining techniques using polysilicon as the structural material and oxide as the sacrificial material. Turbines with gear and blade rotors as small as 125 mu m in diameter and 4.5 mu m in thickness were fabricated on 20- mu m-diameter shafts. A clearance as tight as 1.2 mu m was achieved between the gear and the shaft. Gear trains with two or three sequentially-aligned gears were successfully meshed. A submillimeter pair of tongs with 400- mu m range-of-motion at the jaws was fabricated. This structure incorporates a single prismatic joint and two revolute joints, demonstrating linear-to-rotary motion conversion. >
213 citations
TL;DR: In this article, a microfabricated floating-element shear-stress sensor for measurements in turbulent boundary-layers is reported using surface micromachining of polyimide.
Abstract: A microfabricated floating-element shear-stress sensor for measurements in turbulent boundary-layers is reported. Using surface micromachining of polyimide, a 500- mu m*500- mu m probe has been fabricated incorporating a differential-capacitor readout circuit. A model for the sensor response is described and is used for the design of an element to measure shear stresses of 1 Pa in air. The sensor is packaged for calibration in laminar flow, and electrical results obtained match the expected response. >
211 citations
TL;DR: In this article, a novel method was presented to determine Si-SiO/sub 2/ interface recombination parameters, and the cross-section for capturing electrons was found to exceed the cross section for capturing holes by a factor of 10/sup 2/ to 10 /sup 3.
Abstract: A novel method is presented to determine Si-SiO/sub 2/ interface recombination parameters. The device used is a polysilicon-oxide-semiconductor capacitor with a microscale central junction (a gate-controlled point-junction diode). Data analysis has been performed using a numerical scheme to find a quasi-exact solution for the current combining at the interface. It was found that the interface recombination parameters depend only weakly on trap energy in a wide range around midgap. The cross-section for capturing electrons was found to exceed the cross-section for capturing holes by a factor of 10/sup 2/ to 10/sup 3/. >
208 citations
TL;DR: A comparison of the effect of bias on the total delay through standard and pseudomorphic MODFETs suggests that the excellent microwave performance exhibited by the pseudomorphic device arises from a reduction in parasitic and drain delays and not from a higher electron velocity under the gate as mentioned in this paper.
Abstract: MODFETs have been fabricated using heterojunctions consisting of AlGaAs and pseudomorphic InGaAs, grown on GaAs substrates. The large conduction band discontinuity (about 0.46 eV for 25% In and Al concentration) leads to a 2-D electron density as high as 2.3*10/sup 12/ cm/sup -2/, with electron mobilities of 7000 and 16000 cm/sup 2//V-s at 300 and 77 K, respectively. Such a high electron density in combination with reasonable transport properties leads to MODFETs with exceptional characteristics. Devices with 0.15-0.25- mu m gate length have room-temperature drain currents as high as 600 mA/mm and room-temperature transconductance as high as 500 mS/mm. The f/sub T/ is as high as 98 GHz, as determined by 20-dB/decade extrapolation of microwave data taken to 25 GHz. A comparison of the effect of bias on the total delay through standard and pseudomorphic MODFETs suggests that the excellent microwave performance exhibited by the pseudomorphic device arises from a reduction in parasitic and drain delays and not from a higher electron velocity under the gate. >
TL;DR: In this article, the role of surface states in the operation of GaAs MESFETs is emphasized and a theory that ties together hitherto unconnected anomalies in device behavior is presented.
Abstract: A theory that emphasizes the role of surface states in the operation of GaAs MESFETs and that is intended to tie together hitherto unconnected anomalies in device behavior is presented. Such undesirable effects are consistent with the DC and microwave characteristics of the FET being modified by charge exchange with surface states. Generally speaking, these states are relatively slow, having characteristics frequencies of typically 1 kHz, but they nevertheless affect the microwave scattering parameters of the FET through the distortion they introduce to the shape of the depletion region in the transistor under given bias conditions. It is argued that the FET structure behaves as natural 'probe' of surface states and so constitutes a useful analytic tool for studying states on a variety of unpassivated and passivated surfaces. >
TL;DR: In this paper, the authors demonstrate that polysilicon films with built-in tensile-strain can be achieved and that any physical size limitations due to compressive-buckling in poly-silicon micromechanical structures can be eliminated.
Abstract: Novel processing conditions and strain diagnostic structures are used to demonstrate that polysilicon films with built-in tensile-strain can be achieved and that any physical size limitations due to compressive-buckling in polysilicon micromechanical structures can be eliminated. >
TL;DR: An ultraminiature solid-state capacitive pressure sensor that can be mounted in a 0.5mm OD catheter suitable for multipoint pressure measurements from within the coronary artery of the heart is described in this paper.
Abstract: An ultraminiature solid-state capacitive pressure sensor that can be mounted in a 0.5-mm OD catheter suitable for multipoint pressure measurements from within the coronary artery of the heart is described. The transducer consists of a silicon 290*550*1.5- mu m/sup 3/ microdiaphragm surrounded by a 12- mu m-thick silicon supporting rim, both defined by the boron etch-stop technique. The transducer process features a batch wafer-to-glass electrostatic seal followed by the silicon etch, which eliminates handling of individual small diaphragm structures until die separation and final packaging. A hybrid interface circuit chip provides a high-level output signal and allows the sensor to be compatible with use on a multisite catheter having only two leads. >
TL;DR: In this article, a measurement technique based on the determination of wafer curvature with a laser scanning device is utilized to directly measure the film stress in situ as a function of temperature during thermal cycling.
Abstract: Mechanical stress in interconnection is a problem of growing importance in VLSI devices. Open circuits due to metal cracking and voiding and short circuits due to hillocks are stress-related phenomena. The origins of this stress are discussed including intrinsic stresses from the synthesis of the films and thermally induced stresses. A measurement technique based on the determination of wafer curvature with a laser scanning device is utilized to directly measure the film stress in situ as a function of temperature during thermal cycling. The changes in stress observed during thermal cycles are interpreted quantitatively and mechanisms that lead to plastic deformation and their relationship to hillocks are discussed. In the stress vs. temperature measurements, several regions have been identified including elastic and plastic behavior both under compression and tension, the yield strength, recrystallization, gain growth, hardening, and solid-state reactions. The effects of deposition conditions on these regions are also examined. >
TL;DR: In this paper, the spatial profiles of hot-carrier-induced interface traps in MOSFETs with abrupt arsenic junctions and oxide thickness of 10-38 nm were determined using charge pumping both in the conventional manner and with a modified constant-field approach.
Abstract: The spatial profiles of hot-carrier-induced interface traps in MOSFETs with abrupt arsenic junctions and oxide thickness of 10-38 nm are determined using charge pumping both in the conventional manner and with a modified constant-field approach. For the thinnest oxides the damage is highly localized in a very sharp peak that is located inside the drain at the point of maximum lateral electric field. In thicker oxides, the damage peak is broader and is shifted toward the edge of the drain junction. Two-dimensional device simulations using the measured profiles are in qualitative agreement with measured I-V characteristics after degradation. However, the magnitude of the predicted degradation is underestimated, suggesting that significant electron trapping occurs also. >
TL;DR: In this paper, an AlGaAs/GaAs heterojunction bipolar transistor (HBT) structure with an n-p/sup +/sub 1/i-P/sup+/sub 2/n/Sup +/ doping profile that enables electron collection in the Gamma-valley of GaAs is presented.
Abstract: An AlGaAs/GaAs heterojunction bipolar transistor (HBT) structure with an n-p/sup +//sub 1/-i-p/sup +//sub 2/-n/sup +/ doping profile that enables electron collection in the Gamma -valley of GaAs is presented. In fabricated HBTs operating at low collector current density, f/sub T/ reaches its peak value when the potential variation in the i collector layer is around 0.4 V, which indicates that the electron transport is dominated by the Gamma -valley feature in GaAs. A high f/sub T/ value of 105 GHz obtained at a collector current density of 5*10/sup 4/ A/cm/sup 2/ also demonstrates the significance of the proposed near-ballistic collection structure. >
TL;DR: In this article, it is shown that the classical equations are accurate for predicting drain current for devices with effective channel lengths as small as 0.3 mu m. However, accurate substrate current modeling requires a more detailed level of simulation even for devices having longer channel lengths.
Abstract: Classical semiconductor equations are based on the thermal equilibrium approximation. Limitations introduced by this approximation for the 2-D numerical modeling of n-channel silicon submicrometer MOS transistors are investigated. It is shown that the classical equations are accurate for predicting drain current for devices with effective channel lengths as small as 0.3 mu m. However, accurate substrate current modeling requires a more detailed level of simulation even for devices with longer channel lengths. The solution of the energy conservation equation is discussed. >
TL;DR: In this paper, a charge-based large-signal transient model for the enhancementmode thin-film SOI MOSFET in strong inversion is presented, which is suitable for circuit simulators such as SPICE.
Abstract: A charge-based large-signal transient model for the enhancement-mode thin-film SOI MOSFET in strong inversion, suitable for circuit simulators such as SPICE, is presented. The model physically accounts for the predominant short-channel effects in MOSFET's (namely threshold-voltage reduction, drain-induced conductivity enhancement, velocity saturation with mobility degradation, and channel-length modulation) as influenced by the unique features of thin SOI devices (i.e. the presence of an additional back gate and the possibility of a floating film body). It includes a description of generation current due to (weak) impact ionization, which can have a far greater influence on SOI (as compared to bulk) MOSFET's due to the associated charging of the floating body. Measurements on devices of varied geometry show good agreement with model predictions. The model is implemented in SPICE2, to be used for circuit and device CAD, and TECAP, for automated parameter extraction. >
TL;DR: In this paper, the degradation of polysilicon emitter transistor gain under DC stress conditions can be modelled by Delta I/sub B/ where n approximately=0.5 and m approximately= 0.5.
Abstract: In self-aligned polysilicon emitter transistors a large electric field existing at the periphery of the emitter-base junction under reverse bias can create hot-carrier-induced degradation. The degradation of polysilicon emitter transistor gain under DC stress conditions can be modelled by Delta I/sub B/ varies as I/sub R//sup m+n/t/sup n/ where n approximately=0.5 and m approximately=0.5. The more complex relationships of Delta beta (I/sub C/, I/sub R/, t) and beta (I/sub C/, I/sub R/, t) result naturally from the simple Delta I/sub B/ model. Using these relationships the device lifetime can be extrapolated over a wide range of reverse stress currents for a given technology. >
TL;DR: In this article, the authors considered nonstationary transport effects in III-V compound semiconductors and proposed a solution method for its equations and applied it to a two-dimensional simulation of submicrometer GaAs MESFETs.
Abstract: Nonstationary transport effects in III-V compound semiconductors are taken into account by the well-known full dynamic transport model. A solution method for its equations is proposed and applied to a two-dimensional simulation of submicrometer GaAs MESFETs. Stationary and nonstationary results are compared with results from other transport models, namely a simplified dynamic transport model, the energy transport model, and the drift-diffusion model. >
TL;DR: In this article, germanium ion implantation was carried out over the energy range of 50-125 keV and at doses from 3*10/sup 14/ to 1*10 /sup 15/ cm/sup -2/ to form the n/sup +/-p junctions.
Abstract: Shallow p/sup +/-n and n/sup +/-p junctions were formed in germanium preamorphized Si substrates. Germanium implantation was carried out over the energy range of 50-125 keV and at doses from 3*10/sup 14/ to 1*10/sup 15/ cm/sup -2/. p/sup +/-n junctions were formed by 10-keV boron implantation at a dose of 1*10/sup 15/ cm/sup -2/. Arsenic was implanted at 50 keV at a dose of 5*10/sup 15/ cm/sup -2/ to form the n/sup +/-p junctions. Rapid thermal annealing was used for dopant activation and damage removal. Ge, B, and As distribution profiles were measured by secondary ion mass spectroscopy. Rutherford backscattering spectrometry was used to study the dependence of the amorphous layer formation on the energy and dose of germanium ion implantation. Cross-sectional transmission electron microscopy was used to study the residual defects formed due to preamorphization. Complete elimination of the residual end-of-range damage was achieved in samples preamorphized by 50-keV/1*10/sup 15/ cm/sup -2/ germanium implantation. Areal and peripheral leakage current densities of the junctions were studied as a function of germanium implantation parameters. The results show that high-quality p/sup +/-n and n/sup +/-p junctions can be formed in germanium preamorphized substrates if the preamorphization conditions are optimized. >
TL;DR: The effect of 950 degrees C low-pressure (0.01- or 0.1-atm) nitridation and low pressure reoxidation on the electrical properties of thin (12-nm) silicon dioxide films for scaled MOS devices was studied in this article.
Abstract: The effect of 950 degrees C low-pressure (0.01- or 0.1-atm) nitridation and low-pressure reoxidation on the electrical properties of thin (12-nm) silicon dioxide films for scaled MOS devices was studied. Turnarounds in fixed positive charge, interface state density, electron trapping, and interface state generation under electrical stress were observed with increasing nitridation. Compare to atmospheric nitridations, the turnarounds occur more gradually in the case of low-pressure nitridation. Low-pressure nitrides oxides also differ from atmospheric nitrided oxides in that a suppression of interface state generation is not normally seen. However, low-pressure nitridation and subsequent reoxidation greatly improves reliability. These attributes in the preturnaround regime of the low-pressure nitridation/reoxidation process were used to optimise the electrical properties of the dielectric. >
TL;DR: In this article, a substrate current model and a quasistatic hot-electron-induced MOSFET degradation model have been implemented using the Substrate Current And Lifetime Evaluator (SCALE) package.
Abstract: A substrate current model and a quasistatic hot-electron-induced MOSFET degradation model have been implemented using the Substrate Current And Lifetime Evaluator (SCALE) package. It is shown that quasistatic simulation is valid for a class of waveforms that includes those encountered in inverter-based logic circuits. The validity and limitations of the model are illustrated with experimental results. SCALE is linked to SPICE externally in a pre- and postprocessor fashion to form an independent simulator. The preprocessor interprets the input deck and requests SPICE to output the transient node voltages of the user-selected devices. The postprocessor then calculates the transient substrate current and makes a lifetime prediction. >
TL;DR: In this article, the authors proposed a breakdown model including the effects of floating substrate and finite silicon thickness, and calculated I-V characteristics in the breakdown region agree well with the experimental results, showing that the drain-source breakdown voltage of SOI n-MOSFETs increases with increasing channel length, increasing positive substrate voltage, and decreasing silicon film thickness.
Abstract: A proposed breakdown model includes the effects of floating substrate and finite silicon thickness. The calculated I-V characteristics in the breakdown region agree well with the experimental results. The results show that (1) the drain-source breakdown voltage of silicon-on-insulator (SOI) n-MOSFETs increases with increasing channel length, increasing positive substrate voltage, and decreasing silicon film thickness; and (2) SOI n-MOSFETs have higher breakdown voltage than their bulk-silicon counterparts at large gate bias, but lower breakdown voltage at small gate bias. >
TL;DR: In this paper, the results of inhomogeneous hot-carrier injection experiments in which static and dynamic stresses are applied to n-MOSFETs are presented and a qualitative model in which holes play a key role for the final formation of interface states is developed.
Abstract: The results of inhomogeneous hot-carrier injection experiments in which static and dynamic stresses are applied to n-MOSFETs are presented. A qualitative model in which holes play a key role for the final formation of interface states is developed. The holes are injected and trapped within the strained oxide region. The hole-injection process is controlled by hole traps in the oxide, close to the interface. With this model, a large number of dynamic and static hot-carrier stress experiments are consistently explained. Finally, a simple method by which the lifetime of a device under real operation can be predicted from dynamic stress experiments is given. >
IBM1
TL;DR: In this article, the reverse-stress-induced junction degradation can be eliminated by properly designing the circuit when the logic swing is less than the V/sub be/ of the transistors.
Abstract: The stress-induced leakage current is predominantly a Shockley-Read-Hall-like generation-recombination current. As the stress progresses, the leakage current increases, eventually reaches a maximum and then decays. The leakage current lowers the current gain at low biases. It affects the narrow-emitter transistors more since it is proportional to the emitter edge length. But, its impact is less significant if the transistor is operated at a high V/sub be/, as required by constant-current scaling. The loss of the current gain does not affect the circuit speed directly. Instead, it reduces the logic swing and thus the noise margin of the circuit. The design to absorb the degradation with a larger initial logic swing results in a speed penalty. The reverse-stress-induced junction degradation can be eliminated by properly designing the circuit There is no concern for emitter-coupled logic (ECL) circuits when the logic swing is less than the V/sub be/ of the transistors. >
TL;DR: In this paper, the issues of protection between V/sub DD/ and V/ sub SS/ are discussed and examples of how protection circuit performance can be sensitive to internal chip layout, independent of its effective design.
Abstract: Input/output electrostatic discharge (ESD) circuit requirements call for good protection of the pin with respect to both the ground and the power bus pins. Although effective protection can be designed at the pin many cases of damage phenomena are known to occur internal to the chip beyond the protection circuit. Here, the issues of protection between V/sub DD/ and V/sub SS/ are discussed first. This is followed by examples of how protection circuit performance can be sensitive to internal chip layout, independent of its effective design. Several illustrative actual case studies are reported to emphasize the internal chip ESD phenomena and their adverse effects. >
TL;DR: In this article, a comprehensive model for electron transport mechanisms across a fully formed Schottky-barrier junction is proposed in which the metal-semiconductor interface is approximated as an abrupt quantum mechanical transition.
Abstract: A comprehensive model for electron transport mechanisms across a fully formed Schottky-barrier junction is proposed in which the metal-semiconductor interface is approximated as an abrupt quantum mechanical transition. Improved formulations of the barrier-lowering mechanisms and carrier tunneling effects are derived where the dipole barrier lowering is modeled as a single exponential decay of the total surface charge density. Quantum calculations follow a two-band model in which the imaginary component of the electron wave vector in the semiconductor energy gap is obtained by including the effect of both conduction and valence states. The energy band profile effects are included in the calculation of tunneling current, and it is shown that the finite negative charge residing at the metal-semiconductor interface considerably modulates the tunneling transmission probability of carriers. Experimental results obtained from atomically clean Al-n/sup +/GaAs-nGaAs interfaces fabricated by in situ molecular-beam epitaxy (MBE) are shown to be in excellent agreement with the transport calculations. >
NEC1
TL;DR: In this article, the authors examined the TDDB lifetime for thermally grown 57-190-A SiO/sub 2/Si films in a polycrystalline silicon-SiO-sub 2/-Si structure prepared on n-type and p-type wafers.
Abstract: Gate oxide wearout for thermally grown 57-190-A SiO/sub 2/ films in a polycrystalline silicon-SiO/sub 2/-Si structure prepared on n-type and p-type wafers was studied by examining time-dependent dielectric breakdown (TDDB) under 1-mA/cm/sup 2/ constant current with positive and negative voltages at 250 degrees C. TDDB lifetimes for positive voltage stress are more than one order longer than those for negative voltage stress. TDDB lifetimes depend on oxide thickness, that is, they increase for positive voltage stress and decreases for negative voltage stress with decreasing oxide thickness. They also depend on whether the oxide films are prepared on n-type or p-type wafers. After the positive voltage TDDB stress, negative charges are predominantly produced in the oxide layer, and the electric field at the cathode in the oxide film slightly decreases. On the contrary, after the negative voltage TDDB stress, positive charges are predominantly produced at the cathode in the oxide layer and the electric field at the cathode is built up, resulting in an increase in Fowler-Nordheim tunnel current flowing though the oxide film. >