Showing papers in "IEEE Transactions on Electron Devices in 1992"

Scaling the Si MOSFET: from bulk to SOI to bulk

Abstract: Scaling the Si MOSFET is reconsidered. Requirements on subthreshold leakage control force conventional scaling to use high doping as the device dimension penetrates into the deep-submicrometer regime, leading to an undesirably large junction capacitance and degraded mobility. By studying the scaling of fully depleted SOI devices, the important concept of controlling horizontal leakage through vertical structures is highlighted. Several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design. The concept of vertical doping engineering can also be realized in bulk Si to obtain good subthreshold characteristics without large junction capacitance or heavy channel doping. >

A new recombination model for device simulation including tunneling

Abstract: A recombination model for device simulation that includes both trap-assisted tunneling (under forward and reverse bias) and band-to-band tunneling (Zener tunneling) is presented. The model is formulated in terms of analytical functions of local variables, which makes it easy to implement in a numerical device simulator. The trap-assisted tunneling effect is described by an expression that for weak electric fields reduces to the conventional Shockley-Read-Hall (SRH) expression for recombination via traps. Compared to the conventional SRH expression, the model has one extra physical parameter, the effective mass m*. For m*=0.25 m/sub 0/ the model correctly describes the experimental observations associated with tunneling. The band-to-band tunneling contribution is found to be important at room temperature for electric fields larger than 7*10/sup 5/ V/cm. For dopant concentrations above 5*10/sup 17/ cm/sup -3/ or, equivalently, for breakdown voltages below approximately 5 V, the reverse characteristics are dominated by band-to-band tunneling. >

A functional MOS transistor featuring gate-level weighted sum and threshold operations

Abstract: A functional MOS transistor is proposed which works more intelligently than a mere switching device. The functional transistor calculates the weighted sum of all input signals at the gate level, and controls the 'on' and 'off' of the transistor based on the result of such a weighted sum operation. Since the function is quite analogous to that of biological neurons, the device is named a neuron MOSFET, or neuMOS (vMOS). The device is composed of a floating gate and multiples of input gates that capacitively interact with the floating gate. As the gate-level sum operation is performed in a voltage mode utilizing the capacitive coupling effect, essentially no power dissipation occurs in the calculation, making the device ideal for ULSI implementation. The basic characteristics of neuron MOSFETs as well as of simple circuit blocks are analyzed based on a simple transistor model and experiments. Making use of its very powerful function, a number of interesting circuit applications are explored. A soft hardware logic circuit implemented by neuMOS transistors is also proposed. >

50-nm self-aligned-gate pseudomorphic AlInAs/GaInAs high electron mobility transistors

Abstract: The design and fabrication of a class of 50-nm self-aligned-gate pseudomorphic AlInAs/GaInAs high electron mobility transistors (HEMTs) with potential for ultra-high-frequency and ultra-low-noise applications are reported. These devices exhibit an extrinsic transconductance of 1740 mS/mm and an extrinsic current-gain cutoff frequency of 340 GHz at room temperature. The small-signal characteristics of a pseudomorphic and a lattice-matched AlInAs/GaInAs HEMT with similar gate length (50 nm) and gate-to-channel separation (17.5 nm) are compared. The former demonstrates a 16% higher transconductance and a 15% higher current-gain cutoff frequency, but exhibits a 38% poorer output conductance. An analysis of the high-field transport properties of ultra-short gate-length AlInAs/GaInAs HEMTs shows that a reduction of gate length from 150 to 50 nm neither enhances nor reduces their average velocity. In contrast, the addition of indium from 53% to 80% improves this parameter by 19%. >

Dependence of thin-oxide films quality on surface microroughness

Abstract: The effects of silicon surface microroughness on electrical properties of thin-oxide films, such as breakdown electric field intensity (E/sub BD/) and time-dependent dielectric breakdown (Q/sub BD/), have been studied, where the microroughnesses of silicon and silicon dioxide surfaces are evaluated by the scanning tunneling microscope (STM) and the atomic force microscope (AFM), respectively. An increase of surface microroughness has been confirmed to severely degrade the E/sub BD/ and Q/sub BD/ characteristics of thin-oxide films with thicknesses of 8-10 nm and to simultaneously decrease channel electron mobility. An increase of surface microroughness has been demonstrated to originate mainly from wet chemical cleaning processing based on the RCA cleaning concept, particularly the ammonium-hydrogen-peroxide cleaning step. In order to keep the surface microroughness at an initial level, the content ratio of NH/sub 4/OH/H/sub 2/O/sub 2//H/sub 2/O solution has been set at 0.05:1:5 and the room-temperature DI water rinsing has been introduced right after the NH/sub 4/OH/H/sub 2/O/sub 2//H/sub 2/O cleaning step in conventional RCA cleaning procedure. >

Effect of dead space on gain and noise of double-carrier-multiplication avalanche photodiodes

Abstract: The effect of dead space on the statistics of the gain in a double-carrier-multiplication avalanche photodiode (APD) is determined using a recurrence method. The dead space is the minimum distance that a newly generated carrier must travel in order to acquire sufficient energy to become capable of causing an impact ionization. Recurrence equations are derived for the first moment, the second moment, and the probability distribution function of two random variables that are related, in a deterministic way, to the random gain of the APD. These equations are solved numerically to produce the mean gain and the excess noise factor. The presence of dead space reduces both the mean gain and the excess noise factor of the device. This may have a beneficial effect on the performance of the detector when used in optical receivers with photon noise and circuit noise. >

Electrical characteristics of ferroelectric PZT thin films for DRAM applications

Abstract: Ferroelectric lead zirconate titanate (PZT) films with as much as 2.5 times the storage capacity of the best reported silicon oxide/nitride/oxide (ONO) stacked dielectrics have been fabricated. A 2000-AA film with an effective SiO/sub 2/ thickness of 10 AA is demonstrated. Because of the extremely high dielectric constant ( epsilon /sub r/>or approximately=>1000), even larger storage capacities can be obtained by scaling the ferroelectric film thickness, whereas the thickness of ONO films is limited by direct tunneling through the film. Electrical conduction in the PZT films studied is ohmic at electric fields below 250 kV/cm and follows an exponential field dependence at higher fields, which is shown to be consistent with a simple model for electronic hopping through the film. Leakage current as low as 9*10/sup -8/ A/cm/sup 2/ at 2.5 V for a 4000-AA film is obtained with the addition of La and Fe to compensate for Pb and O vacancies in the film. Further improvement in both leakage current and time-dependent dielectric breakdown characteristics are necessary to ensure reliable DRAM operation. >

A new analytical diode model including tunneling and avalanche breakdown

Abstract: An analytical model describing reverse and forward DC characteristics is presented. It serves as a basis for a compact model for circuit simulation purposes. The model is based on the solution of the hole continuity equation in the depletion layer of a p-n junction and incorporates the following physical mechanisms: band-to-band tunneling, trap-assisted tunneling (both under forward and reverse bias), Shockley-Read-Hall recombination, and avalanche breakdown. It contains seven parameters which can be determined at one temperature. No additional parameters are needed to describe the temperature dependence. From comparisons with both numerical simulations and measurements it is found that the model gives an adequate description of the DC characteristics in both forward and reverse modes. >

CW measurement of HBT thermal resistance

Abstract: Measurements of the temperature dependence of beta and V/sub BE/ were made on AlGaAs-GaAs HBTs and used to determine device thermal resistance. The measurements were CW and not switched or pulsed in order to have a simpler procedure. With base doping greater than 10/sup 19/ cm/sup -3/, HBTs have negligible base-width modulation (i.e., flat I/sub C/ versus V/sub CE/ characteristics) which makes CW thermal resistance measurement especially direct and simple. >

Improving the ESD failure threshold of silicided n-MOS output transistors by ensuring uniform current flow

Abstract: The authors describe and extend the present understanding of the high-current behavior of the simple single-poly finger n-MOS transistor. They present a model for the failure of the ladder structure n-MOS output device based on both the structure of the device and the behavior of its constituent n-MOS transistors. This model is able to show why the failure threshold of the output n-MOS device behaves as it does. Solutions that have been shown to improve the electrostatic discharge (ESD) failure threshold are described. The test environment and the process technology used for fabrication are described. >

Polysilicon emitters for bipolar transistors: a review and re-evaluation of theory and experiment

Abstract: A critical review is presented of the theories proposed in the literature to explain the current gain enhancement of polysilicon emitter bipolar transistors. From these theories a simplified analytical formulation is chosen which models the blocking properties of the interface, including tunneling through the interfacial oxide, reduced grain boundary mobility at the polysilicon/silicon interface, and the potential barrier created by segregated dopant, which can all give rise to an enhanced current gain. Also modeled are the mechanisms which limit the extent of any gain enhancement, such as recombination in the single-crystal emitter, in the bulk of the polysilicon, and at the polysilicon/silicon interface. This model is then applied in an original manner to a selection of experimental data in an effort to identify the dominant current gain mechanisms in polysilicon emitter transistors as a function of a given set of fabrication conditions. >

An integrated mass flow sensor with on-chip CMOS interface circuitry

Abstract: A multielement monolithic mass flow sensor which developed for possible use in automotive and industrial process control applications is reported. The chip illustrates the use of a common microstructure (a thin dielectric window/diaphragm) for the simultaneous measurement of flow velocity (rate), flow direction, gas type, and pressure. These transducers are merged with on-chip interface electronics to amplify and multiplex the transducer signals, control on-chip actuators, perform self-test, reduce the number of external leads required, and demonstrate process compatibility with a p-well CMOS process. The on-chip circuitry also implements a bandgap sensor for the measurement of ambient temperature. Thus, the chip simultaneously monitors all parameters needed for the computation of true mass flow, requires only ten external leads, and delivers high-level buffered output signals. >

Explaining the amplitude of RTS noise in submicrometer MOSFETs

Abstract: A simple-man's model for the random telegraph signal (RTS) noise amplitude in a submicrometer MOSFET is presented. It is shown that the channel resistance modulation for a specific trap can be expressed as a product of the normalized scattering cross section and of the fractional conductivity change. The model qualitatively describes the experimental temperature and drain current dependence of the RTS amplitude and allows evaluation of the influence of the trap location and nature on the wide scatter in values observed. >

Design for suppression of gate-induced drain leakage in LDD MOSFETs using a quasi-two-dimensional analytical model

Abstract: A systematic study of gate-induced drain leakage (GIDL) in single-diffusion drain (SD), lightly doped drain (LDD), and fully gate-overlapped LDD (GOLD) NMOSFETs is described. Design curves quantifying the GIDL dependence on gate oxide thickness, phosphorus dose, and spacer length are presented. In addition, a new, quasi-2-D analytical model is developed for the electric field in the gate-to-drain overlap region. This model successfully explains the observed GIDL dependence on the lateral doping profile of the drain. Also, a technique is proposed for extracting this lateral doping profile using the measured dependence of GIDL current on the applied substrate bias. Finally, the GIDL current is found to be much smaller in lightly doped LDD devices than in SD or fully overlapped LDD devices, due to smaller vertical and lateral electric fields. However, as the phosphorus dose approaches 10/sup 14//cm/sup 2/, the LDD and fully overlapped LDD devices exhibit similar GIDL current. >

Effects of microscopic fluctuations in dopant distributions on MOSFET threshold voltage

Abstract: The effects of fluctuations in dopant distribution on the MOSFET threshold voltage and their dependence on the scaling were investigated using device simulation. The simulation indicates that the microscopic fluctuations in dopant distribution not only induce threshold-voltage value. It was found that the threshold-voltage value deviation is mostly affected by fluctuating dopant distribution at the substrate surface, rather than throughout the depletion layer. Discussion incorporating microscopic fluctuations in surface electric potential, due to fluctuating dopant distribution, explained not only deviations but also the mean value lowering of the threshold voltage in the simulation. >

Effective mass and mobility of holes in strained Si/sub 1-x/Ge/sub x/ layers on

Abstract: The directional density-of-state effective masses of the valence bands of a strained Si/sub 1-x/Ge/sub x/ layer for the

Numerical analysis of a cylindrical thin-pillar transistor (CYNTHIA)

Abstract: The authors have analyzed the characteristics of a cylindrical thin-pillar transistor, (CYNTHIA), which is a vertical MOS transistor with a cylindrical gate electrode surrounding a submicrometer-diameter silicon pillar. The device characteristics are calculated by solving Poisson's equation in cylindrical coordinates. Results showed that CYNTHIA has three superior features: excellent subthreshold characteristics, enhanced electron mobility, and increased sheet electron concentration. These superior characteristics result in a feature size twice that of vertical SOI transistors, The authors' calculation is that CYNTHIA is quite an attractive device design for future ultra-high-density LSIs. >

Performance of thin-film transistors on polysilicon films grown by low-pressure chemical vapor deposition at various pressures

Abstract: Defect properties of undoped low-pressure chemical-vapor-deposited (LPCVD) polysilicon films have been investigated by capacitance techniques on a simple metal-oxide-semiconductor (MOS) capacitor structure. The results show that the effective density of bulk and interface trap states is almost independent of the deposition pressure. After reducing the polysilicon film thickness by etching, although the grain size decreases due to the columnar mode of growth at low pressures, the trap states density reduces significantly. This finding could be explained by the hypothesis that, during the growth of the material, impurities are segregated at the film surface by fast diffusion through the grain boundaries. The transport properties of 0.5- mu m-thick polysilicon films deposited at a pressure ranging from 100 to 0.5 mtorr were evaluated from measurements on thin-film transistors (TFTs). The results demonstrate that at high pressures the grain boundaries and at low pressures the polysilicon-SiO/sub 2/ interface roughness scattering are the main factors in determining the transistor performance. >

Modeling H/sup +/-sensitive FETs with SPICE

Abstract: A generalized physical model including two kinds of binding sites is presented on H/sup +/-sensitive ISFET devices. The model results in a set of equations which is introduced into a modified version of the electronic circuit simulation program SPICE. In this way, the effects induced on the device performances by varying several physico-chemical parameters are analyzed. The slope of V/sub out/ versus pH curves is predicted for SiO/sub 2/-, Al/sub 2/O/sub 3/-, and Si/sub 3/N/sub 4/-gate ISFETs. The model is then used to predict the behavior of a hypothetical, partially pH-insensitive (REFET) structure. Finally, the model is utilized to fit the slow response of the Al/sub 2/O/sub 3/-gate ISFET to a pH stop. >

Low-frequency noise properties of N-p-n AlGaAs/GaAs heterojunction bipolar transistors

Abstract: The low-frequency noise characteristics of N-p-n Al/sub x/Ga/sub 1-x/As/GaAs heterojunction bipolar transistors (HBTs) have been investigated as a function of bias current, device geometry, extrinsic-base-surface condition, Al mole fraction in the emitter, and temperature in order to identify the dominant noise mechanisms. These measurements show the existence of three distinct regions in the noise spectra: a 1/f noise line shape, a Lorentzian spectrum (noise 'bump'), and a white-noise region. The 1/f noise is attributed to fluctuations in the extrinsic-base surface recombination current. The noise bump is generated by an AlGaAs trap in the emitter-base junction. The DX center was identified as a possible candidate for this trap. It is shown that for 4- mu m*10- mu m emitter AlGaAs/GaAs HBTs, the use of a depleted, AlGaAs passivation ledge over the extrinsic-base surface typically reduced the 1/f base noise current by a factor of 10, and the reduction of the Al mole fraction from 0.3 to 0.2 decreased the magnitude of the noise bump by a factor of 3. >

Electrical and optical characteristics of vacuum-sealed polysilicon microlamps

Abstract: A silicon-filament vacuum-sealed incandescent light source has been fabricated using IC technology and subsurface micromachining. The incandescent source consists of a heavily doped p/sup +/ polysilicon filament coated with silicon nitride and enclosed in a vacuum-sealed ( approximately=80-mT) cavity in the silicon-chip surface. The filament is formed beneath the surface and later released using sacrificial etching to obtain a microstructure that is protected from the external environment. The filament is electrically heated to reach incandescence at a temperature near 1400 K. The power required to achieve this temperature (for a filament 510*5*1 mu m) is 5 mW. The emitted optical power is 250 mu W, and the peak in the spectrum distribution is near 2.5 mu m. The radiation approximately follows Lambert's cosine law. The subsurface micromachining technique used to produce the evacuated cavity has applications in other micromechanical devices. >

Influence of high substrate doping levels on the threshold voltage and the mobility of deep-submicrometer MOSFETs

Abstract: The high levels of substrate doping needed in deep-submicrometer MOS devices affect device properties strongly. The authors present a detailed experimental study of high-doping effects on the threshold voltage, which is shown to be affected by the quantum-mechanical splitting of the energy levels in the conduction band. A simple expression to account for these effects is proposed and the consequences for device scaling and design are discussed. Furthermore, the increasing levels of substrate doping and high normal electric fields affect the channel mobility through Coulomb and surface-roughness scattering. Several empirical models for the surface mobility are compared with the characteristics of experimental devices. >

Quantum-mechanical modeling of accumulation layers in MOS structure

Abstract: An original method is used for the quantum-mechanical modeling of n-type silicon accumulation layers. Unlike previous methods, which were only valid near 4.2 K, the approach is valid up to room temperature and beyond. The self-consistent results obtained are compared with those of the standard classical model for the accumulation layer, and the differences between them are found to be relevant for the modeling of important device applications. The dependences of the accumulation voltage drop and effective F-N (Fowler-Nordheim) barrier height on oxide electric field and substrate dopine are reported. Experimental F-N current-voltage characteristics of production-quality MOS capacitors are used to validate the quantum results and to show that the standard classical model is not adequate even if the barrier height is considered as a fitting parameter. Approximate analytical expressions giving the semiconductor voltage drop and the effective F-N barrier height as a function of oxide field and substrate doping are derived for and n-type silicon at 77 and 300 K. >

A high-performance 0.25- mu m CMOS technology. II. Technology

Abstract: For Pt. I, see ibid., vol.39, no.4, pp.959-966 (1992). The key technology elements and their integration into a high-performance, selectively scaled, 0.25- mu m CMOS technology are presented. Dual poly gates are fabricated using a process where the poly and source/drain (S/D) are doped simultaneously. The critical issues related to the dual poly gate are addressed. A reduced operating voltage of 2.5 V is used which allows the application of shallow junctions with abrupt profiles (no LDD) to minimize the device series resistance as well as gate to source/drain overlap capacitance. The poly gate and the S/D sheet resistances are lowered, using a thin salicide (TiSi/sub 2/) process. The TiSi/sub 2/ thickness is reduced to maintain low leakage and low contact resistance for the shallow S/D junctions. The gate level with 0.4- mu m physical length is defined using optical lithography with a contrast enhanced layer (CEL) resist system. >

Electric micromotor dynamics

Abstract: The dynamometry technique uses a strobe flash which is triggered from a phase excitation signal after a known time delay. This acts essentially as a video shutter allowing the position of the rotor as a function of the time delay to be recorded and measured. A dynamic model is developed that includes an electrostatic drive term, a velocity-dependent viscous drag term, and a Coulomb friction term that is dependent on the square of the drive voltage and the sign of the velocity. From the position-versus-time data, coefficients for this model are estimated using nonlinear least square error estimation. It is shown that both viscous drag and Coulomb friction terms are required if the model is to closely fit all the experimental data. The motor dynamics are shown to have a weak, if any, dependence on the rotor-bushing apparent area of contact. >

Simulation of ultra-small GaAs MESFET using quantum moment equations

Abstract: Ultra-small MESFETs have characteristic lengths comparable to quantum lengths: wavelength, mean free path, etc. In a first attempt to incorporate these quantum lengths, the authors develop a model based upon a set of quantum moment equations obtained from the Wigner function equation-of-motion. Interesting time-dependent current oscillation behavior has been observed when a step voltage is applied to the initial steady state. The oscillation frequency is peaked around 500 GHz, which is related to the plasma response of the carriers in the channel. Quantum effects, such as barrier repulsion and penetration, have been demonstrated in the simulation. These effects modify the electron density distribution and current density distribution both in the channel and near the source. Modifications of the frequency spectrum of the oscillation current due to the quantum effects are obvious. >

An ultraminiature CMOS pressure sensor for a multiplexed cardiovascular catheter

Abstract: A multiplexed ultraminiature pressure sensor designed for use in a cardiovascular catheter is described. The sensor operates from only two loads, which are shared by two sensors per catheter. The sensing chip is 350 mu m wide by 1.4 mm long by 100 mu m thick. CMOS readout circuitry at the sensing site converts applied pressure to a frequency variation in the supply current, which is detected at the end of the catheter by a microprocessor-controlled interface. The nominal pressure sensitivity is 2 kHz/fF about a zero-pressure output frequency of 2.7 MHz. This on-site circuitry contains two reference capacitors which allow external compensation for nonlinearity and temperature sensitivity and has an idle-state power dissipation of less than 50 mu W. With the transducer sealed at ambient pressure, the device can resolve pressure variations of about 3 mmHg, while vacuum-sealed devices do considerably better and should permit >

Single-wafer integrated semiconductor device processing

Abstract: The authors present an overview of various single-wafer fabrication techniques for integrated processing of microelectronic devices. Numerous processing modules, sensors, and associated fabrication processes have been developed for advanced semiconductor device manufacturing. The combination of single-wafer processing, cluster tools, sensors, and advanced factory control/computer-integrated manufacturing techniques provides a capability for flexible fast-cycle-time device manufacturing. Specific developments and results are described in the areas of dry/vapor-phase surface cleaning, epitaxy, plasma processing, rapid thermal processing, and in situ sensors. An integrated sub-half micrometer CMOS technology based on these single-wafer fabrication methods including rapid thermal processing is also described. >

A high-performance 0.25- mu m CMOS technology. I. Design and characterization

Abstract: A high-performance 0.25- mu m-channel CMOS technology is designed and characterized. The technology utilizes n/sup +/ polysilicon gates on nFETs and p/sup +/ polysilicon gates on pFETs so that both FETs are surface channel devices. The gate oxide thickness is 7 nm. Abrupt As and B source/drain junctions with reduced power supply voltage are used to achieve high-speed operation. The technology yields a loaded ring oscillator (NAND, FI=FO=3, C/sub w/=0.2 pF) delay per stage of 280 ps at W/sub eff//L/sub eff/=15 mu m/0.25 mu m, which is a 1.7* improvement over 0.5- mu m CMOS technology. At a channel length of 0.18 mu m, a CMOS stage delay of 38 ps for unloaded inverter and 185 ps for loaded NAND ring oscillators were measured. Key design issues of the CMOS devices are discussed. >