Showing papers in "IEEE Transactions on Electron Devices in 1996"

Detection, mixing, and frequency multiplication of terahertz radiation by two-dimensional electronic fluid

Abstract: We show that a short channel High Electron Mobility Transistor (HEMT) has a resonance response to electromagnetic radiation at the plasma oscillation frequencies of the two dimensional electrons in the device. This response can be used for new types of detectors, mixers, and multipliers. These devices should operate at much higher frequencies than conventional, transit-time limited devices, since the plasma waves propagate much faster than electrons. The responsivities of such devices may greatly exceed the responsivities of Schottky diodes currently used as detectors and mixers in the terahertz range. A long channel HEMT has a nonresonant response to electromagnetic radiation and can be used as a broadband detector for frequencies up to several tens of terahertz.

Fast and long retention-time nano-crystal memory

Abstract: A threshold-shifting, single transistor memory structure with fast read and write times and long retention time is described. The structure consists of a silicon field-effect transistor with nano-crystals of germanium or silicon placed in the gate oxide in close proximity of the inversion surface. Electron charge is stored in these isolated 2-5 nm size nano-crystals which are separated from each other by greater than 5 nm of SiO/sub 2/ and from the inversion layer of the substrate surface by less than 5 nm of SiO/sub 2/. Direct tunneling of charge from the inversion layer and its storage in the nano-crystal causes a shift in the threshold voltage which is detected via current sensing. The nano-crystals are formed using implantation and annealing or using direct deposition of the distributed floating gate region. Threshold shift of 0.3 V is obtained in Ge-implanted devices with 2 nm of SiO/sub 2/ injection layer by a 4 V write pulse of 300 ns duration. The nano-crystal memories achieve improved programming characteristics as a nonvolatile memory as well as simplicity of the single poly-Si-gate process. The V/sub T/ window is scarcely degraded after greater than 10/sup 9/ write/erase cycles or greater than 10/sup 5/ s retention time. Nano-crystal memories are promising for nonvolatile memory applications.

Trends in power semiconductor devices

Abstract: This paper reviews recent trends in power semiconductor device technology that are leading to improvements in power losses for power electronic systems. In the case of low voltage ( 100 V) power rectifiers, the silicon P-i-N rectifier continues to dominate but significant improvements are expected by the introduction of the silicon MPS rectifier followed by the GaAs and SiC based Schottky rectifiers. Equally important developments are occurring in power switch technology. The silicon bipolar power transistor has been displaced by silicon power MOSFETs in low voltage ( 100 V) systems. The process technology for these MOS-gated devices has shifted from V-MOS in the early 1970s to DMOS in the 1980s, with more recent introduction of the UMOS technology in the 1990s. For the very high power systems, the thyristor and GTO continue to dominate, but significant effort is underway to develop MOS-gated thyristors (MCTs, ESTs, DG-BRTs) to replace them before the turn of the century. Beyond that time frame, it is projected that silicon carbide based switches will begin to displace these silicon devices.

Silicon carbide high-power devices

Abstract: In recent years, silicon carbide has received increased attention because of its potential for high-power devices. The unique material properties of SiC, high electric breakdown field, high saturated electron drift velocity, and high thermal conductivity are what give this material its tremendous potential in the power device arena. 4H-SiC Schottky barrier diodes (1400 V) with forward current densities over 700 A/cm/sup 2/ at 2 V have been demonstrated. Packaged SITs have produced 57 W of output power at 500 MHz, SiC UMOSFETs (1200 V) are projected to have 15 times the current density of Si IGBTs (1200 V). Submicron gate length 4H-SiC MESFETs have achieved f/sub max/=32 GHz, f/sub T/=14.0 GHz, and power density=2.8 W/mm @ 1.8 GHz. The performances of a wide variety of SiC devices are compared to that of similar Si and GaAs devices and to theoretically expected results.

Plasma wave electronics: novel terahertz devices using two dimensional electron fluid

Abstract: We discuss how the propagation of plasma waves in a High Electron Mobility Transistor (HEMT) can be used to implement a new generation of terahertz devices, including sources, resonant detectors, broad band detectors, and frequency multipliers. Our estimates show that these devices should outperform conventional terahertz devices, which use deep submicron Schottky diodes.

Nonlithographic nano-wire arrays: fabrication, physics, and device applications

Abstract: A novel system of nanostructures is described consisting of nonlithographically produced arrays of nano-wires directly electrodeposited into porous anodic aluminum oxide templates. Using this method regular and uniform arrays of metal or semiconductor nano-wires or nano-dots can be created with diameters ranging from /spl sim/5 nm to several hundred nanometers and with areal pore densities in the /spl sim/10/sup 9/-10/sup 11/ cm/sup -2/ range. We report on the present state of their fabrication, properties, and prospective device applications. Results of X-ray diffraction, Raman and magnetic measurements on metal (Ni, Fe) and semiconductor (CdS, CdSe, CdS/sub x/Se/sub 1-x/, Cd/sub x/Zn/sub 1-x/S and GaAs) wires are presented. The I-V characteristics of two terminal devices made from the nano-arrays are found to exhibit room temperature periodic conductance oscillations and Coulomb-blockade like current staircases. These observations are likely associated with the ultra-small tunnel junctions that are formed naturally in the arrays. Single-electron tunneling (SET) In the presence of interwire coupling in these arrays is shown to lead to the spontaneous electrostatic polarization of the wires. Possible device applications such as magnetic memory or sensors, electroluminescent flat-panel displays, and nanoelectronic and single-electronic devices are also discussed.

A single-transistor silicon synapse

Abstract: We have developed a new floating-gate silicon MOS transistor for analog learning applications. The memory storage is nonvolatile; hot-electron injection and electron tunneling permit bidirectional memory updates. Because these updates depend on both the stored memory value and the transistor terminal voltages, the synapse can implement a learning function. We have derived a memory-update rule from the physics of the tunneling and injection processes, and have investigated synapse learning in a prototype array. Unlike conventional EEPROM devices, the synapse allows simultaneous memory reading and writing. Synapse transistor arrays can therefore compute both the array output, and local memory updates, in parallel. The synapse is small, and typically is operated at subthreshold current levels; it will permit the development of dense, low-power silicon learning systems.

1.5 nm direct-tunneling gate oxide Si MOSFET's

Abstract: In this paper, normal operation of a MOSFET with an ultra-thin direct-tunneling gate oxide is reported for the first time. These high current drive n-MOSFET's were fabricated with a 1.5 nm direct-tunneling gate oxide. They operate well at gate lengths of around 0.1 /spl mu/m, because the gate leakage current falls in proportional to the gate length, while the drain current increases in inverse proportion. A current drive of more than 1.0 mA//spl mu/m and a transconductance of more than 1,000 mS/mm were obtained at a gate length of 0.09 /spl mu/m at room temperature. These are the highest values ever obtained with Si MOSFET's at room temperature. Further, hot-carrier reliability is shown to improve as the thickness of the gate oxide is reduced, even in the 1.5 nm case. This work clarifies that excellent performance-a transconductance of over 1,000 mS/mm at room temperature-can be obtained with Si MOSFET's if a high-capacitance gate insulator is used.

Soft breakdown of ultra-thin gate oxide layers

Abstract: The dielectric breakdown of ultra-thin 3 nm and 4 nm SiO/sub 2/ layers used as a gate dielectric in poly-Si gate capacitors is investigated. The ultra-thin gate oxide reliability was determined using tunnel current injection stressing measurements. A soft breakdown mechanism is demonstrated for these ultra-thin gate oxide layers. The soft breakdown phenomenon corresponds with an anomalous increase of the stress induced leakage current and the occurrence of fluctuations in the current. The soft breakdown phenomenon is explained by the decrease of the applied power during the stressing for thinner oxides so that thermal effects are avoided during the breakdown of the ultra-thin oxide capacitor. It is proposed that multiple tunnelling via generated electron traps in the ultra-thin gate oxide layer is the physical mechanism of the electron transport after soft breakdown. The statistical distributions of the charge to dielectric breakdown and to soft breakdown for a constant current stress of the ultra-thin oxides are compared. It is shown that for accurate ultra-thin gate oxide reliability measurements it is necessary to take the soft breakdown phenomenon into account.

Technology and device scaling considerations for CMOS imagers

Abstract: This paper presents an analysis of the impact of device and technology scaling on active pixel CMOS image sensors. Using the SLA roadmap as a guideline, we calculate the device characteristics that are germane to the image sensing performance of CMOS imagers, and highlight the areas where the CIMOS imager technology may need to depart from "standard" CMOS technologies. The impact of scaling on those analog circuit performance that pertain to image sensing performances are analyzed. Our analyses suggest that while "standard" CMOS technologies may provide adequate imaging performance at the 2-1 /spl mu/m generation without any process change, some modifications to the fabrication process and innovations of the pixel architecture are needed to enable CMOS to perform good quality imaging at the 0.5 /spl mu/m technology generation and beyond. Finally, the challenges to the CMOS imager research community are outlined.

Wide bandgap semiconductor materials and devices

Abstract: Given a matrix of all semiconductor materials and their properties, the highest and the lowest of these property values will almost always be associated with wide bandgap materials. The many possible combinations of these "poles and zeros" lead not only to superlative electron device performance, but to new device concepts as well. An overview of wide bandgap semiconductor properties is presented followed by several concepts for both new and enhanced devices. Finally, impediments to immediate exploitation and a time-oriented appraisal of the various materials and devices is presented.

A comparative study of advanced MOSFET concepts

Abstract: Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) has been the major device for integrated circuits over the past two decades. With technology advancement, there have been numerous MOSFET structures for channel length of 0.1 /spl mu/m and below reported in industrial research. A side-by-side comparison of these advanced device structures can provide useful understanding in device physics and the design tradeoffs among MOSFET's parameters. In this work we employ experimental data, device simulation, and analytical modeling for device comparison. The devices were developed at several different research laboratories. Guided by experimental data and simulations, analytical models for topics such as threshold voltage, short-channel effect, and saturation current for these different MOSFET structures are developed. These analytical models are then used for optimizing each device structure and comparing the devices under the same set of constraints for a fair comparison. The key design parameters are highlighted and the strength and weakness of each device structure in various performance categories are discussed.

Self-heating effects in SOI MOSFETs and their measurement by small signal conductance techniques

Abstract: Self-heating is an important issue for SOI CMOS, and hence, so is its characterization and modeling. This paper sets out how the critical parameters for modeling, i.e., thermal resistance and thermal time-constants, may be obtained using purely electrical measurements on standard MOS devices. A summary of the circuit level issues is presented, and the physical effects contributing to thermally related MOSFET behavior are discussed. A new thermal extraction technique is presented, based on an analytically derived expression for the electro-thermal drain conductance in saturation. Uniquely, standard MOSFET structures can be used, eliminating errors due to additional heat flow through special layouts. The conductance technique is tested experimentally and results are shown to be in excellent agreement with thermal resistance values obtained from noise thermometry and gate resistance measurements using identical devices. It is demonstrated that the conductance technique can be used confidently over a wide range of bias conditions, with both fully and partially depleted devices.

Size dependence of the characteristics of Si single-electron transistors on SIMOX substrates

Abstract: A Si single-electron transistor (SET) was fabricated by converting a one-dimensional (1-D) Si wire on a SIMOX substrate into a small Si island with a tunneling barrier at each end by means of pattern-dependent oxidation. Since the size of the Si island became as small as around 10 nm owing to this novel technique, the total capacitance of the SET was reduced to a value of the order of 1 aF, which guaranteed the conductance oscillation of the SET even at room temperature. Furthermore, a linear relation between the designed wire length and the gate capacitance of SET's was obtained, which clearly indicates that the single island was actually formed in the middle of the one dimensional Si wire. These results were achieved owing to the highly reproducible fabrication process based on pattern dependent oxidation of SIMOX-Si layers.

High-mobility strained-Si PMOSFET's

Abstract: Operation and fabrication of a new high channel mobility strained-Si PMOSFET are presented. The growth of high-quality strained Si layer on completely relaxed, step-graded, SiGe buffer layer is demonstrated by gas source MBE. The strained-Si layer is characterized by double crystal X-ray diffraction, photoluminescence, and transmission electron microscopy. The operation of a PMOSFET is shown by device simulation and experiment. The high-mobility strained-Si PMOSFET is fabricated on strained-Si, which is grown epitaxially on a completely relaxed step-graded Si/sub 0.82/Ge/sub 0.18/ buffer layer on Si(100) substrate. At high vertical fields (high |V/sub g/|), the channel mobility of the strained-Si device is found to be 40% and 200% higher at 300 K and 77 K, respectively, compared to those of the bulk Si device. In the case of the strained-Si device, degradation of channel mobility due to Si/SiO/sub 2/ interface scattering is found to be more pronounced compared to that of the bulk Si device. Carrier confinement at the type-II strained-Si/SiGe-buffer interface is clearly demonstrated from device transconductance and C-V measurements at 300 K and 77 K.

Infrared focal plane array incorporating silicon IC process compatible bolometer

Abstract: A 128/spl times/128 element bolometer infrared image sensor using thin film titanium is proposed. The device is a monolithically integrated structure with a titanium bolometer detector located over a CMOS circuit that reads out the bolometer's signals. By employing a metallic material like titanium and refining the CMOS readout circuit, it is possible to minimize 1/f noise. It is demonstrated that the use of low 1/f noise material will help increase bias current and improve the S/N ratio. Since the fabrication process is silicon-process compatible, costs can be kept low.

Threshold voltage, field effect mobility, and gate-to-channel capacitance in polysilicon TFTs

Abstract: Based on experimental and theoretical studies of n- and p-channel polysilicon thin film transistors with gate W/L ratios from 0.3 to 3.3, we have demonstrated that the threshold voltage extracted from gate to channel capacitance data results in field effect mobility parameters which are independent of device geometry. The parameters extracted using this V/sub t/ allow us to reproduce the I-V characteristics of the n- and p channel TFTs over wide ranges of bias voltages and gate sizes. The C/sub gc/-V/sub GS/ characteristics of polysilicon TFTs are strongly affected by the trapping and de-trapping of carriers. As a result, the measured C/sub gc/ characteristic is a function of measurement frequency and gate length. However, we demonstrate that to the first order, the frequency dispersion of the C/sub gc/ curve can be related to the effective carrier transit time determined using the V/sub GS/ dependent field effect mobility.

Thermal noise modeling for short-channel MOSFETs

Abstract: An analytical formulation of the thermal noise in short-channel MOSFETs, working in the saturation region, is presented. For the noise calculation, we took into account effects like the field dependent noise temperature and mobility, the device geometry and the channel length modulation, the back gate effect and the velocity saturation. The derived data from the model are in good agreement with reported thermal noise measurements, regarding the noise bias dependence, for transistors with channel lengths shorter than 1 /spl mu/m. Since the present thermal noise models of MOS transistors are valid for channel lengths well above 1 /spl mu/m, the proposed model can be easily incorporated in circuit simulators like SPICE, providing an extension to the analytical thermal noise modeling suitable for submicron MOSFETs.

High-performance InP-based enhancement-mode HEMTs using non-alloyed ohmic contacts and Pt-based buried-gate technologies

Abstract: High performance InP-based InAlAs/InGaAs enhancement-mode HEMT's are demonstrated using two improved approaches to device structure design and fabrication, i.e., nonalloyed ohmic contacts and Pt-based buried-gate technologies, to reduce the source resistance (R/sub S/). With specially designed cap layer structures, nonalloyed ohmic contacts to the device channel were obtained providing contact resistance as low as 0.067 /spl Omega//spl middot/mm. Furthermore, in device fabrication, a Pt-based buried-gate approach is used in which depletion-mode HEMTs are first intentionally fabricated, and then, the Pt-based gate metal is annealed at 250/spl deg/C, causing the Pt-InAlAs reaction to take place under the gate electrode so that Pt sinks into InAlAs and depletes the channel. As a result, the depletion-mode HEMTs are changed to enhancement-mode, while the channel region between the source and gate electrodes remain undepleted, and therefore, the small R/sub S/ of 0.2 /spl Omega//spl middot/mm can be maintained. Excellent maximum transconductance of 1170 mS/mm was obtained for a 0.5-/spl mu/m-gate device. A maximum current-gain cutoff frequency f/sub T/ of 41.2 GHz and maximum unilateral power-gain cutoff frequency f/sub max/ of 61 GHz were demonstrated for a 0.6-/spl mu/m-gate enhancement-mode HEMT.

Integrated RF and microwave components in BiCMOS technology

Abstract: This paper presents and discusses an approach to exploit conventional BiCMOS technology for monolithic integration of RF & microwave systems. Several components, which are important elements of RF and microwave circuit design and which are not available in current BiCMOS, are described and characterized. The results for integrated spiral inductors in particular show that obvious limitations in comparison to compound semiconductor technology or hybrid configurations can be overcome to a large extent by utilizing the structural design options given with VLSI silicon integration technology.

Design of Si/SiGe heterojunction complementary metal-oxide-semiconductor transistors

Abstract: An optimized Si/SiGe heterostructure for complementary metal-oxide semiconductor (CMOS) transistor operation is presented. Unlike previous proposals, the design is planar and avoids inversion of the Si layer at the oxide interface. The design consists of a relaxed Si/sub 0.7/Ge/sub 0.3/ buffer, a strained Si quantum well (the electron channel), and a strained S/sub 1-x/Ge/sub x/ (0.7>x>0.5) quantum well (the hole channel). The channel charge distribution is predicted using a 1-D analytical model and quantum mechanical solutions. Transport is modeled using 2-D drift-diffusion and hydrodynamic numerical simulations. An almost symmetric performance of p- and n-transistors with good short-channel behavior is predicted. Simulated ring oscillators show a 4- to 6-fold reduction in power-delay product compared to bulk Si CMOS at the 0.2-/spl mu/m channel length generation.

Leakage current mechanism in sub-micron polysilicon thin-film transistors

Abstract: We have studied leakage current in sub-micron p-channel polysilicon thin-film-transistor. Our study revealed that thermionic emission is the dominant mechanism at low drain bias (-0.1 V) while thermionic field emission dominate at moderately high drain bias. At high drain bias (>-5.0 V), tunneling was observed to be the dominant leakage mechanism.

Effect of surface inhomogeneities on the electrical characteristics of SiC Schottky contacts

Abstract: This paper reports analysis of the role of defects on the electrical characteristics of high-voltage 6H-SiC Schottky rectifiers. The measured reverse leakage current of high-voltage Ti and Pt rectifiers was found to be much higher than that predicted by thermionic emission theory and using a barrier height extracted from the C-V measurements. In this paper, a model based upon the presence of defects at the 6H-SiC/metal interface is used to explains this behavior. It is proposed that these defects result in lowering of the barrier height in the localized regions and thus, significantly affect the reverse I-V characteristics of the Schottky contacts. The presence of electrically active defects in the Schottky barrier area has been verified by EBIC studies.

Extraction of experimental mobility data for MOS devices

Abstract: MOS surface mobility is a fundamental material and device property which has been extensively studied both theoretically and experimentally. This work reports on a new technique for extracting surface mobility data from experimentally measured I-V data on large area MOS devices. The approach employs a least squares curve fitting technique for combining theoretical models of inversion layer charge and surface mobility to obtain an accurate value of surface threshold voltage. An accurate model of inversion layer charge is then used to calculate the experimental mobility. The extraction technique gives high field values of mobility which compare very closely with previously reported extraction approaches but gives more accurate low field values due to an improved model for inversion layer charge. A very important feature of the technique is the ability to obtain data on individual components of surface scattering such as interface scattering density and surface roughness coefficient. These individual parameters are very valuable when comparing the effects of changes in surface preparation techniques on MOS surface mobility.

The use of base ballasting to prevent the collapse of current gain in AlGaAs/GaAs heterojunction bipolar transistors

Abstract: We propose the use of base-ballasting resistance to guarantee absolute thermal stability in AlGaAs/GaAs heterojunction bipolar transistors (HBTs). Base-ballasted HBTs are fabricated and the measured I-V, regression and S-factor characteristics are discussed. We present a numerical model which elucidates the reasons why the base-ballasting scheme is helpful to HBTs but is damaging to silicon bipolar transistors. We compare measured small-signal and large-signal performances of unballasted, emitter-ballasted, and base-ballasted HBTs.

Thermal conductivity measurements of thin silicon dioxide films in integrated circuits

Abstract: The thermal conductivity of thin silicon dioxide (SiO/sub 2/) films is measured using specialized test structures. The test structures consist of parallel plate-electrodes that sandwich the dielectric whose thermal conductivity is determined. The accuracy of the measurement technique is verified based on simulations. Films with thicknesses in the range of 0.57 /spl mu/m to 2.28 /spl mu/m are investigated. At room temperature the thin films exhibit a thermal conductivity of /spl sim/1.1 W/Km which is approximately 20% below that of bulk fused SiO/sub 2/. As opposed to prior studies, the thermal conductivity of the thin films is observed to increase with rising temperature. Temperature dependence of thermal conductivity is found to be very similar to that of bulk fused SiO/sub 2/. The impart of thermal resistances at boundaries between silicon dioxide and metallization is shown to be insignificant for the films investigated. In addition, no dependence of thermal conductivity on film thickness is observed. Vias are found to be very effective in reducing thermal resistance between adjacent metallization layers.

A computationally efficient model for inversion layer quantization effects in deep submicron N-channel MOSFETs

Abstract: Successful scaling of MOS device feature size requires thinner gate oxides and higher levels of channel doping in order to simultaneously satisfy the need for high drive currents and minimal short-channel effects. However, in deep submicron (/spl les/0.25 /spl mu/m gate length) technology, the combination of the extremely thin gate oxides (t/sub ox//spl les/10 nm) and high channel doping levels (/spl ges/10/sup 17/ cm/sup -3/) results in transverse electric fields at the Si/SiO/sub 2/ interface that are sufficiently large, even near threshold, to quantize electron motion perpendicular to the interface. This phenomenon is well known and begins to have an observable impact on room temperature deep submicron MOS device performance when compared to the traditional classical predictions which do not take into account these quantum mechanical effects. Thus, for accurate and efficient device simulations, these effects must be properly accounted for in today's widely used moment-based device simulators. This paper describes the development and implementation into PISCES of a new computationally efficient three-subband model that predicts both the quantum mechanical effects in electron inversion layers and the electron distribution within the inversion layer. In addition, a model recently proposed by van Dort et al. (1994) has been implemented in PISCES. By comparison with self-consistent calculations and previously published experimental data, these two different approaches for modeling the electron inversion layer quantization are shown to be adequate in order to both accurately and efficiently simulate many of the effects of quantization on the electrical characteristics of N-channel MOS transistors.

Quantum efficiency analysis of thin-layer silicon solar cells with back surface fields and optical confinement

Abstract: Thin-layer silicon solar cells utilize surface textures to increase light absorption and back surface fields to prevent recombination at the silicon-substrate interface. We present an analytical model for the internal quantum efficiency that accounts for light trapping and also considers carrier generation and recombination in back surface fields or substrates. We introduce a graphical representation of experimental data, the so-called Parameter-Confidence-Plot, which allows one to draw maximum information on diffusion lengths and surface recombination velocities from quantum efficiency measurements. The analysis is exemplified for state of the art thin-layer silicon solar cells with and without back surface fields.

A VLSI-compatible high-speed silicon photodetector for optical data link applications

Abstract: A novel silicon photodetector suitable for high-speed, low-voltage operation at 780- to 850-nm wavelengths is reported. It consists of an interdigitated p-i-n detector fabricated on a silicon-on-insulator (SOI) substrate by using a standard bipolar process. Biased at 3.5 V, this device attains a -3-dB bandwidth in excess of 1 GHz at /spl lambda/=840 nm. The dc responsivity measured at /spl lambda/=840 nm on nonoptimized structures ranges from 0.05 to 0.09 A/W, depending on the finger shadowing factor. A new approach for improving the responsivity is proposed and quantitatively analyzed. The fabricated devices exhibit extremely low dark currents, small capacitance, large dynamic range, and no evidence of low-frequency gain. The overall performance and process compatibility of these photodetectors make them viable candidates for the fabrication of silicon monolithic receivers for fiber-optic data links.

Collective computational activity in self-assembled arrays of quantum dots: a novel neuromorphic architecture for nanoelectronics

Abstract: We describe a new class of nanoelectronic circuits which exploits the charging behavior in resistively/capacitively linked arrays of nanometer-sized metallic islands (quantum dots), self-assembled on a resonant tunneling diode, to perform neuromorphic computation. These circuits produce associative memory effects and realize the additive short-term memory (STM) or content addressable memory (CAM) models of neural networks without requiring either large-area/high-power operational amplifiers, or massive interconnectivity between devices. Both these requirements had seriously hindered the application of neural networks in the past. Additionally, the circuits can solve NP-complete optimization problems (such as the traveling salesman problem) using single electron charge dynamics, exhibit rudimentary image-processing capability, and operate at room temperature unlike most quantum devices. Two-dimensional (2D) processors, with a 100/spl times/100 pixel capacity, can be fabricated in an area of 10/sup -8/ cm/sup 2/ leading to unprecedented functional density. Possible routes to synthesizing these circuits, employing self-assembly, are also discussed.