Showing papers in "IEEE Transactions on Electron Devices in 1997"
TL;DR: In this article, the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed.
Abstract: CMOS active pixel sensors (APS) have performance competitive with charge-coupled device (CCD) technology, and offer advantages in on-chip functionality, system power reduction, cost, and miniaturization. This paper discusses the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed.
1,182 citations
TL;DR: In this article, the threshold voltage of the device is a function of its gate voltage, i.e., as the gate voltage increases, the voltage drops resulting in a much higher current drive than standard MOSFET for low power supply voltages.
Abstract: In this paper, we propose a novel operation of a MOSFET that is suitable for ultra-low voltage (0.6 V and below) VLSI circuits. Experimental demonstration was carried out in a Silicon-On-Insulator (SOI) technology. In this device, the threshold voltage of the device is a function of its gate voltage, i.e., as the gate voltage increases the threshold voltage (V/sub t/) drops resulting in a much higher current drive than standard MOSFET for low-power supply voltages. On the other hand, V/sub t/ is high at V/sub gs/=0, therefore the leakage current is low. We provide extensive experimental results and two-dimensional (2-D) device and mixed-mode simulations to analyze this device and compare its performance with a standard MOSFET. These results verify excellent inverter dc characteristics down to V/sub dd/=0.2 V, and good ring oscillator performance down to 0.3 V for Dynamic Threshold-Voltage MOSFET (DTMOS).
533 citations
TL;DR: In this paper, the authors show that the large sub-threshold slope typically observed is not an intrinsic property of the organic semiconducting material and that devices with sub-reshold slope similar to amorphous silicon devices are possible.
Abstract: Organic thin-film transistors using the fused-ring polycyclic aromatic hydrocarbon pentacene as the active electronic material have shown mobility as large as 0.7 cm/sup 2//V-s and on/off current ratio larger than 10/sup 8/; both values are comparable to hydrogenated amorphous silicon devices. On the other hand, these and most other organic TFT's have an undesirably large subthreshold slope. We show here that the large subthreshold slope typically observed is not an intrinsic property of the organic semiconducting material and that devices with subthreshold slope similar to amorphous silicon devices are possible.
520 citations
TL;DR: In this paper, the authors show that surface recombination plays an important role in today's high purity Si and will become yet more important as bulk impurity densities in Si are reduced further.
Abstract: Carrier lifetimes in semiconductors are being rediscovered by the Si IC community, because the lifetime is a very effective parameter to characterize the purity of a material or device. It has become a process and equipment characterization parameter. The various recombination mechanisms are discussed and the concept of recombination and generation lifetime is presented. We show that surface recombination/generation plays an important role in today's high purity Si and will become yet more important as bulk impurity densities in Si are reduced further. Furthermore, the dependence of lifetime on impurity energy level and minority carrier injection level is discussed. Concepts are stressed in the paper, with the necessary equations to clarify these concepts. Wherever possible, the concepts are augmented with experimental data, with particular emphasis on the case of iron in silicon, because Fe is one of the most important impurities in Si today. We have used Si in the examples because lifetime measurements are most commonly made in Si.
404 citations
TL;DR: The quantum capacitance effect in the accumulation layer of polycrystalline anatase TiO/sub 2/ has been investigated in this paper, where the authors showed that N-channel transistors made with these films showed near ideal behavior, but mobilities were significantly lower than those of thermal oxide MOSFETs.
Abstract: Layers of polycrystalline anatase TiO/sub 2/ have been deposited through the thermal decomposition of titanium tetrakisisopropoxide (TTIP). 500 /spl Aring/ films deposited and annealed in oxygen at 750/spl deg/C had average roughnesses (R/sub a/) of about 30 /spl Aring/. Capacitors made from 190 /spl Aring/ layers of TiO/sub 2/ displayed a voltage dependent accumulation capacitance. This was postulated to be caused by finite width effects in the accumulation layer which we have dubbed the quantum capacitance effect. N-channel transistors made with these films showed near ideal behavior, but mobilities were significantly lower than those of thermal oxide MOSFETs. This mobility reduction was believed to be caused by interface states, which fell below 10/sup 11/ cm/sup -2/ eV/sup -1/ at midgap, but rose sharply on either side, unlike the "U" shaped behavior in thermal oxide MOSFET's.
403 citations
TL;DR: A CCD-based range-finding sensor which uses the time-of-flight method for range measurement and exploits two charge packets for light integration and detects the delay of the received light pulse relative to the transmitted light pulse.
Abstract: Integration-time-based, time-domain computation provides an area-efficient way to process image information by directly handling photo-created charge during photo-sensing. We have fabricated and tested a CCD-based range-finding sensor which uses the time-of-flight method for range measurement. The sensor exploits two charge packets for light integration and detects the delay of the received light pulse relative to the transmitted light pulse. It has detected a 10 cm distance difference at the range of 150 cm in the dark background.
314 citations
TL;DR: In this paper, the authors analyzed both by simulations and measurements the substrate crosstalk performances of various Silicon-On-Insulator (SOI) technologies, and compared them to those of normal bulk CMOS process.
Abstract: This work analyzes both by simulations and measurements the substrate crosstalk performances of various Silicon-On-Insulator (SOI) technologies, and compares them to those of normal bulk CMOS process. The influence of various parameters, such as substrate resistivity, buried oxide thickness and distance between devices, is investigated. The use of capacitive guard rings is proposed, and their effectiveness is demonstrated. A simple RC model has been developed to allow a deep understanding of these phenomena as well as to simplify future studies of more complex systems. The superiority of high-resistivity SIMOX substrates over standard SOI and bulk is finally demonstrated.
310 citations
TL;DR: In this article, a novel, tunable OLED consisting of vertically stacked, transparent light-emitting devices which can serve as a color-tunable element in high-resolution full-color display is described.
Abstract: We review recent results in the field of organic light-emitting devices (OLED's), with particular attention to the application of organic light-emitting devices to ultra-lightweight, full color, flat-panel displays. We show that OLED brightness, efficiency, operating voltage, and lifetime is sufficient to compete with other flat-panel display technologies such as backlit liquid crystal displays. We describe a novel, tunable OLED consisting of vertically stacked, transparent light-emitting devices which can serve as a color-tunable element in high-resolution full-color display., In addition, the unique physical properties of organic thin films allow for flexible, conformable, or foldable displays which are unobtainable with conventional, inorganic semiconductor technologies.
305 citations
TL;DR: In this article, a CMOS active pixel sensor (APS) that achieves wide intrascene dynamic range using dual sampling is reported, which achieves an intrascenesensitivity of 109 dB without nonlinear companding.
Abstract: A CMOS active pixel sensor (APS) that achieves wide intrascene dynamic range using dual sampling is reported. A 64/spl times/64 element prototype sensor with dual output architecture was fabricated using a 1.2 /spl mu/m n-well CMOS process with 20.4 /spl mu/m pitch photodiode-type active pixels. The sensor achieves an intrascene dynamic range of 109 dB without nonlinear companding.
263 citations
TL;DR: In this article, an organic electroluminescenters with multilayer structure were fabricated using alkaline metal compounds as the electron injection materials, which reduced the driving voltage and increased the quantum EL efficiency.
Abstract: Organic electroluminescent (EL) devices with multilayer structure were fabricated using alkaline metal compounds as the electron injection materials. We found that the EL cells using the alkaline metal compounds reduce the driving voltage and increase the quantum EL efficiency. In addition, these cells are made with good reproducibility compared with the cells using aluminum and lithium alloy cathode.
219 citations
TL;DR: In this paper, a detailed study of electroluminescent devices made from single-layer doped polymer blend thin films having bipolar carrier transport abilities is presented. And the authors show that in an optimized device, a relatively high external quantum efficiency (>1%, backside emission only) and a low operating voltage (<10 V for over 100 cd/m/sup 2/) can be easily achieved by this class of devices.
Abstract: Detailed studies of electroluminescent devices made from single-layer doped polymer blend thin films having bipolar carrier transport abilities are presented. The active organic layer consists of the hole-transport polymer poly(N-vinylcarbazole) (PVK) containing dispersed electron-transport molecules, as well as different fluorescent small molecules or polymers as emitting centers to vary the emission color. Both the photoluminescence and electroluminescence (EL) properties are extensively studied. In photoluminescence, very efficient transfer of energy can occur from the host to very dilute (/spl sim/1 wt.%) amounts of emitting materials. When covered with a metal layer, the intensity of photoluminescence from blend thin films was found to be dependent on the type of metal coverage. The optical and electrical properties of materials and devices were systematically studied to understand the operating mechanisms and to optimize the devices. In EL, excitons appear to be formed at doped emitting centers, rather than in the host. We show that in an optimized device, a relatively high external quantum efficiency (>1%, backside emission only) and a low operating voltage (<10 V for over 100 cd/m/sup 2/) can be easily achieved by this class of devices. It was also found air-stable Ag is as good as reactive Mg-Ag alloy for the cathode contact in devices using PVK containing dispersed electron-transport oxadiazole molecules.
TL;DR: In this paper, the electrical properties of model interfaces of organic electroluminescent (EL) devices and porphyrin/metal interfaces were investigated by UV photoemission spectroscopy (UPS).
Abstract: Electronic structures of model interfaces of organic electroluminescent (EL) devices and porphyrin/metal interfaces were investigated by UV photoemission spectroscopy (UPS). At all the measured interfaces, shift of the vacuum level was observed, showing the formation of an interfacial electric dipole layer. For Alq/sub 3/ (tris(8-hydroxyquinolino) aluminum), TPD (N,N'-diphenyl-N,N'-(3-methylphenyl)-1,1-biphenyl-4,4'-diamine), and DP-NTCI (N,N'-diphenyl-1,4,5,8-naphthyltetracarboxylimide)/metal interfaces, interfacial energy diagrams determined by UPS correspond well with the actually observed carrier-injecting character at the interfaces. For ZnTPP (15,10,15,20-zinc-tetraphenylporphyrin), H/sub 2/TPP (5,10,15,20-tetraphenylporphyrin), and H/sub 2/T(4-Py)P (5,10,15,20-tetra(4-pyridyl) porphyrin)/metal interfaces, the shifts of the vacuum level as well as the energies of the levels in porphyrins could be expressed as a linear function of work function of the metal substrate. The slope of the linear function depended on the compound. These findings are in contrast to the traditional assumption of common vacuum level at the interfaces, For ZnTPP/metal interfaces, sample exposure to oxygen induced energy level shift in close relation with the change of the substrate work function at oxygen exposure. The present results have clearly demonstrated that direct observation of the interfacial electronic structure by microscopic method such as UPS is necessary for understanding the organic electronic devices such as EL devices and organic solar cells.
TL;DR: In this paper, the authors present results of the numerical simulation of the transient behavior of shallow junction single photon avalanche diodes (SPADs) and develop a bidimensional model for above breakdown simulations and show that the initially photogenerated charge density builds up locally by an avalanche multiplication process and then spreads over the entire detector area by a diffusion-assisted process.
Abstract: We present results of the numerical simulation of the transient behavior of shallow junction single photon avalanche diodes (SPAD's). We developed a bidimensional model for above breakdown simulations and show that the initially photogenerated charge density builds up locally by an avalanche multiplication process and then spreads over the entire detector area by a diffusion-assisted process. To model real geometries, we developed a simplified model based on the obtained results. The importance of the photon-assisted spreading mechanism is evaluated and compared with the diffusive one. The contribution of the photon-assisted mechanism is minor in these geometries. The model is compared with the experimental data on the avalanche leading edge and the timing resolution; the agreement is good. We conclude that the model can be considered to be a useful tool for the design of improved structures.
TL;DR: In this article, stress-induced leakage current (SILC) is examined both below and above the voltage at which the preexisting Fowler-Nordheim tunneling current dominates.
Abstract: Stress-induced leakage current (SILC) is examined both below and above the voltage at which the preexisting Fowler-Nordheim tunneling current dominates. Based on these results, it is argued that SILC is the result of inelastic rather than elastic trap-assisted tunneling. This clarification explains the well-known thickness dependence of the SILC at low fields that has identified it as a scaling limitation for nonvolatile memory tunnel oxide. It also explains a newly observed different thickness dependence at high fields and facilitates modeling of the electric field/voltage and trap density dependencies of the SILC.
TL;DR: In this paper, a physically-based, semi-empirical, local model for transverse-field dependent electron and hole mobility in MOS transistors is presented to accurately predict the measured relationship between the effective mobility and effective electric field over a wide range of substrate doping and bias.
Abstract: A new, comprehensive, physically-based, semiempirical, local model for transverse-field dependent electron and hole mobility in MOS transistors is presented. In order to accurately predict the measured relationship between the effective mobility and effective electric field over a wide range of substrate doping and bias, we account for the dependence of surface roughness limited mobility on the inversion charge density, in addition to including the effect of coulomb screening of impurities by charge carriers in the bulk mobility term. The result is a single mobility model applicable throughout a generalized device structure that gives good agreement with measured mobility data and measured MOS I-V characteristics over a wide range of substrate doping, channel length, transverse electric field, substrate bias, and temperature.
TL;DR: A new physical and continuous BSIM (Berkeley Short-Channel IGFET Model) I-V model in BSIM3v3 is presented for circuit simulation, which allows users to accurately describe the MOSFET characteristics over a wide range of channel lengths and widths for various technologies, and is attractive for statistical modeling.
Abstract: A new physical and continuous BSIM (Berkeley Short-Channel IGFET Model) I-V model in BSIM3v3 is presented for circuit simulation. Including the major physical effects in state-of-the art MOS devices, the model describes current characteristics from subthreshold to strong inversion as well as from the linear to the saturation operating regions with a single I-V expression, and guarantees the continuities of I/sub ds/, conductances and their derivatives throughout all V/sub gs/, V/sub ds/, and T/sub bs/, bias conditions. Compared with the previous BSIM models, the improved model continuity enhances the convergence property of the circuit simulators. Furthermore, the model accuracy has also been enhanced by including the dependencies of geometry and bias of parasitic series resistances, narrow width, bulk charge, and DIBL effects. The new model has the extensive built-in dependencies of important dimensional and processing parameters (e.g., channel length, width, gate oxide thickness, junction depth, substrate doping concentration, etc.). It allows users to accurately describe the MOSFET characteristics over a wide range of channel lengths and widths for various technologies, and is attractive for statistical modeling. The model has been implemented in the circuit simulators such as Spectre, Hspice, SmartSpice, Spice3e2, and so on.
TL;DR: In this article, both in situ and ex situ Ga/sub 2/O/sub 3/ deposition schemes utilizing molecular beams of gallium oxide have been investigated, and the existence of strong inversion in both n- and p-type GaAs has been clearly established.
Abstract: Thermodynamically stable, low D/sub it/ amorphous Ga/sub 2/O/sub 3/-(100) GaAs interfaces have been fabricated by extending molecular beam epitaxy (MBE) related techniques. We have investigated both in situ and ex situ Ga/sub 2/O/sub 3/ deposition schemes utilizing molecular beams of gallium oxide. The in situ technique employs Ga/sub 2/O/sub 3/ deposition on freshly grown, atomically ordered (100) GaAs epitaxial films in ultrahigh vacuum (UHV); the ex situ approach is based on thermal desorption of native GaAs oxides in UHV prior to Ga/sub 2/O/sub 3/ deposition. Unique electronic interface properties have been demonstrated for in situ fabricated Ga/sub 2/O/sub 3/-GaAs interfaces including a midgap interface state density D/sub it/ in the low 10/sup 10/ cm/sup -2/ eV/sup -1/ range and an interface recombination velocity S of 4000 cm/s. The existence of strong inversion in both n- and p-type GaAs has been clearly established. We will also discuss the excellent thermodynamic and photochemical interface stability. Ex situ fabricated Ga/sub 2/O/sub 3/-GaAs interfaces are inferior but still of a high quality with S=9000 cm/s and a corresponding D/sub it/ in the upper 10/sup 10/ cm/sup -2/ eV/sup -1/ range. We also developed a new numerical heterostructure model for the evaluation of capacitance-voltage (C-V), conductance-voltage (G-V), and photoluminescence (PL) data. The model involves selfconsistent interface analysis of electrical and optoelectronic measurement data and is tailored to the specifics of GaAs such as band-to-band luminescence and long minority carrier response time /spl tau//sub R/. We will further discuss equivalent circuits in strong inversion considering minority carrier generation using low-intensity light illumination.
TL;DR: The theoretical optimal pocket implant performance is to achieve an L/sub min/ approximately 55/spl sim/60% that of a uniform-channel MOSFET without pocket implant, which is a significant (over one technology generation) improvement.
Abstract: The normal and reverse short-channel effect of LDD MOSFET's with lateral channel-engineering (pocket or halo implant) has been investigated. An analytical model is developed which can predict V/sub th/ as a function of L/sub eff/, V/sub DS/, V/sub BS/, and pocket parameters down to 0.1-/spl mu/m channel length. The new model shows that the V/sub th/ roll-up component due to pocket implant has an exponential dependence on channel length and is determined roughly by (N/sub p/)/sup 1/4 /L/sub p/. The validity of the model is verified by both experimental data and two-dimensional (2-D) numerical simulation. On the basis of the model, a methodology to optimize the minimum channel length L/sub min/ is presented. The theoretical optimal pocket implant performance is to achieve an L/sub min/ approximately 55/spl sim/60% that of a uniform-channel MOSFET without pocket implant, which is a significant (over one technology generation) improvement. The process design window of pocket implant is analyzed. The design tradeoff between the improvement of short-channel immunity and the other device electrical performance is also discussed.
TL;DR: In this article, the chelate metal complexes are used as an organic electroluminescent (EL) material for full-color flat displays as an emitting material, which is a strong candidate for organic EL material in practical use.
Abstract: The chelate metal complexes, such as tris(8-hydroxyquinolinate)aluminum (Alq/sub 3/), have excellent electroluminescent (EL) properties. Several chelate metal complexes were developed and the experimental rule of molecular design for use in an organic EL device was found. When the chelate metal complex has the structure of an inner complex sell, the EL device is fabricated by conventional vacuum-vapor deposition. This rule was applied to some chelate metal complexes, and, as a result, various complex materials could be obtained. RGB (red, green, and blue) emission was achieved using only chelate metal complexes, after successfully obtaining high-luminance blue-emitting materials, such as azomethine-zinc complex. This shows that the chelate metal complexes can be applied to full-color flat displays as an emitting material. As for durability, when Bis(10-hydroxybenzo[h]quinolinato)beryllium (BeBq/sub 2/) was used as an electron transport layer, a lifetime (initial luminance: 500 cd/m/sup 2/) of more than 3500 h, which is a practical level, was achieved in running tests. Thus, it seems that chelate metal complexes are a strong candidate as an organic EL material in practical use.
TL;DR: In this article, the effect of the kink effect on polycrystalline silicon thin film transistors (poly-TFTs) was investigated by means of numerical simulations.
Abstract: Floating body effects in polycrystalline silicon thin film transistors (poly-TFTs) are investigated by means of numerical simulations. The current increase in the output characteristics at large V/sub DS/, usually referred to as the "kink effect" is explained by impact ionization occurring in the high-field region at the drain end of the channel. Its effect is enhanced by the action of a parasitic bipolar transistor in the back-channel region, whose base current arises from the impact generated holes. The dependence of the kink on the recombination kinetics is also investigated.
TL;DR: A novel Silicon-On-Insulator-with-Active-Substrate (SOIAS)based technology was developed whereby a back-gate is used to control the threshold voltage of the front-gate and this concept was demonstrated on a selectively scaled CMOS process implementing discrete devices and ring oscillators.
Abstract: The simultaneous reduction of power supply and threshold voltages for low-power design without suffering performance losses will eventually reach the limit of diminishing returns as static leakage power dissipation becomes a significant portion of the total power consumption. This is especially acute in systems that are idling most of the time. In order to meet the opposing requirements of high performance at reduced power supply voltage and low-static leakage power during idle periods, a dynamic threshold voltage control scheme is proposed. A novel Silicon-On-Insulator (SOI)-based technology called Silicon-On-Insulator-with-Active-Substrate (SOIAS) was developed whereby a back-gate is used to control the threshold voltage of the front-gate; this concept was demonstrated on a selectively scaled CMOS process implementing discrete devices and ring oscillators. For a 250 mV switch in threshold voltage, a reduction of 3-4 decades in subthreshold leakage current was measured.
TL;DR: The unit device consists of four tunnel junctions and operates as a two-way switch for single-electron transport and computer simulation shows that the designed circuits perform the logic operations correctly.
Abstract: The unit device consists of four tunnel junctions and operates as a two-way switch for single-electron transport. Any combinational logic can be implemented by connecting identical unit devices into a cascade to build the tree of a BDD graph. Several sample designs are presented for logic circuits of NAND, NOR, exclusive-OR, and AND-OR combinational logic. Computer simulation shows that the designed circuits perform the logic operations correctly.
TL;DR: In this article, a comprehensive study of TDDB of 6.5, 9-, 15-, and 22nm SiO/sub 2/ films under dc and pulsed bias has been conducted over a wide range of electric fields and temperatures.
Abstract: A comprehensive study of Time-Dependent Dielectric Breakdown (TDDB) of 6.5-, 9-, 15-, and 22-nm SiO/sub 2/ films under dc and pulsed bias has been conducted over a wide range of electric fields and temperatures. Very high temperatures were used at the wafer level to accelerate breakdown so tests could be conducted at electric fields as low as 4.5 MV/cm. New observations are reported for TDDB that suggest a consistent electric field and temperature dependence for intrinsic breakdown and a changing breakdown mechanism as a function of electric field. The results show that the logarithm of the median-test-time-to failure, log (t/sub 50/), is described by a linear electric field dependence with a field acceleration parameter that is not dependent on temperature. It has a value of approximately 1 decade/MV/cm for the range of oxide thicknesses studied and shows a slight decreasing trend with decreasing oxide thickness. The thermal activation E/sub a/ ranged between 0.7 and 0.95 eV for electric fields below 9.0 MV/cm for all oxide thicknesses. TDDB tests conducted under pulsed bias indicate that increased dielectric lifetime is observed under unipolar and bipolar pulsed stress conditions, but diminishes as the stress electric field and oxide thickness are reduced. This observation provides new evidence that low electric field aging and breakdown is not dominated by charge generation and trapping.
TL;DR: In this paper, the design, design issues, fabrication, and performance of a 2048/spl times/2048 active pixel image sensor in a 0.5-/spl mu/m standard CMOS process are discussed.
Abstract: In this paper, we discuss the design, design issues, fabrication, and performance of a 2048/spl times/2048 active pixel image sensor in a 0.5-/spl mu/m standard CMOS process. Each pixel, 7.5/spl times/7.5 /spl mu/m/sup 2/, consists of three transistors and a photo diode, resulting in a 12-million transistor chip with a die size of 16.3/spl times/16.5 mm. The pixel has a nonintegrating direct readout architecture, with a logarithmic light-to-voltage conversion. This allows the array to be fully random accessible, both in space and time. The sensor has eight analog outputs, each with a pixel rate of 4.5 MHz, which implies a maximum frame rate of eight full frames per second. Sub-sampling or windowing makes higher frame rates possible. The yield of the sensor is high if one accepts a small number of bad pixels.
TL;DR: In this paper, the authors describe the key features and performance data of a 1024/spl times/1026-pixel frame-transfer imager for use as a soft-X-ray detector on the NASA X-ray observatory Advanced Xray Astrophysics Facility (AXAF).
Abstract: We describe the key features and performance data of a 1024/spl times/1026-pixel frame-transfer imager for use as a soft-X-ray detector on the NASA X-ray observatory Advanced X-ray Astrophysics Facility (AXAF). The four-port device features a floating-diffusion output circuit with a responsivity of 20 /spl mu/V/e/sup -/ and noise of about 2 e/sup -/ at a 100-kHz data rate. Techniques for achieving the low sense-node capacitance of 5 fF are described. The CCD is fabricated on high-resistivity p-type silicon for deep depletion and includes narrow potential troughs for transfer inefficiencies of around 10/sup -7/. To achieve good sensitivity at energies below 1 keV, we have developed a back-illumination process that features low recombination losses at the back surface and has produced quantum efficiencies of about 0.7 at 277 eV (carbon K/spl alpha/).
TL;DR: In this article, a first-principles approach to inversion layer quantization, valid for arbitrarily complex band structures, has been developed, which has allowed, for the first time, hole quantization and its effects on p-MOSFET device characteristics to be studied.
Abstract: A first-principles approach to inversion layer quantization, valid for arbitrarily complex band structures, has been developed. This has allowed, for the first time, hole quantization and its effects on p-MOSFET device characteristics to be studied. In addition, electron quantization effects are revisited, improving on previous, simpler approaches. In particular, the impact of quantization on the threshold voltages and "effective" gate oxide thicknesses of p- and n-MOSFETs is investigated. A simple compact model is provided to quantitatively describe the threshold voltage shifts at 300 K as a function of the doping concentration and the oxide thickness. The significance of hole quantization for buried channel p-MOS structures is also studied. The results can be used to both identify and model these effects using popular device simulators.
TL;DR: In this paper, a silicon-on-insulator (SOI) RF complementary metal-oxide-semiconductor (CMOS) technology for microwave applications up to 5 GHz has been developed.
Abstract: A silicon-on-insulator (SOI) RF complementary metal-oxide-semiconductor (CMOS) technology for microwave applications up to 5 GHz has been developed. The technology is based on ultra large scale integration (ULSI) CMOS processing using a high resistivity separation through implanted oxygen (SIMOX) substrate of typically 10 k/spl Omega/cm. Dedicated RF n-channel and RF p-channel MOSFET's with an effective channel length of 0.20 and 0.40 /spl mu/m have been fabricated using a multiple gate finger design. Maximum frequencies of operation f/sub max/ of 46 GHz (NMOS) and 16 GHz (PMOS) have been measured. Metal-Insulator-Metal (MIM) capacitances with up to 63 pF with 70 nF/cm/sup 2/, planar inductances with up to 25 nH and a quality factor up to 12 and coplanar waveguides with a loss <2.8 dB/cm at 5 GHz are monolithically integrated in the technology without additional processes and materials. Using this SOI-CMOS technology we have fabricated integrated silicon RF circuits, e.g., amplifiers, oscillators, and mixers, operating in the 2 GHz range.
TL;DR: The first frame-transfer CMOS active pixel sensor (APS) is reported and charge integration amplifer-based readout of the memory cells permits binning of pixels for variable resolution imaging.
Abstract: The first frame-transfer CMOS active pixel sensor (APS) is reported. The sensor architecture integrates an array of active pixels with an array of passive memory cells. Charge integration amplifer-based readout of the memory cells permits binning of pixels for variable resolution imaging. A 32/spl times/32 element prototype sensor with 24-/spl mu/m pixel pitch was fabricated in 1.2-/spl mu/m CMOS and demonstrated.
TL;DR: In this paper, the influence of image and exchange-correlation effects on the inversion layer and total gate capacitance in scaled Si MOSFETs was studied using a fully quantum-mechanical model.
Abstract: We use a fully quantum-mechanical model to study the influence of image and exchange-correlation effects on the inversion layer and total gate capacitance in scaled Si MOSFETs. We show that, when the device is in weak and moderate inversion, the inclusion of image and many-body exchange-correlation effects increases both the inversion layer and total gate capacitances and shifts the N/sub s/=N/sub s/(VG) characteristics of the device toward lower gate voltages.
TL;DR: In this article, a high-resolution monolithic nozzle array for inkjet printing is described, which uses a bulk anisotropic etching technology to undercut a network of highly-boron-doped silicon support ribs, forming an array of microchannels which are then sealed using thermal oxidation and LPCVD dielectrics.
Abstract: This paper describes a high-resolution monolithic nozzle array for inkjet printing. The nozzles are fabricated using a bulk anisotropic etching technology to undercut a network of highly-boron-doped silicon support ribs, forming an array of microchannels which are then sealed using thermal oxidation and LPCVD dielectrics. Closely-spaced trapezoidal or triangular nozzles are realized after cutting the wafer perpendicular to the microtubes. With a 21-/spl mu/m nozzle width and a 4-/spl mu/m nozzle-to-nozzle separation, a resolution of 1016 dots per inch (d/in) can be achieved. Polysilicon heaters are integrated on top of each microchannel so that when activated, the underlying ink is vaporized and a drop of ink is expelled to impinge on the paper. The fabrication of this device requires only five masks and is compatible with the addition of on-chip circuitry for multiplexing the heater control signals. Heat transfer efficiency to the ink is enhanced by the high thermal conductivity of the silicon ribs in the channel ceiling, while the bulk silicon maintains high interchannel isolation. Current pulses 20 /spl mu/s wide with a power density of 3.35/spl times/10/sup 8/ W/m/sup 2/ have been used in initial printing tests, resulting in 20-/spl mu/m diameter ink dots on a piece of paper which was set 2 mm away from the nozzle. The energy required to fire an ink drop is 11.5 /spl mu/J.