Showing papers in "IEEE Transactions on Electron Devices in 1998"

Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 /spl mu/m MOSFET's: A 3-D "atomistic" simulation study

Abstract: A three-dimensional (3-D) "atomistic" simulation study of random dopant induced threshold voltage lowering and fluctuations in sub-0.1 /spl mu/m MOSFETs is presented. For the first time a systematic analysis of random dopant effects down to an individual dopant level was carried out in 3-D on a scale sufficient to provide quantitative statistical predictions. Efficient algorithms based on a single multigrid solution of the Poisson equation followed by the solution of a simplified current continuity equation are used in the simulations. The effects of various MOSFET design parameters, including the channel length and width, oxide thickness and channel doping, on the threshold voltage lowering and fluctuations are studied using typical samples of 200 atomistically different MOSFETs. The atomistic results for the threshold voltage fluctuations were compared with two analytical models based on dopant number fluctuations. Although the analytical models predict the general trends in the threshold voltage fluctuations, they fail to describe quantitatively the magnitude of the fluctuations. The distribution of the atomistically calculated threshold voltage and its correlation with the number of dopants in the channel of the MOSFETs was analyzed based on a sample of 2500 microscopically different devices. The detailed analysis shows that the threshold voltage fluctuations are determined not only by the fluctuation in the dopant number, but also in the dopant position.

New insights in the relation between electron trap generation and the statistical properties of oxide breakdown

Abstract: In this paper it is demonstrated in a wide stress field range that breakdown in thin oxide layers occurs as soon as a critical density of neutral electron traps in the oxide is reached. It is proven that this corresponds to a critical hole fluence, since a unique relationship between electron trap generation and hole fluence is found independent of stress field and oxide thickness. In this way literature models relating breakdown to hole fluence or to trap generation are linked. A new model for intrinsic breakdown, based on a percolation concept, is proposed. It is shown that this model can explain the experimentally observed statistical features of the breakdown distribution, such as the increasing spread of the Q/sub BD/-distribution for ultrathin oxides. An important consequence of this large spread is the strong area dependence of the Q/sub BD/ for ultrathin oxides.

Modeling statistical dopant fluctuations in MOS transistors

Abstract: The impact of statistical dopant fluctuations on the threshold voltage V/sub T/ and device performance of silicon MOSFET's is investigated by means of analytical and numerical modeling. A new analytical model describing dopant fluctuations in the active device area enables the derivation of the standard deviation, /spl sigma/V/sub T/, of the threshold voltage distribution for arbitrary channel doping profiles. Using the MINIMOS device simulator to extend the analytical approach, it is found that /spl sigma/V/sub T/, can be properly derived from two-dimensional (2-D) or three-dimensional (3-D) simulations using a relatively coarse simulation grid. Evaluating the threshold voltage shift arising from dopant fluctuations, on the other hand, calls for full 3-D simulations with a numerical grid that is sufficiently refined to represent the discrete nature of the dopant distribution. The average V/sub T/-shift is found to be positive for long, narrow devices, and negative for short, wide devices. The fast 2-D MINIMOS modeling of dopant fluctuations enables an extensive statistical analysis of the intrinsic spreading in a large set of compact model parameters for state-of-the-art CMOS technology. It is predicted that V/sub T/-variations due to dopant fluctuations become unacceptably large in CMOS generations of 0.18 /spl mu/m and beyond when the present scaling scenarios are pursued. Parameter variations can be drastically reduced by using alternative device designs with ground-plane channel profiles.

Making silicon nitride film a viable gate dielectric

Abstract: To extend the scaling limit of thermal SiO/sub 2/ in the ultrathin regime when the direct tunneling current becomes significant, members of this author's research team at Yale University, in collaboration with the Jet Process Corporation, embarked on a program to explore the potential of silicon nitride as an alternative gate dielectric. In this paper, high-quality silicon nitride (or oxynitride) films made by a novel jet vapor deposition (JVD) technique are described. The JVD process utilizes a high-speed jet of light carrier gas to transport the depositing species onto the substrate to form the desired films. The film composition has been determined to consist primarily of Si and N, with some amounts of O and H. Metal-nitride-Si (MNS) capacitors based on the JVD nitride films deposited directly on Si exhibit relatively low densities of interface traps, fixed charge, and bulk traps. The interface traps at the nitride/Si interface exhibit different properties from those at the SiO/sub 2//Si interface in several aspects. In contrast to the conventional CVD silicon nitride, the high-field I-V characteristics of the JVD silicon nitride fit the Fowler-Nordheim (F-N) tunneling theory over four to five orders of magnitude in current, but do not fit at all the Frenkel-Poole (F-P) transport theory. This is consistent with the much lower concentration of electronic traps in the JVD silicon nitride. Results from the carrier separation experiment indicate that electron current dominates the gate current with very little hole contribution. Both theoretical calculation and experimental data indicate that the gate leakage current in JVD silicon nitride is significantly lower than that in silicon dioxide of the same equivalent oxide thickness. The breakdown characteristics of the JVD nitride are also respectable. Compared to their MOSFET counterparts, MNS transistors exhibit reduced low-field transconductance but enhanced high-field transconductance, perhaps due to the presence of border traps. As expected, the JVD silicon nitride films exhibit very strong resistance to boron penetration and oxidation at high temperatures. These properties, coupled with its room-temperature deposition process, make JVD silicon nitride an attractive candidate to succeed thermal SiO/sub 2/ as an advanced gate dielectric in future generations of ULSI devices.

A stochastic wire-length distribution for gigascale integration (GSI). I. Derivation and validation

Abstract: Based on Rent's Rule, a well-established empirical relationship, a rigorous derivation of a complete wire-length distribution for on-chip random logic networks is performed. This distribution is compared to actual wire-length distributions for modern microprocessors, and a methodology to calculate the wire-length distribution for future gigascale integration (GSI) products is proposed.

Negative capacitance effect in semiconductor devices

Abstract: Nontrivial capacitance behavior, including a negative capacitance (NC) effect, observed in a variety of semiconductor devices, is discussed emphasizing the physical mechanism and the theoretical interpretation of experimental data. The correct interpretation of NC can be based on the analysis of the time-domain transient current in response to a small voltage step or impulse, involving a self-consistent treatment of all relevant physical effects (carrier transport, injection, recharging, etc.). NC appears in the case of the nonmonotonic or positive-valued behavior of the time-derivative of the transient current in response to a small voltage step. The time-domain transient current approach is illustrated by simulation results and experimental studies of quantum well infrared photodetectors (QWIPs). The NC effect in QWIPs has been predicted theoretically and confirmed experimentally. The huge NC phenomenon in QWIP's is due to the nonequilibrium transient injection from the emitter caused by the properties of the injection barrier and the inertia of the QW recharging.

Improved equivalent circuit and analytical model for amorphous silicon solar cells and modules

Abstract: An improved equivalent circuit for hydrogenated amorphous silicon (a-Si:H) solar cells and modules is presented. It is based on the classic combination of a diode with an exponential current-voltage characteristic, of a photocurrent source plus a new term representing additional recombination losses in the i-layer of the device. This model/equivalent circuit matches the I(V) curves of a-Si:H cells over an illumination range of six orders of magnitude. The model clearly separates effects related to the technology of the device (series and parallel resistance) and effects related to the physics of the p-i-n junction (recombination losses). It also allows an effective /spl mu//spl tau/ product in the i-layer of the device to be determined, characterizing its state of degradation.

On the retention time distribution of dynamic random access memory (DRAM)

Abstract: The retention time distribution of high-density dynamic random access memory (DRAM) has been investigated. The key issue for controlling the retention time distribution has been clarified and its model has been proposed for the first time. Trench capacitor cell with 0.6-/spl mu/m ground rule was evaluated. It was found that the retention time distribution consists of "tail distribution" and "main distribution." "tail distribution," by which DRAM refresh characteristics are restricted, depends on the boron concentration of the memory cell region. As boron concentration of the memory cell region increases, "tail distribution" is enhanced. This enhancement is due to the increase of the junction leakage current from the storage node. For the purpose of accounting for the nature of "Tail Distribution," the concept of thermionic field emission (TFE) current has been introduced. The high electric field at pn junction of the storage node enhances thermionic field emission from a deep level. The activation energy of the deep level is normally distributed among the memory cells, which leads to the normal distribution of log(retention time). Two methods for reducing "tail distribution" are proposed. One is to reduce the electric field of the depletion layer of the storage node. The other is to reduce the concentration of the deep level for TFE current.

A stochastic wire-length distribution for gigascale integration (GSI). II. Applications to clock frequency, power dissipation, and chip size estimation

Abstract: For pt.I see ibid., vol.45, no.3, pp.580-9 (Mar. 1998). Based on Rent's Rule, a well-established empirical relationship, a complete wire-length distribution for on-chip random logic networks is used to enhance a critical path model; to derive a preliminary dynamic power dissipation model; and to describe optimal architectures for multilevel wiring networks that provide maximum interconnect density and minimum chip size.

Design considerations and experimental analysis of high-voltage SiC Schottky barrier rectifiers

Abstract: Practical design of high-voltage SiC Schottky rectifiers requires an understanding of the device physics that affect the key performance parameters. Forward characteristics of SiC Schottky rectifiers follow thermionic emission theory and are relatively well understood. However, the reverse characteristics are not well understood and have not been experimentally investigated in-depth. In this paper we report the analysis and experimental results of both the forward and reverse characteristics of high-voltage SiC Schottky rectifiers. Ti and Ni Schottky rectifiers with boron implant edge termination were fabricated on n-type 4H SiC samples. Ni Schottky rectifiers fabricated on a 13-/spl mu/m thick 3.5/spl times/10/sup 15/ cm/sup -3/ epilayer have a current density of 100 A/cm/sup 2/ at approximately 2 V forward bias and a reverse leakage current density of less than 0.1 A/cm/sup 2/ at a reverse bias of 1720 V. The reverse leakage current is observed to depend on device area, Schottky barrier height, electric field at the metal-semiconductor interface, and temperature (a decreasing temperature dependence with increasing reverse bias). In addition. the reverse leakage current magnitude is larger and the electric field dependence is stronger than predicted by thermionic emission and image-force barrier height lowering. This suggests the reverse leakage current is due to a combination of thermionic field emission and field emission.

The physical and electrical effects of metal-fill patterning practices for oxide chemical-mechanical polishing processes

Abstract: In oxide chemical-mechanical polishing (CMP) processes, layout pattern dependent variation in the interlevel dielectric (ILD) thickness can reduce yield and impact circuit performance. Metal-fill patterning practices have emerged as a technique for substantially reducing layout pattern dependent ILD thickness variation. We present a generalizable methodology for selecting an optimal metal-fill patterning practice with the goal of satisfying a given dielectric thickness variation specification while minimizing the added interconnect capacitance associated with metal-fill patterning. Data from two industrial-based experiments demonstrate the beneficial impact of metal-fill on dielectric thickness variation, a 20% improvement in uniformity in one case and a 60% improvement in the other case, and illustrate that pattern density is the key mechanism involved. The pros and cons of two different metal-fill patterning practices-grounded versus floating metal-are explored. Criteria for minimizing the effect of floating or grounded metal-fill patterns on delay or crosstalk parameters are also developed based on canonical metal-fill structures. Finally, this methodology is illustrated using a case study which demonstrates an 82% reduction in ILD thickness variation.

Modeling and simulation of stress-induced leakage current in ultrathin SiO/sub 2/ films

Abstract: This paper presents a new model fur stress-induced leakage current (SILC) in ultrathin SiO/sub 2/ films, that is able to explain and accurately represent the experimental data obtained with MOS capacitors fabricated with different technologies and oxide thickness in the 3-7 nm range.

Modeled tunnel currents for high dielectric constant dielectrics

Abstract: The effect of dielectric constant and barrier height on the WKB modeled tunnel currents of MOS capacitors with effective oxide thickness of 2.0 nm is described. We first present the WKB numerical model used to determine the tunneling currents. The results of this model indicate that alternative dielectrics with higher dielectric constants show lower tunneling currents than SiO/sub 2/ at expected operating voltages. The results of SiO/sub 2//alternative dielectric stacks indicate currents which are asymmetric with electric field direction. The tunneling current of these stacks at low biases decreases with decreasing SiO/sub 2/ thickness. Furthermore, as the dielectric constant of an insulator increased, the effect of a thin layer of SiO/sub 2/ on the current characteristics of the dielectric stack increases.

Polarity dependent gate tunneling currents in dual-gate CMOSFETs

Abstract: Polarity dependence of the gate tunneling current in dual-gate CMOSFETs is studied over a gate oxide range of 2-6 nm. It is shown that, when measured in accumulation, the I/sub g/ versus V/sub g/ characteristics for the p/sup +//pMOSFET are essentially identical to those for the n/sup +//nMOSFET; however, when measured in inversion, the p/sup +//pMOSFET exhibits much lower gate current for the same |V/sub g/|. This polarity dependence is explained by the difference in the supply of the tunneling electrons. The carrier transport processes in p/sup +//pMOSFET biased in inversion are discussed in detail. Three tunneling processes are considered: (1) valence band hole tunneling from the Si substrate; (2) valence band electron tunneling from the p/sup +/-polysilicon gate; and (3) conduction band electron tunneling from the p/sup +/-polysilicon gate. The results indicate that all three contribute to the gate tunneling current in an inverted p/sup +//pMOSFET, with one of them dominating in a certain voltage range.

Giant isotope effect in hot electron degradation of metal oxide silicon devices

Abstract: A giant isotope effect of hot electron degradation was found by annealing and passivating integrated circuits of recent complementary metal oxide silicon (CMOS) technology with deuterium instead of hydrogen. In this paper, we summarize our experience and present new results of secondary ion mass spectroscopy that correlate deuterium accumulation with reduced hot electron degradation. We also present a first account of the physical theory of this effect with a view on engineering application and point toward rules of current and voltage scaling as obtained from this theory.

Avalanche multiplication noise characteristics in thin GaAs p/sup +/-i-n/sup +/ diodes

Abstract: Avalanche noise measurements have been performed on a range of homojunction GaAs p/sup +/-i-n/sup +/ and n/sup +/-i-p/sup +/ diodes with "i" region widths, /spl omega/ from 2.61 to 0.05 /spl mu/m. The results show that for /spl omega//spl les/1 /spl mu/m the dependence of excess noise factor F on multiplication does not follow the well-established continuous noise theory of McIntyre [1966]. Instead, a decreasing noise factor is observed as /spl omega/ decreases for a constant multiplication. This reduction in F occurs for both electron and hole initiated multiplication in the thinner /spl omega/ structures even though the ionization coefficient ratio is close to unity. The dead-space, the minimum distance a carrier must travel to gain the ionization threshold energy, becomes increasingly important in these thinner structures and largely accounts for the reduction in noise.

Fully-depleted SOI CMOS for analog applications

Abstract: Fully-depleted (FD) SOI MOSFETs offer near-ideal properties for analog applications. In particular their high transconductance to drain current ratio allows one to obtain a higher gain than from bulk devices, and the reduced body effect permits one to fabricate more efficient pass gates. The excellent behavior of SOI MOSFETs at high temperature or at gigahertz frequencies is outlined as well.

Accurate SOI MOSFET characterization at microwave frequencies for device performance optimization and analog modeling

Abstract: The maturation of low-cost silicon-on-insulator (SOI) MOSFET technology in the microwave domain has brought about a need to develop specific characterization techniques. An original scheme is presented, which, by combining careful design of probing and calibration structures, rigorous in situ calibration, and a new powerful direct extraction method, allows reliable identification of the parameters of the non-quasi-static (NQS) small-signal model for MOSFETs. The extracted model is shown to be valid up to 40 GHz.

An improved MOSFET model for circuit simulation

Abstract: Problems that have continued to remain in some of the recently published MOSFET compact models are demonstrated in this paper. Of particular interest are discontinuities observed in these models at the boundary between forward and reverse mode operation. A new MOSFET model is presented that overcomes the errors present in state-of-the-art models. Comparison with measured data is also presented to validate the new model.

AlSb/InAs HEMT's for low-voltage, high-speed applications

Abstract: The design, fabrication, and characterization of 0.1 /spl mu/m AlSb/InAs HEMT's are reported. These devices have an In/sub 0.4/Al/sub 0.6/As/AlSb composite barrier above the InAs channel and a p/sup +/ GaSb layer within the AlSb buffer layer. The HEMT's exhibit a transconductance of 600 mS/mm and an f/sub T/ of 120 GHz at V/sub Ds/=0.6 V. An intrinsic f/sub T/ of 160 GHz is obtained after the gate bonding pad capacitance is removed from an equivalent circuit. The present HEMT's have a noise figure of 1 dB with 14 dB associated gain at 4 GHz and V/sub Ds/=0.4 V. Noise equivalent circuit simulation indicates that this noise figure is primarily limited by gate leakage current and that a noise figure of 0.3 dB at 4 GHz is achievable with expected technological improvements. HEMT's with a 0.5 /spl mu/m gate length on the same wafer exhibit a transconductance of 1 S/mm and an intrinsic f/sub T/L/sub g/, product of 50 GHz-/spl mu/m.

DRAM technology perspective for gigabit era

Abstract: Many challenges emerge as the DRAM enters into a generation of the gigabit density era. Most of the challenges come from the shrink technology which scales down minimum feature size by a factor of 0.84 per year. The need for higher performance to narrow the bandwidth mismatch between fast processors and slower memories and lower power consumption drives the DRAM technology toward smaller cell size, faster memory cell operation, less power consumption, and longer data retention times. In addition, increasingly complicated wafer processing requires simple process. In this paper, the challenges brought from the extremely small minimum feature, high performance, and simple wafer processing will be discussed. The solutions to overcome the challenges will be described focusing on the memory cell scheme, lithography, device, memory cell capacitor, and metallization.

An efficient approach to noise analysis through multidimensional physics-based models

Abstract: The paper presents a general approach to numerically simulate the noise behavior of bipolar solid-state electron devices through a physics-based multidimensional device model. The proposed technique accounts for noise sources due to carrier velocity and population fluctuations. The power and correlation spectra of the external current or voltage fluctuations are evaluated through a Green's function, linear perturbation theory equivalent to the classical Impedance Field Method for noise analysis and its generalizations. The numerical implementation of the method is performed through an efficient technique, which allows noise analysis to be carried out with negligible overhead with respect to the small-signal simulation. Some case studies are analyzed in order to compare the present approach with theoretical results from the classical noise theory of p-n junctions and bipolar transistors.

A 0.1-/spl mu/m delta-doped MOSFET fabricated with post-low-energy implanting selective epitaxy

Abstract: A simple fabrication technology for delta-doped MOSFETs, named post-low-energy implanting selective epitaxy (PLISE) is presented. The PLISE technology needs no additional photo-lithography mask, deposition step or etching step even for CMOS devices. The only additional step is growing undoped epitaxial channel layers by UHV-CVD after the channel implantation. With this technology, delta-doped NMOSFETs with 0.1-/spl mu/m gate length were successfully fabricated. By optimizing the epi-layer thickness and the channel doping level, short-channel effects are suppressed enough to achieve 0.1-/spl mu/m gate length. Moreover, the junction capacitance at zero bias is reduced by 50%.

A physical model for threshold voltage instability in Si/sub 3/N/sub 4/-gate H/sup +/-sensitive FET's (pH ISFET's)

Abstract: A physical model is presented which quantitatively describes the threshold voltage instability, commonly known as drift, in n-channel Si/sub 3/N/sub 4/-gate pH ISFET's. The origin of the so-called drift is postulated to be associated with the relatively slow conversion of the silicon nitride surface to a hydrated SiO/sub 2/ or oxynitride layer. The rate of hydration is modeled by a hopping and/or trap-limited transport mechanism known as dispersive transport. Hydration leads to a decrease in the overall insulator capacitance with time, which gives rise to a monotonic temporal increase in the threshold voltage.

A new model for the field dependence of intrinsic and extrinsic time-dependent dielectric breakdown

Abstract: The field acceleration of intrinsic and extrinsic breakdown is studied. For the intrinsic mode an exp(1/E)-acceleration law is found, while for the extrinsic mode an new exp (E)-acceleration law for Q/sub BD/ is proposed. This field acceleration model is implemented in a maximum likelihood algorithm together with a new analytical expression for fitting competing Weibull distributions. With this algorithm an extensive t/sub BD/-data set measured at different stress conditions can be fitted excellently in one single calculation. From the result, predictions of low-field oxide reliability are made and the screening conditions in order to guarantee a pre-set reliability specification are calculated.

Degradation of thin tunnel gate oxide under constant Fowler-Nordheim current stress for a flash EEPROM

Abstract: The degradation of thin tunnel gate oxide under constant Fowler-Nordheim (FN) current stress was studied using flash EEPROM structures. The degradation is a strong function of the amount of injected charge density (Q/sub inj/), oxide thickness, and the direction of stress. Positive charge trapping is usually dominant at low Q/sub inj/ followed by negative charge trapping at high Q/sub inj/, causing a turnaround of gate voltage and threshold voltage. Interface trap generation continues to increase with increasing stress, as evidenced by subthreshold slope and transconductance. Gate injection stress creates more positive charge traps and interface traps than does substrate injection stress. Oxide degradation gets more severe for thicker oxide, due to more oxide charge trapping and interface trap generation by impact ionization. A simple model of oxide degradation and breakdown was established based on the experimental results. It indicates that the damage in the oxide is more serious near the anode interface by impact ionization and oxide breakdown is also closely related to surface roughness at the cathode interface. When all the damage sites in the oxide connect and a conductive path between cathode and anode is formed, oxide breakdown occurs. The damage is more serious for thicker oxide because a thicker oxide is more susceptible to impact ionization.

Advanced thin-film silicon-on-sapphire technology: microwave circuit applications

Abstract: This paper reviews the prospects of thin-film silicon-on-sapphire (TFSOS) CMOS technology in microwave applications in the 1-5 GHz regime and beyond and presents the first demonstration of microwave integrated circuits based on this technology, MOSFET's optimized for microwave use, with 0.5-/spl mu/m optically defined gate lengths and a T-gate structure, have f/sub t/ values of 25 GHz (14 GHz) and f/sub max/ values of 66 GHz (41 GHz) for n-channel (p-channel) devices and have noise figure values below 1 db at 2 GHz, some of the best reported performance characteristics of any silicon-based MOSFET's to date. On-chip spiral inductors exhibit quality factors above ten. Circuit performance compares favorably with that of other CMOS-based technologies and approach performance levels similar to those obtained by silicon bipolar technologies. The results demonstrate the significant potential of this technology for microwave applications.

A robust and physical BSIM3 non-quasi-static transient and AC small-signal model for circuit simulation

Abstract: A new non-quasi-static (NQS) MOSFET model, which is applicable for both large-signal transient and small-signal ac analysis, has been developed. It employs a physical relaxation time approach to take care of the finite channel charging time to reach equilibrium and the effect of instantaneous channel charge re-distribution. The NQS model is formulated independently from the dc I-V and the charge-capacitor model, thus can be easily applied to any existing simulators. The model has been implemented in the newly released BSIM3 version 3, and comparison has been made among this model, common quasi-static (QS) SPICE models and PISCES two-dimensional (2-D) numerical device simulator. While predicting accurate NQS behavior, the time penalty for using the new model is only about 20-30% more than the common QS models. It is much less than the time required by other NQS models reported. Limitations and compromises between simplicity, efficiency and accuracy are also discussed.

RF measurement technique for characterizing thin dielectric films

Abstract: We have developed a novel technique for measuring the dielectric constant and loss tangent of a thin film dielectric material up to 5 GHz. The dielectric film needs to be deposited on a metal layer and capped with a metal electrode layer. The bottom metal layer does not have to be very conductive, as long as its sheet resistance is uniform and known. Only one step lithography on the top metal layer is required. No dc electrical contact to the bottom metal layer is necessary. The measurement is taken with a Vector Network Analyzer and a coplanar-wave-guide miniature wafer probe.

Technology for advanced high-performance microprocessors

Abstract: This paper describes the development of logic technologies that meet the density, performance, power, and manufacturing requirements for advanced high-performance microprocessors. Aggressive scaling of MOS transistor dimensions along with reduced power supply provide devices with high performance, low power, and good reliability. Multiple layers of planarized aluminum interconnect with high aspect ratios are used to address the increasing importance of interconnect density and performance. Static RAM test vehicles with small 6-transistor cell sizes are used to develop these logic technologies and to provide early demonstrations of yield and performance capabilities. The manufacturing strategy includes development group ownership of the technology from inception to early manufacturing ramp, extensive reuse of prior generation process equipment and modules, and a "copy exactly" methodology to ensure successful process startup and ramp in multiple facilities.