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Showing papers in "IEEE Transactions on Electron Devices in 1999"


Journal ArticleDOI
TL;DR: In this article, a new technique is presented which allows the frequency-independent device capacitance to be accurately extracted from impedance measurements at two frequencies for a 1.7 nm SiO/sub 2/ capacitor.
Abstract: As oxide thickness is reduced below 2.5 nm in MOS devices, both series and shunt parasitic resistances become significant in capacitance-voltage (C-V) measurements. A new technique is presented which allows the frequency-independent device capacitance to be accurately extracted from impedance measurements at two frequencies. This technique is demonstrated for a 1.7 nm SiO/sub 2/ capacitor.

492 citations


Journal ArticleDOI
TL;DR: In this paper, the dual material gate (DMG) FET was proposed and demonstrated, where the gate consists of two laterally contacting materials with different work functions, such that the threshold voltage near the source is more positive than that near the drain, resulting in a more rapid acceleration of charge carriers in the channel.
Abstract: A generic new type of field effect transistor (FET), the dual material gate (DMG) FET, is proposed and demonstrated. The gate of the DMGFET consists of two laterally contacting materials with different work functions. This novel gate structure takes advantage of material work function difference in such a way that the threshold voltage near the source is more positive than that near the drain (for n-channel FET, the opposite for p-channel FET), resulting in a more rapid acceleration of charge carriers in the channel and a screening effect to suppress short-channel effects. Using the heterostructure FET as a vehicle, the principle, computer simulation results, design guidelines, processing, and characterization of the DMGFET are discussed in detail.

450 citations


Journal ArticleDOI
TL;DR: In this paper, the potential impact of high/spl kappa/ gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities using a two-dimensional (2D) simulator implemented with quantum mechanical models.
Abstract: The potential impact of high-/spl kappa/ gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities using a two-dimensional (2-D) simulator implemented with quantum mechanical models. It is found that the short-channel performance degradation is caused by the fringing fields from the gate to the source/drain regions. These fringing fields in the source/drain regions further induce electric fields from the source/drain to channel which weakens the gate control. The gate dielectric thickness-to-length aspect ratio is a proper parameter to quantify the percentage of the fringing field and thus the short channel performance degradation. In addition, the gate stack architecture plays an important role in the determination of the device short-channel performance degradation. Using double-layer gate stack structures and low-/spl kappa/ dielectric as spacer materials can well confine the electric fields within the channel thereby minimizing short-channel performance degradation. The introduction of a metal gate not only eliminates the poly gate depletion effect, but also improves short-channel performance. Several approaches have been proposed to adjust the proper threshold voltage when midgap materials or metal gates are used.

335 citations


Journal ArticleDOI
TL;DR: In this paper, a whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole chip ESDprotection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits.
Abstract: A whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole-chip ESD protection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits. The efficient VDD-to-VSS ESD clamp circuit has been designed to provide a low-impedance path between the VDD and VSS power lines of the IC during the ESD-stress condition, but this ESD clamp circuit is kept off when the IC is under its normal operating condition. Due to the parasitic resistance and capacitance along the VDD and VSS power lines, the ESD-protection efficiency is dependent on the pin location on a chip. Therefore, an experimental test chip has been designed and fabricated to build up a special ESD design rule for whole-chip ESD protection in a 0.8-/spl mu/m CMOS technology. This whole-chip ESD protection design has been practically used to rescue a 0.8-/spl mu/m CMOS IC product with a pin-to-pin HBM ESD level from the original level of 0.5 kV to become above 3 kV.

323 citations


Journal ArticleDOI
TL;DR: In this article, the authors present a new theory that incorporates history-dependent ionization coefficients, and it is shown that this model can be utilized to calculate the low-frequency properties of avalanche photodiodes (APD's) (gain, noise, and breakdown probability in the Geiger mode) and the frequency response.
Abstract: Impact ionization in thick multiplication regions is adequately described by models in which the ionization coefficients are functions only of the local electric field. In devices with thin multiplication lengths, nonlocal effects become significant, necessitating new models that account for the path that a carrier travels before gaining sufficient energy to impact ionize. This paper presents a new theory that incorporates history-dependent ionization coefficients, and it is shown that this model can be utilized to calculate the low-frequency properties of avalanche photodiodes (APD's) (gain, noise, and breakdown probability in the Geiger mode) and the frequency response. A conclusion of this work is that an ionization coefficient is not a fundamental material characteristic at a specific electric field and that any experimental determination of ionization coefficients is valid only for the particular structure on which the measurement was performed.

283 citations


Journal ArticleDOI
TL;DR: In this paper, a new thermal oxidation process of growing a dry oxide then following with a wet re-oxidation anneal produces an oxide with the dielectric strength of a dry oxides and the high-quality interface of a wet oxide.
Abstract: Significant improved high-temperature reliability of SiC metal-insulator-semiconductor (MIS) devices has been achieved with both thermally grown oxides and by using a stacked dielectric consisting of silicon oxide-nitride-oxide (ONO). Capacitors of p-type 6H-SiC, n-type 6H-SiC and n-type 4H-SiC were fabricated with a variety of insulators. The best performance was accomplished only with insulators incorporating silicon dioxide. A new thermal oxidation process of growing a dry oxide then following with a wet re-oxidation anneal produces an oxide with the dielectric strength of a dry oxide and the high-quality interface of a wet oxide. MIS field effect transistors (MISFETs) with an ONO gate insulator had surface channel mobilities similar to MISFETs with thermal gate oxides, and demonstrated a lifetime of 10 days at 335/spl deg/C and 15 V bias. The lifetime of the ONO MISFET was a factor of 100 higher than for devices fabricated with deposited oxides, which had been the prior state of the art for high-temperature MISFETs on SiC.

271 citations


Journal ArticleDOI
TL;DR: In this paper, the small-molecule polycyclic aromatic hydrocarbon pentacene was used as the active material for organic thin-film transistors (TFTs).
Abstract: We have fabricated organic thin-film transistors (TFT's) using the small-molecule polycyclic aromatic hydrocarbon pentacene as the active material. Devices were fabricated on glass substrates using low-temperature ion-beam deposited silicon dioxide as the gate dielectric, ion-beam deposited palladium for the source and drain contacts, and vacuum-evaporated pentacene to form the active layer. Excellent electrical characteristics were obtained, including carrier mobility as large as 0.6 cm/sup 2//V-s, on/off current ratio as large as 10/sup 8/, and subthreshold slope as low as 0.7 V/dec, all record values for organic transistors fabricated on nonsingle-crystal substrates.

264 citations


Journal ArticleDOI
TL;DR: In this article, direct tunneling currents across ultra-thin gate oxides of MOS structures have been modeled for electrons from the inversion layers in p-type Si substrates using both quantum mechanical calculations for the silicon substrate and a modified WKB approximation for the transmission probability.
Abstract: Using both quantum mechanical calculations for the silicon substrate and a modified WKB approximation for the transmission probability, direct tunneling currents across ultra-thin gate oxides of MOS structures have been modeled for electrons from the inversion layers in p-type Si substrates. The modeled direct tunneling currents have been compared to experimental data obtained from nMOSFET's with direct tunnel gate oxides. Excellent agreement between the model and experimental data for gate oxides as thin as 1.5 nm has been achieved. Advanced capacitance-voltage techniques have been employed to complement direct tunneling current modeling and measurements. With capacitance-voltage (C-V) techniques, direct tunneling currents can be used as a sensitive characterization technique for direct tunnel gate oxides. The effects of both silicon substrate doping concentration and polysilicon doping concentration on the direct tunneling current have also been studied as a function of applied gate voltage.

228 citations


Journal ArticleDOI
TL;DR: In this paper, 1 kV 4H and 6 h SiC Schottky diodes utilizing a metal-oxide overlap structure for electric field termination were fabricated using Ni-SiC ohmic contact formation.
Abstract: We have fabricated 1 kV 4H and 6H SiC Schottky diodes utilizing a metal-oxide overlap structure for electric field termination. This simple structure when used with a high barrier height metal such as Ni has consistently given us good yield of Schottky diodes with breakdown voltages in excess of 60% of the theoretically calculated value. This paper presents the design considerations, the fabrication procedure, and characterization results for these 1 kV Ni-SiC Schottky diodes. Comparison to similarly fabricated Pt-SiC Schottky diodes is reported. The Ni-SiC ohmic contact formation has been studied using Auger electron spectroscopy and X-ray diffraction. The characterization study includes measurements of current-voltage (I-V) temperature and capacitance-voltage (C-V) temperature characteristics. The high-temperature performance of these diodes has also been investigated. The diodes show good rectifying behavior with ON/OFF current ratios, ranging from 10/sup 6/ to 10 at 27/spl deg/C and in excess of 10/sup 6/ up to 300/spl deg/C.

202 citations


Journal ArticleDOI
TL;DR: In this paper, the effects of surface defects on performance of kV-class 4H- and 6H-SiC epitaxial p-n junction diodes were investigated.
Abstract: Effects of surface defects on performance of kV-class 4H- and 6H-SiC epitaxial p-n junction diodes were investigated. The perimeter recombination and generation, instead of the bulk process, are responsible for forward recombination current and reverse leakage current of the diodes, respectively. Mapping studies of surface morphological defects have revealed that triangular-shaped defects severely degrade high-blocking capability of the diodes whereas shallow round pits and scratch give no direct impact. Device-killing defects in SiC epilayers are discussed based on breakdown voltage mapping. Effective minority carrier lifetimes are mainly limited not by bulk recombination but by perimeter recombination.

200 citations


Journal ArticleDOI
TL;DR: In this article, the authors investigated the electrical properties of the double-gate MOSFET and showed that the ideality factor in subthreshold is equal to unity, i.e., the slope of the turn-on characteristic is 60 mV/decade at room temperature.
Abstract: In this work, we investigate the electrical properties of the Double-Gate MOSFET (DG-MOSFET), which turn out to be very promising for device miniaturization below 0.1 /spl mu/m. A compact model which accounts for charge quantization within the channel, Fermi statistics, and nonstatic effects in the transport model is worked out. The main results of this investigation are: (1) the ideality factor in subthreshold is equal to unity, i.e., the slope of the turn-on characteristic is 60 mV/decade at room temperature; (2) the drain-induced barrier lowering is minimized by the shielding effect of the double gate, which allows us to reduce the channel length below 30 nm; and (3) the device transconductance per unit width is maximized by the combination of the double gate and by a strong velocity overshoot which occurs in response to the sudden variation of the electric field at the source end of the channel, and which can be further strengthened near the drain in view of the short device length. As a result, a sustained electron velocity of nearly twice the saturation velocity is achievable. The above results prove that the potential performance advantages of the double-gate device architecture may be worth the development effort.

Journal ArticleDOI
TL;DR: In this article, a detailed three-dimensional (3D) statistical "atomistic" simulation study of fluctuation-resistant sub 0.1/spl mu/m MOSFET architectures with epitaxial channels and delta doping is presented.
Abstract: A detailed three-dimensional (3-D) statistical "atomistic" simulation study of fluctuation-resistant sub 0.1-/spl mu/m MOSFET architectures with epitaxial channels and delta doping is presented. The need for enhancing the fluctuation resistance of the sub-0.1-/spl mu/m generation transistors is highlighted by presenting summarized results from atomistic simulations of a wide range of conventional devices with uniformly doped channels. According to our atomistic results, the doping concentration dependence of the random dopant-induced threshold voltage fluctuations in conventional devices is stronger than the analytically predicted fourth-root dependence. As a result of this, the scaling of such devices will be restricted by the "intrinsic" random dopant-induced fluctuations earlier than anticipated. Our atomistic simulations confirm that the introduction of a thin epitaxial layer in the MOSFET's channel can efficiently suppress the random dopant-induced threshold voltage fluctuations in sub-0.1-/spl mu/m devices. For the first time, we observe an "anomalous" reduction in the threshold voltage fluctuations with an increase in the doping concentration behind the epitaxial channel, which we attribute to screening effects. Also, for the first time we study the effect of a delta doping, positioned behind the epitaxial layer, on the intrinsic threshold voltage fluctuations. Above a certain thickness of epitaxial layer, we observe a pronounced anomalous decrease in the threshold voltage fluctuation with the increase of the delta doping. This phenomenon, which is also associated with screening, enhances the importance of the delta doping in the design of properly scaled fluctuation-resistant sub-0.1-/spl mu/m MOSFET's.

Journal ArticleDOI
TL;DR: In this article, a new experimental technique was proposed to study the transport properties of stress-induced leakage current (SILC), based on the carrier separation measurement for p-channel MOSFETs, the quantum yield of impact ionization for electrons involved in the SILC process was evaluated directly from the change in the source and gate currents of p-MOSFets before and after stressing.
Abstract: We propose a new experimental technique to study the transport properties of stress-induced leakage current (SILC). Based on the carrier separation measurement for p-channel MOSFETs, the quantum yield of impact ionization for electrons involved in the SILC process is evaluated directly from the change in the source and gate currents of p-MOSFETs before and after stressing. Since the relationship between the electron energy and the quantum yield is established for direct and FN tunneling currents, the electron energy of electrons involved in the SILC process can be determined from the quantum yield. The results reveal that the measured energy of electrons in the SILC process is lower roughly by 1.5 eV than the energy expected in the elastic tunneling process. Trap-assisted inelastic tunneling model is proposed as a conduction mechanism of SILC accompanied by energy relaxation. It is shown, through the evaluation of the substrate hole current in n-channel MOSFETs, that the contribution of trap-assisted valence electron tunneling, another possible mechanism to explain the energy relaxation, to SILC is small.

Journal ArticleDOI
Toyoji Yamamoto1, K. Uwasawa1, Tohru Mogami1
TL;DR: In this paper, the bias temperature instability in surface-channel p/sup +/ polysilicon gate p-MOSFETs was evaluated and it was found that a large negative threshold voltage shift (/spl Delta/V/sub th,BT/) was induced by negative bias temperature (BT) stress in short-channel P/sup+/ poly silicon gate mOSFets, and sufficient care should be taken in scaled dual-gate CMOS devices.
Abstract: The bias temperature instability in surface-channel p/sup +/ polysilicon gate p-MOSFETs was evaluated. It was found that a large negative threshold voltage shift (/spl Delta/V/sub th,BT/) is induced by negative bias temperature (BT) stress in short-channel p/sup +/ polysilicon gate p-MOSFETs. This Vth shift, which depends on the gate length of p-MOSFETs, is a new degradation mode. In this degradation, the negative /spl Delta/V/sub th,BT/ increases significantly with a reduction in the gate length. It was shown that this is because of the local degradation of the gate oxide near the gate edge. This degradation is caused by the electrochemical reaction between holes and oxide defects and it is enhanced by boron penetration through the gate oxide from p/sup +/-gate. For the bias temperature instability in p/sup +/-gate p-MOSFETs, sufficient care should be taken in scaled dual-gate CMOS devices.

Journal ArticleDOI
TL;DR: In this paper, a new theory for impact ionization that utilizes history-dependent ionization coefficients to account for the nonlocal nature of the ionization process has been described, and a systematic study of the noise characteristics of GaAs homojunction avalanche photodiodes with different multiplication layer thicknesses is also presented.
Abstract: For Part I see R.J. McIntyre, ibid., vol.46, no.8, pp.1623-31 (1999). In Part I, a new theory for impact ionization that utilizes history-dependent ionization coefficients to account for the nonlocal nature of the ionization process has been described. In this paper, we will review this theory and extend it with the assumptions that are implicitly used in both the local-field theory in which the ionization coefficients are functions only of the local electric field and the new one. A systematic study of the noise characteristics of GaAs homojunction avalanche photodiodes with different multiplication layer thicknesses is also presented. It is demonstrated that there is a definite "size effect" for thin multiplication regions that is not well characterized by the local-field model. The new theory, on the other hand, provides very good fits to the measured gain and noise. The new ionization coefficient model has also been validated by Monte Carlo simulations.

Journal ArticleDOI
C.T. Black1, J.J. Welser1
TL;DR: In this article, a simple, semiclassical model of an idealized capacitor is used to estimate the capacitance correction due to the distribution of displacement charge in the metal electrodes, which contributes to the universally seen decrease in measured dielectric constant with capacitor film thickness.
Abstract: A consequence of the finite electronic screening length in metals is that electric fields penetrate short distances into the metal surface. Using a simple, semiclassical model of an idealized capacitor, we estimate the capacitance correction due to the distribution of displacement charge in the metal electrodes. We compare our result with experimental data from thin-film high-dielectric-constant capacitors, which are currently leading contenders for use in future high-density memory applications. This intrinsic mechanism contributes to the universally-seen decrease in measured dielectric constant with capacitor film thickness.

Journal ArticleDOI
TL;DR: In this article, the dc-measured reverse-breakdown characteristics of low-voltage (<250 V) small-area 4H-SiC p/sup +/-n diodes with and without elementary screw dislocations were compared.
Abstract: Given the high-density (/spl sim/10/sup 4/ cm/sup -2/) of elementary screw dislocations (Burgers vector=1c with no hollow core) in commercial SiC wafers and epilayers, all large current (>1 A) SiC power devices will likely contain elementary screw dislocations for the foreseeable future. It is therefore important to ascertain the electrical impact of these defects, particularly in high-field vertical power device topologies where SiC is expected to enable large performance improvements in solid-state high-power systems. This paper compares the dc-measured reverse-breakdown characteristics of low-voltage (<250 V) small-area (<5/spl times/10/sup -4/ cm/sup 2/) 4H-SiC p/sup +/-n diodes with and without elementary screw dislocations. Diodes containing elementary screw dislocations exhibited higher pre-breakdown reverse leakage currents, softer reverse breakdown current-voltage (I-V) knees, and highly localized microplasmic breakdown current filaments compared to screw dislocation-free devices. The observed localized 4H-SiC breakdown parallels microplasmic breakdown observed in silicon and other semiconductors, in which space-charge effects limit current conduction through the local microplasma as reverse bias is increased.

Journal ArticleDOI
TL;DR: In this article, a complete characterization of poly SiGe bolometers has been presented, and the impact of resistivity, bias voltage, thermal conductance, thickness, and dimensions of the active element on the device performance has been investigated.
Abstract: In this paper, we present a complete characterization of poly SiGe bolometers. Devices having different dimensions and different geometry have been fabricated. The dependence of the low-frequency noise and of the temperature coefficient of resistance (TCR) on resistivity in poly SiGe has been measured and modeled. The impact of resistivity, bias voltage, thermal conductance, thickness, and dimensions of the active element on the device performance has been investigated. It has been demonstrated that, by using the appropriate absorber and by optimizing the device parameters, poly SiGe bolometers are suitable for realizing high-performance focal plane arrays (FPA's).

Journal ArticleDOI
TL;DR: In this article, the authors presented an accurate modeling and efficient parameter extraction of the small signal equivalent circuit of submicrometer MOS transistors for high-frequency operation, based on a quasi-static approximation which was found to be adequate in the gigahertz range if the extrinsic components are properly modeled.
Abstract: Accurate modeling and efficient parameter extraction of the small signal equivalent circuit of submicrometer MOS transistors for high-frequency operation are presented The equivalent circuit is based on a quasi-static approximation which was found to be adequate in the gigahertz range if the extrinsic components are properly modeled It includes the complete intrinsic quasi-static MOS model, the series resistances of gate, source, and drain, and a substrate coupling network Direct extraction is performed by Y-parameter analysis on the equivalent circuit in the linear and saturation regions of operation The extracted results are physically meaningful and can be used to "de-embed" the extrinsic effects such as the substrate coupling within the device Good agreement has been obtained between the simulation results of the equivalent circuit and measured data up to 10 GHz

Journal ArticleDOI
TL;DR: In this paper, the effects of wet atmosphere during oxidation and anneal on thermally oxidized p-type and n-type MOS interface properties were systematically investigated for both 4H- and 6H-SiC.
Abstract: Effects of wet atmosphere during oxidation and anneal on thermally oxidized p-type and n-type MOS interface properties were systematically investigated for both 4H- and 6H-SiC. Deep interface states and fixed oxide charges were mainly discussed. The wet atmosphere was effective to reduce a negative flatband shift caused by deep donor-type interface states in p-type SiC MOS capacitors. Negative fixed charges, however, appeared near the interface during wet reoxidation anneal. In n-type SIC MOS capacitors, the flatband shift indicated a positive value when using wet atmosphere. The relation between interface properties and characteristics of n-channel planar 6H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs) was also investigated. There was little relation between the interface properties of p-type MOS capacitors and the channel mobility of MOSFETs. The threshold voltage of MOSFETs processed by wet reoxidation anneal was higher than that of without reoxidation anneal. A clear relation between the threshold voltage and the channel mobility was observed in MOSFETs fabricated on the same substrate.

Journal ArticleDOI
TL;DR: In this paper, a high resolution low-temperature polysilicon thin-film transistor driven light emitting polymer display (LT p-Si TFT LEPD) with integrated drivers has been developed.
Abstract: A high-resolution low-temperature polysilicon thin-film transistor driven light emitting polymer display (LT p-Si TFT LEPD) with integrated drivers has been developed. We adopted conductance control of the TFT and optimized design and voltage in order to achieve good gray scale and simple pixel circuit. A p-channel TFT is used in order to guarantee reliability in dc bias. An inter-layer reduces parasitic capacitance of bus lines. Because of the combination of the LT p-Si TFT and LEP, the display is thin, compact, and lightweight, as well as having low power consumption, wide viewing angle, and fast response.

Journal ArticleDOI
TL;DR: In this paper, the state-of-the-art of multijunction solar cells and the future prospects of this technology are discussed and a cost calculation showing that highly efficient cells under very high concentration would be able to produce electricity at costs competitive with electricity generation costs for some utilities.
Abstract: In this paper, we present the state-of-the-art of multijunction solar cells and the future prospects of this technology. Their use in terrestrial applications will likely be for concentrators operating at very high concentrations. Some trends are also discussed and we present a cost calculation showing that highly efficient cells under very high concentration would be able to produce electricity at costs competitive with electricity generation costs for some utilities.

Journal ArticleDOI
TL;DR: In this article, a model based on two parallel Schottky rectifiers with different barrier heights is presented, and it is shown that the excess current at low voltage can be explained by a lowering of the Schotty barrier in localized regions.
Abstract: Forward density-voltage (J-V) measurements of titanium/4H-SiC Schottky rectifiers are presented in a large temperature range. While some of the devices present a behavior in accordance with the thermionic current theory, others present an excess forward current at low voltage level. This anomaly appears more or less depending on the rectifier and on the temperature. A model based on two parallel Schottky rectifiers with different barrier heights is presented. The characteristics show good agreement. It is shown that the excess current at low voltage can be explained by a lowering of the Schottky barrier in localized regions. A proposal for the physical origin of these low barrier height areas is given.

Journal ArticleDOI
TL;DR: In this paper, the drift of copper ions in various low-permittivity (low-spl kappa/) polymer dielectrics to identify copper barrier requirements for reliable interconnect integration in future ULSI was addressed.
Abstract: This paper addresses the drift of copper ions (Cu/sup +/) in various low-permittivity (low-/spl kappa/) polymer dielectrics to identify copper barrier requirements for reliable interconnect integration in future ULSI. Stressing at temperatures of 150-275/spl deg/C and electric fields up to 1.5 MV/cm was conducted on copper-insulator-silicon capacitors to investigate the penetration of Cu/sup +/ into the polymers. The drift properties of Cu/sup +/ in six industrially relevant low-/spl kappa/ organic polymer insulators-parylene-F, benzocyclobutene, fluorinated polyimide, an aromatic hydrocarbon, and two varieties of poly(arylene ether)-were evaluated and compared by capacitance-voltage, current-time, current-voltage, and dielectric time-to-failure measurements. Our study shows that Cu/sup +/ drifts readily into fluorinated polyimide and poly(arylene ether), more slowly into parylene-F, and even more slowly into benzocyclobutene. Among these polymers, the copper drift barrier property appears to be improved by increased polymer crosslinking and degraded by polar functional groups in the polymers. A thin nitride cap layer can stop the drift. A physical model has been developed to explain the kinetics of Cu/sup +/ drift.

Journal ArticleDOI
TL;DR: In this article, a new I-V model to quantitatively represent stress-induced leakage current (SILC) is presented and compared with the experimental I-v characteristics, where the trap-assisted tunneling model is modified so as to include the energy relaxation of tunneling electrons.
Abstract: A new I-V model to quantitatively represent stress-induced leakage current (SILC) is presented and compared with the experimental I-V characteristics. The trap-assisted tunneling model is modified so as to include the energy relaxation of tunneling electrons, which has been experimentally verified by applying the carrier separation technique to MOSFETs with the SILC component. The energy relaxation is treated in the new model as the change in the energy level of traps before and after the capture of electrons during two-step tunneling. It is demonstrated that this model successfully represents the experimental I-V characteristics of the SILC component and, particularly, the low apparent barrier height in the Fowler-Nordheim (FN) plot of the SILC component. The calculated low barrier height is attributed to the dominance of direct tunneling mechanism on both tunneling into traps and out of traps. The impact of the energy relaxation during tunneling, used in the present model, on the I-V characteristics is discussed in terms of the trap distribution inside the gate oxide, compared with conventional elastic tunneling model.

Journal ArticleDOI
TL;DR: In this article, the authors reported a substantially improved efficiency for a multicrystalline silicon solar cell of 19.8% by enshrouding cell surfaces in thermally grown oxide to reduce their detrimental electronic activity and forming a hexagonally-symmetric "honeycomb" surface texture.
Abstract: This paper reports a substantially improved efficiency for a multicrystalline silicon solar cell of 19.8%. This is the highest ever reported efficiency for a multicrystalline silicon cell. The improved multicrystalline cell performance results from enshrouding cell surfaces in thermally grown oxide to reduce their detrimental electronic activity and from isotropic etching to form a hexagonally-symmetric "honeycomb" surface texture. This texture, largely of inverted hemispheres, reduces reflection loss and improves absorption of infrared light by effectively acting as a randomizer. Results of a ray tracing model are presented, with the notable finding that up to 90% of infrared light is trapped in the substrate after the first two passes, compared with only 65% for the well known inverted pyramid structure. These optical features are considered to contribute to an exceptionally high short-circuit current density of 38.1 mA/cm/sup 2/. A further improvement is expected by using under-etched wells for these honeycomb cells.

Journal ArticleDOI
TL;DR: In this article, the authors show that the electrical performance of thin cells drops strongly with decreasing cell thickness if solar cell manufacturing technologies without a backside passivation or a back surface field (BSF) are applied.
Abstract: One of the most effective approaches for a cost reduction of crystalline silicon solar cells is the better utilization of the crystals by cutting thinner wafers. However, such thin silicon wafers must have sufficient mechanical strength to maintain a high mechanical yield in cell and module manufacturing. The electrical performance of thin cells drops strongly with decreasing cell thickness if solar cell manufacturing technologies without a backside passivation or a back-surface-field (BSF) are applied. However, with the application of a BSF, stable efficiencies of over 17%, even with decreasing cell thickness, have been reached. Thin solar cells show lower photodegradation, as is normally observed for Cz-silicon cells with today's standard thickness (about 300 /spl mu/m) because of a higher ratio of the diffusion length compared to the cell thickness. Cells of about 100-150 /spl mu/m thickness fabricated with the production Cz-silicon show almost no photodegradation. Furthermore, thin boron BSF cells have a pronounced efficiency response under backside illumination. The backside efficiency increases with decreasing cell thickness and reaches 60% of the frontside cell efficiency for 150 /spl mu/m solar cells and also for solar modules assembled of 36 cells of a thickness of 150 /spl mu/m. Assuming, for example, a rearside illumination of 150 W/m/sup 2/, this results in an increased module power output of about 10% relatively.

Journal ArticleDOI
TL;DR: In this article, the authors demonstrate the viability of SiC-based detectors for a variety of radiation monitoring applications and demonstrate that they can achieve linear detector response up to thermal neutron fluxes of 2000 n/sub th//cm/sup 2/s.
Abstract: Neutron response studies have been performed on Schottky diodes fabricated using 4H-SiC material. These studies indicate that neutron detection using SiC diodes is possible without significant degradation in the energy resolution, noise characteristics or, most importantly, the neutron counting rate even after exposure to neutron fluences of 3.4/spl times/10/sup 17/ n/sub th//cm/sup 2/ (1/spl times/10/sup 17/ n/sub fast//cm/sup 2/; E/sub n.fast/>1 MeV), the highest yet examined. The results represent orders of magnitude increased device lifetime in neutron fields compared to commercial silicon based detectors. Additionally, detector response was found to be linear up to thermal neutron fluxes of 2000 n/sub th//cm/sup 2//s. However, degradation in the charge collection efficiency due to neutron damage-induced defects prevented self-biased operation after exposures above /spl sim/5.7/spl times/10/sup 16/ n/sub th//cm/sup 2/. A carrier removal rate of 9.7/spl plusmn/0.7 cm/sup -1/ was calculated from C-V doping profile measurements on neutron irradiated samples. These results demonstrate the viability of SiC-based detectors for a variety of radiation monitoring applications.

Journal ArticleDOI
N. Akil1, S.E. Kerns1, D.V. Kerns1, A. Hoffmann, Jean-Pierre Charles 
TL;DR: In this paper, a multimechanism model fitting measured spectra and spectra measured by other researchers is presented and justified, and the success of the model indicates that indirect recombination of electrons and holes is the dominant emission mechanism below the light intensity peak (/spl sim/1.8-2.0 eV), that indirect intraband recombination dominates at intermediate energies up to /spl sim 2.3 eV, and that direct interband recombination between high-field populations of carriers near k=0 dominates above 2.4-3.4 eV
Abstract: Light emission from three device types ((1) commercial silicon JFETs, (2) bipolar transistors, and (3) a custom diode) with p-n junctions biased in controlled avalanche breakdown, has been measured over the photon energy range 1.4-3.4 eV, Previously published models are compared with these data to elucidate the mechanisms responsible for avalanche light emission in silicon. A multimechanism model fitting measured spectra and spectra measured by other researchers is presented and justified. The success of the model indicates that indirect recombination of electrons and holes is the dominant emission mechanism below the light intensity peak (/spl sim/1.8-2.0 eV), that indirect intraband recombination dominates at intermediate energies up to /spl sim/2.3 eV, and that direct interband recombination between high-field populations of carriers near k=0 dominates above /spl sim/2.3 eV. For junctions with overlayer passivation, an interference model must be applied to model measured spectra.

Journal ArticleDOI
TL;DR: In this paper, the main drivers have been improved electrical and optical design of the cells, including improved passivation of contact and surface regions, reduced reflection and improved trapping of light within the cell.
Abstract: Although it has been close to 60 years since the first operational silicon solar cell was demonstrated, the last 15 years have seen large improvements in the technology, with the best confirmed cell efficiency improved by over 50 %. The main drivers have been improved electrical and optical design of the cells. Improvements in the former area include improved passivation of contact and surface regions of the cells and a reduction in the volume of heavily doped material within the cell. Optically, reduced reflection and improved trapping of light within the cell have had a large impact. Such features have increased silicon cell efficiency to a recently confirmed value of 24.7%. Over recent years, good progress has been made in transferring some of the corresponding design improvements into commercial product with commercial cells of 17-18% efficiency now commercially available, record values of a mere 15 years ago. The theory supporting these improvements in bulk cell efficiency shows that thin layers of silicon, only a micron or so in thickness, should be capable of comparably high efficiency.