Showing papers in "IEEE Transactions on Electron Devices in 2002"
TL;DR: In this paper, the physics of charge control, source velocity saturation due to thermal injection, and scattering in ultrasmall MOSFETs are examined. And the results show that the essential physics of nanoscale MOSFLETs can be understood in terms of a conceptually simple scattering model.
Abstract: The device physics of nanoscale MOSFETs is explored by numerical simulations of a model transistor. The physics of charge control, source velocity saturation due to thermal injection, and scattering in ultrasmall devices are examined. The results show that the essential physics of nanoscale MOSFETs can be understood in terms of a conceptually simple scattering model.
536 citations
TL;DR: In this article, the design principles and fabrication process of metal nanocrystal memories are described, and one-dimensional (1-D) analyses are provided to illustrate the concept of work function engineering, both in direct tunneling and F-Ntunneling regimes.
Abstract: This paper describes the design principles and fabrication process of metal nanocrystal memories. The advantages of metal nanocrystals over their semiconductor counterparts include higher density of states, stronger coupling with the channel, better size scalability, and the design freedom of engineering the work functions to optimize device characteristics. One-dimensional (1-D) analyses are provided to illustrate the concept of work function engineering, both in direct-tunneling and F-N-tunneling regimes. A self-assembled nanocrystal formation process by rapid thermal annealing of ultrathin metal film deposited on top of gate oxide is developed and integrated with NMOSFET to fabricate such devices.
524 citations
TL;DR: In this paper, the authors describe computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices.
Abstract: This paper describes computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced. The Pi-gate device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. The simulation results indicate that the the Pi-gate device is a very promising candidate for future nanometer MOSFET applications.
477 citations
TL;DR: In this article, the authors review the evolution of SiC power MOSFETs between 1992 and the present, discuss the current status of device development, identify the critical fabrication issues, and assess the prospects for continued progress and eventual commercialization.
Abstract: SiC electronic device technology has made rapid progress during the past decade In this paper, we review the evolution of SiC power MOSFETs between 1992 and the present, discuss the current status of device development, identify the critical fabrication issues, and assess the prospects for continued progress and eventual commercialization
438 citations
TL;DR: In this paper, a methodology is developed to calculate the repeater size and interconnect length which minimizes the total interconnect power dissipation for any given delay penalty, and this methodology is used to calculate power-optimal buffering schemes for various ITRS technology nodes for 5% delay penalty.
Abstract: This paper addresses the problem of power dissipation during the buffer insertion phase of interconnect performance optimization. It is shown that the interconnect delay is actually very shallow with respect to both the repeater size and separation close to the minimum point. A methodology is developed to calculate the repeater size and interconnect length which minimizes the total interconnect power dissipation for any given delay penalty. This methodology is used to calculate the power-optimal buffering schemes for various ITRS technology nodes for 5% delay penalty. Furthermore, this methodology is also used to quantify the relative importance of the various components of the power dissipation for power-optimal solutions for various technology nodes.
328 citations
TL;DR: In this article, the authors investigated the design of the FinFET by 3D simulation and analytical modeling, and derived the threshold voltage (V/sub th/) rolloff and the subthreshold swing (S) by considering the source barrier changes in the most leaky channel path.
Abstract: Design considerations of the FinFET have been investigated by three-dimensional (3-D) simulation and analytical modeling in this paper. Short-channel effects (SCE) of the FinFET can be reasonably controlled by reducing either silicon fin height or fin thickness. Analytical solution of 3-D Laplace's equation is employed to establish the design equations for the subthreshold behavior in the fully depleted silicon fins. Based on the 3-D analytical electrostatic potential in the subthreshold region, the threshold voltage (V/sub th/) roll-off and the subthreshold swing (S) are estimated by considering the source barrier changes in the most leaky channel path. V/sub th/ roll-off is an exponential function of the ratio of effective channel length to drain potential decay length, which can then be expressed as a function of the fin thickness, the fin height and the gate oxide thickness. The drain-potential decay lengths of single-gate fully depleted SOI MOSFET (FDFET), double-gate MOSFET (DGFET), rectangular surrounding-gate MOSFET (SGFET), and FinFET are compared. The drain potential scaling length and V/sub th/ roll-off can be included into a universal relation for convenient comparison.
297 citations
TL;DR: In this article, a spacer patterning technology using a sacrificial layer and a chemical vapor deposition (CVD) spacer layer has been developed, and is demonstrated to achieve sub-7 nm structures with conventional dry etching.
Abstract: A spacer patterning technology using a sacrificial layer and a chemical vapor deposition (CVD) spacer layer has been developed, and is demonstrated to achieve sub-7 nm structures with conventional dry etching. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this technology yields critical dimension (CD) variations of minimum-sized features much smaller than that achieved by optical or e-beam lithography. In addition, it also provides a doubling of device density for a given lithography pitch. This method is used to pattern silicon fins for double-gate metal-oxide semiconductor field effect transistors (MOSFETs) (FinFETs) and gate electrode structures for ultrathin body MOSFETs. Process details are presented.
281 citations
TL;DR: In this article, a compact physics-based quantum effects model for symmetrical double-gate (DG) MOSFETs of arbitrary Si-film thickness is developed and demonstrated.
Abstract: A compact physics-based quantum-effects model for symmetrical double-gate (DG) MOSFETs of arbitrary Si-film thickness is developed and demonstrated. The model, based on the quantum-mechanical variational approach, not only accounts for the thin Si-film thickness dependence but also takes into account the gate-gate charge coupling and the electric field dependence; it can be used for FDSOI MOSFETs as well. The analytical solutions, verified via results obtained from self-consistent numerical solutions of the Poisson and Schrodinger equations, provide good physical insight with regard to the quantization and volume inversion due to carrier confinement, which is governed by the Si-film thickness and/or the transverse electric field. A design criterion for achieving beneficial volume-inversion operation in DG devices is quantitatively defined for the first time. Furthermore, the utility of the model for aiding optimal DG device design, including exploitation of the volume-inversion benefit to carrier mobility, is exemplified.
237 citations
TL;DR: In this article, a realistic assessment of future interconnect performance is addressed, specifically, by modeling copper wire effective resistivity in the light of technological and reliability constraints, and detailed implications of the effect of resistivity trends on performance are addressed in the second part.
Abstract: A realistic assessment of future interconnect performance is addressed, specifically, by modeling copper (Cu) wire effective resistivity in the light of technological and reliability constraints. The scaling-induced rise in resistance in the future may be significantly exacerbated due to an increase in Cu resistivity itself, through both electron surface scattering and the diffusion barrier effect. The impact of these effects on resistivity is modeled under various technological conditions and constraints. These constraints include the interconnect operation temperature, the effect of copper-diffusion barrier thickness and its deposition technology, and the quality of the interconnect/barrier interface. Reliable effective resistivity trends are established at various tiers of interconnects, namely, at the local, semiglobal, and global levels. Detailed implications of the effect of resistivity trends on performance are addressed in the second part of this work.
235 citations
TL;DR: In this paper, the design, fabrication, and characterization of a 130 A Schottky diode, 4.9 kV 4H-SiC SiC PiN diode and 8.6 kV SiC power diodes are described in detail.
Abstract: The present state of SiC power Schottky and PiN diodes are presented in this paper. The design, fabrication, and characterization of a 130 A Schottky diode, 4.9 kV Schottky diode, and an 8.6 kV 4H-SiC PiN diode, which are considered to be significant milestones in the development of high power SiC diodes, are described in detail. Design guidelines and practical issues for the realization of high-power SiC Schottky and PiN diodes are also presented. Experimental results on edge termination techniques applied to newly developed, extremely thick (e.g., 85 and 100 /spl mu/m) 4H-SiC epitaxial layers show promising results. Switching and high-temperature measurements prove that SiC power diodes offer extremely low loss alternatives to conventional technologies and show the promise of demonstrating efficient power circuits. At sufficiently high on-state current densities, the on-state voltage drop of Schottky and PiN diodes have been shown to be comparable to those offered by conventional technologies.
226 citations
TL;DR: In this paper, the intrinsic threshold voltage fluctuations induced by local oxide thickness variations (OTVs) in deep submicrometer (decanano) MOSFETs are studied using three-dimensional numerical simulations on a statistical scale.
Abstract: Intrinsic threshold voltage fluctuations introduced by local oxide thickness variations (OTVs) in deep submicrometer (decanano) MOSFETs are studied using three-dimensional (3-D) numerical simulations on a statistical scale. Quantum mechanical effects are included in the simulations employing the density gradient (DG) formalism. The random Si/SiO/sub 2/ and gate/SiO/sub 2/ interfaces are generated from a power spectrum corresponding to the autocorrelation function of the interface roughness. The impact on the intrinsic threshold voltage fluctuations of both the parameters used to reconstruct the random interface and the MOSFET design parameters are studied using carefully designed simulation experiments. The simulations show that intrinsic threshold voltage fluctuations induced by local OTV become significant when the dimensions of the devices become comparable to the correlation length of the interface. In MOSFETs with characteristic dimensions below 30 nm and conventional architecture, they are comparable to the threshold voltage fluctuations introduced by random discrete dopants.
TL;DR: In this article, the electrical characteristics of the metal nanocrystal memory devices continued from the previous paper, and the concern of the possible metal contamination was also addressed by currentvoltage (I-V) and capacitance-voltage characterizations.
Abstract: This paper describes the electrical characteristics of the metal nanocrystal memory devices continued from the previous paper [see ibid., vol. 49, p. 1606-13, Sept. 2002]. Devices with Au, Ag, and Pt nanocrystals working in the F-N tunneling regime have been investigated and compared with Si nanocrystal memory devices. With hot-carrier injection such as the programming mechanism, retention time up to 10/sup 6/ s has been observed and 2-bit-per-cell storage capability has been demonstrated and analyzed. The concern of the possible metal contamination is also addressed by current-voltage (I-V) and capacitance-voltage (C-V) characterizations. The extracted inversion layer mobility and minority carrier lifetime suggest that the substrate is free from metal contamination with continuous operations.
TL;DR: In this article, the authors investigated self-heating effects and temperature rise in AlGaN/GaN HEMTs grown on silicon and sapphire substrates, exploiting transistor DC characterization methods.
Abstract: Self-heating effects and temperature rise in AlGaN/GaN HEMTs grown on silicon and sapphire substrates are studied, exploiting transistor DC characterization methods A negative differential output resistance is observed for high dissipated power levels An analytical formula for a source-drain current drop as a function of parasitic source resistance and threshold voltage changes is proposed to explain this behavior The transistor source resistance and threshold voltage is determined experimentally at different elevated temperatures to construct channel temperature versus dissipated power transfer characteristic It is found that the HEMT channel temperature increases rapidly with dissipated power and at 6 W/mm reaches values of /spl sim/320/spl deg/C for sapphire and /spl sim/95/spl deg/C for silicon substrate, respectively
TL;DR: In this article, a general analytical subthreshold swing model for symmetric DG MOSFETs was derived using evanescent-mode analysis through a concept of effective conducting path, which explains a unique doping concentration (N/sub A/) dependence of S, providing a unified understanding of previous S models and leading to a new improved S model.
Abstract: A general analytical subthreshold swing (S) model for symmetric DG MOSFETs is derived using evanescent-mode analysis. Through a concept of effective conducting path, it explains a unique doping concentration (N/sub A/) dependence of S, providing a unified understanding of previous S models and leading to a new improved S model for undoped DG MOSFETs. Compact, explicit expressions of a scale length are derived, which expedite projections of scalability of DG MOSFETs and its requirement.
TL;DR: An analytically compact model for the double-gate metal-oxide semiconductor field effect transistor (MOSFET) based on McKelvey's flux theory is developed in this article.
Abstract: An analytically compact model for the nanoscale double gate metal-oxide semiconductor field effect transistor (MOSFET) based on McKelvey's flux theory is developed. The model is continuous above and below threshold and from the linear to saturation regions. Most importantly, it describes nanoscale MOSFETs from the diffusive to ballistic regimes. In addition to its use in exploring the limits and circuit applications of double gate MOSFETs, the model also serves as an example of how semiclassical scattering theory can be used to develop physically sound models for nanoscale transistors.
TL;DR: In this paper, an equivalent circuit describing the gate current in an nFET after hard gate-oxide breakdown is proposed, where the breakdown path is modeled as a narrow inclusion of highly doped n-type silicon.
Abstract: Dissimilar post-hard-breakdown nMOSFET characteristics are consistently explained by the location of a constant-size breakdown path. Device simulations with the breakdown path modeled as a narrow inclusion of highly doped n-type silicon well reproduce all postbreakdown nFET characteristics, including the substrate current behavior, for both gate-to-substrate and gate-to-extension breakdowns. An equivalent circuit describing the gate current in an nFET after hard gate-oxide breakdown is proposed.
TL;DR: In this paper, the Schottky barrier MOSFETs are explored by solving the two-dimensional Poisson equation self-consistently with a quantum transport equation, and the results show that with positive, effective metal-semiconductor barrier heights, the on-current is limited by tunneling through a barrier at the source.
Abstract: Nanoscale Schottky barrier MOSFETs (SBFETs) are explored by solving the two-dimensional Poisson equation self-consistently with a quantum transport equation. The results show that for SBFETs; with positive, effective metal-semiconductor barrier heights, the on-current is limited by tunneling through a barrier at the source. If, however, a negative metal-semiconductor barrier height could be achieved, on-current of SBFETs would approach that of a ballistic MOSFET. The reason is that the gate voltage would then modulate a thermionic barrier rather than a tunneling barrier, a process similar to ballistic MOSFETs and one that delivers more current.
TL;DR: In this article, a new channel noise model using the channel length modulation (CLM) effect was proposed to calculate the channel noise of deep submicron MOSFETs.
Abstract: This brief presents a new channel noise model using the channel length modulation (CLM) effect to calculate the channel noise of deep submicron MOSFETs. Based on the new channel noise model, the simulated noise spectral densities of the devices fabricated in a 0.18 /spl mu/m CMOS process as a function of channel length and bias condition are compared to the channel noise directly extracted from RF noise measurements. In addition, the hot electron effect and the noise contributed from the velocity saturation region are discussed.
TL;DR: In this article, a simple design technique that allows the fabrication of UV/blue-selective avalanche photodiodes in a conventional CMOS process is presented, which achieves a very low dark current of only 400 pA/mm/sup 2/, an excess noise factor F=7 at /spl lambda/=400 nm and a good gain uniformity.
Abstract: We present a simple design technique that allows the fabrication of UV/blue-selective avalanche photodiodes in a conventional CMOS process. The photodiodes are fabricated in a twin tub 0.8 /spl mu/m CMOS technology. An efficient guard-ring structure is created using the lateral diffusion of two n-well regions separated by a gap of 0.6 /spl mu/m. When operated at a multiplication gain of 20, our photodiodes achieve a very low dark current of only 400 pA/mm/sup 2/, an excess noise factor F=7 at /spl lambda/=400 nm and a good gain uniformity. At zero bias voltage, the responsivity peaks at /spl lambda/=470 nm, with 180 mA/W. It corresponds to a 50% quantum efficiency. Successive process steps are simulated to provide a comprehensive understanding of this technique.
TL;DR: In this article, the present understanding of wear-out and breakdown in ultrathin (t/sub ox/ < 5.0 nm) SiO/sub 2/ gate dielectric films and issues relating to reliability projection are reviewed.
Abstract: The present understanding of wear-out and breakdown in ultrathin (t/sub ox/ < 5.0 nm) SiO/sub 2/ gate dielectric films and issues relating to reliability projection are reviewed in this article. Recent evidence supporting a voltage-driven model for defect generation and breakdown, where energetic tunneling electrons induce defect generation and breakdown will be discussed. The concept of a critical number of defects required to cause breakdown and percolation theory will be used to describe the observed statistical failure distributions for ultrathin gate dielectric breakdown. Recent observations of a voltage dependent voltage acceleration parameter and non-Arrhenius temperature dependence will be presented. The current understanding of soft breakdown will be discussed and proposed techniques for detecting breakdown presented. Finally, the implications of soft breakdown on circuit functionality and the applicability of applying current reliability characterization and analysis techniques to project the reliability of future alternative gate dielectrics will be discussed.
TL;DR: In this paper, three different experimental techniques to measure Weibull slopes are described and compared in terms of their advantages and disadvantages, and a comparison of these three methods are given.
Abstract: Critically examined several important aspects concerning the experimental determination of Weibull shape factors (slopes). Statistical characteristics of breakdown distribution such as area scaling property and the extreme-value distribution are reviewed. We discuss the experimental measurement methodology of time-to-breakdown (T/sub BD/) or charge-to-charge (Q/sub BD/) distributions with the emphasis on the accuracy. The influence of sample numbers on the estimation of Weibull distribution parameters such as characteristic T/sub BD/ and Weibull slopes are investigated in the context of confidence limits. Some examples of the measurement fallacy on Weibull slopes are given. Three different experimental techniques to measure Weibull slopes are described and compared in terms of their advantages and disadvantages. Finally, we will give a comparison of these three methods. Having established these fundamental aspects of the Weibull slope measurements, we will present our extensive experimental data on thickness, voltage, temperature, and polarity dependence of Weibull slopes in part II.
TL;DR: In this article, a numerical analysis of the electrical characteristics for the ferroelectric memory field-effect transistors (FeMFETs) is presented, and a new analytic expression for the relation of polarization versus electric field (P-E) is proposed to describe the nonsaturated hysteresis loop of the material.
Abstract: A numerical analysis of the electrical characteristics for the ferroelectric memory field-effect transistors (FeMFETs) is presented. Two important structures such as the metal-ferroelectric-insulator-semiconductor field-effect transistor (MFISFET) and metal-ferroelectric-metal-insulator-semiconductor field-effect transistor (MFMISFET) are considered. A new analytic expression for the relation of polarization versus electric field (P-E) is proposed to describe the nonsaturated hysteresis loop of the ferroelectric material. In order to provide a more accurate simulation, we incorporate the combined effects of the nonsaturated polarization of ferroelectric layers and the nonuniform distributions of electric field and charge along the channel. We also discuss the possible nonideal effects due to the fixed charges, charge injection, and short channel. The present theoretical work provides some new design rules for improving the performance of FeMFETs.
TL;DR: In this paper, a photonic high-frequency capacitance-voltage (HF C-V) response of metal-oxide semiconductor (MOS) capacitors is reported for the analysis of interface states in MOS systems.
Abstract: A new characterization method based on the photonic high-frequency capacitance-voltage (HF C-V) response of metal-oxide semiconductor (MOS) capacitors is reported for the analysis of interface states in MOS systems. An optical source with a photon energy less than the silicon band-gap (h/spl nu/ = 0.799 eV < E/sub g/ = 1.11 eV) is employed for the photonic characterization of interface states (Bit) distributed in the photoresponsive energy band (E/sub c/ h/spl nu/ < E/sub it/ < E/sub c/) in NMOS capacitors with a polysilicon gate. Assuming a uniform distribution of the trap levels, the density of interface states (D/sub it/) was observed to be D/sub it/ 1-5 /spl times/ 10/sup 11/ eV/sup -1/ cm/sup -2/ in the photoresponsive energy band.
TL;DR: In this paper, a polycrystalline-silicon transistor (poly-Si TFT) backplane for liquid crystal displays (LCDs) with integrated drivers was fabricated using a low-temperature process (below 425/spl deg/C).
Abstract: In order to realize electronic devices on plastic film, new technology has been developed that enables the transfer of thin-film devices from an original substrate to another substrate by using laser irradiation. This technology was termed SUFTLA, which stands for surface-free technology by laser annealing. A polycrystalline-silicon thin film transistor (poly-Si TFT) back-plane for liquid crystal displays (LCDs) with integrated drivers was fabricated using a low-temperature process (below 425/spl deg/C) and could be successfully transferred from a glass or quartz substrate to plastic film using this technology. This technology enabled us to fabricate an all-plastic substrate TFT-LCD having a display area of 0.7 in measured diagonally and a pixel count of 428/spl times/238. In addition, the operation of the integrated drivers and the displayed image could be confirmed for the first time in the world.
TL;DR: In this paper, the authors extended the realistic resistance modeling of on-chip copper interconnects to assess its impact on key interconnect performance metrics, including wire delay and power penalty arising from repeater insertion.
Abstract: For pt. I see ibid., vol.49, no.4, pp.590-7 (2002). This work extends the realistic resistance modeling of on-chip copper interconnects to assess its impact on key interconnect performance metrics. As quantified in part I of this work, the effective resistivity of copper is not only significantly larger than its ideal, bulk value but also highly dependent on technology and reliability constraints. Performance is quantified under various technological conditions in the future. In particular, wire delay is extensively addressed. Further, the impact of optimal repeater insertion to improve these parameters is also studied using realistic resistance trends. The impact of technologically constrained resistance on power penalty arising from repeater insertion is briefly addressed. Where relevant, aforementioned results are contrasted with those obtained using ideal copper resistivity.
TL;DR: In this paper, an experimental investigation on high-temperature carrier mobility in bulk silicon is carried out with the aim of improving qualitative and quantitative understanding of carrier transport under ESD events.
Abstract: In this paper, an experimental investigation on high-temperature carrier mobility in bulk silicon is carried out with the aim of improving our qualitative and quantitative understanding of carrier transport under ESD events. Circular van der Pauw patterns, suitable for resistivity and Hall measurements, were designed and manufactured using both the n and p layers made available by the BCD-3 smart-power technology. The previous measurements were carried out using a special measurement setup that allows operating temperatures in excess of 400/spl deg/C to be reached within the polar expansions of a commercial magnet. A novel extraction methodology that allows for the determination of the Hall factor and drift mobility against impurity concentration and lattice temperature has been developed. Also, a compact mobility model suitable for implementation in device simulators is worked out and implemented in the DESSIS/spl copy/ code. Comparisons with the mobility models by G. Masetti et al. (1983) and D.B.M. Klaassen (1992) are shown in the temperature range between 25 and 400/spl deg/C.
TL;DR: In this paper, the authors present experimental evidence on the voltage-dependence of voltage acceleration factors observed on ultrathin oxides from 5 nm down to /spl sim/1 nm over a wide range of voltages.
Abstract: In this paper, we present experimental evidence on the voltage-dependence of the voltage acceleration factors observed on ultrathin oxides from 5 nm down to /spl sim/1 nm over a wide range of voltages from /spl sim/2 V to 6 V. Two independent experimental approaches, area scaling method and long-term stress, are used to investigate this phenomenon. We show the exponential law with a constant voltage-acceleration factor violates the widely accepted fundamental breakdown property of Poisson random statistics while the voltage-dependent voltage acceleration described by an empirical power-law relation preserves this well-known property. The apparent thickness-dependence of voltage acceleration factors measured in different voltage ranges can be nicely understood and unified with these independent experimental results in the scenario of a voltage-driven breakdown. In the framework of the critical defect density and defect generation rate for charge-to-breakdown, we explore the possible explanation of increasing voltage acceleration factors at reduced voltage by assuming a geometric model for the critical defect density.
TL;DR: In this paper, the impact of energy quantization on gate tunneling current was studied for double-gate and ultrathin body MOSFETs, and the effects of body thickness scaling and channel crystallographic orientation were studied.
Abstract: The impact of energy quantization on gate tunneling current is studied for double-gate and ultrathin body MOSFETs. Reduced vertical electric field and quantum confinement in the channel of these thin-body devices causes a decrease in gate leakage by as much as an order of magnitude. The effects of body thickness scaling and channel crystallographic orientation are studied. The impact of threshold voltage control solutions, including doped channel and asymmetric double-gate structures is also investigated. Future gate dielectric thickness scaling and the use of high-/spl kappa/ gate dielectrics are discussed.
TL;DR: In this paper, the drift-diffusion model was used to illustrate the operation of the quantum dot intermediate band solar cell (QD-IBSC) and its validity limits, and conditions in which the contribution of the electron and hole drift currents is small when compared to the total current were discussed.
Abstract: This paper describes the application of the drift-diffusion model in order to illustrate the operation of the quantum dot intermediate band solar cell (QD-IBSC) and its validity limits. The main particularities of the model arise from the fact that the intermediate band solar cell (IBSC) is a two-minority carrier device. The role of the current transport in the IB is discussed, providing the beneficial conditions in which this current approaches zero. The electric field is also related to the current density in the intermediate band. The conditions in which the contribution of the electron and hole drift currents is small when compared to the total current are discussed. The description of the operation of the cell is aided by means of a numerical example.
TL;DR: In this article, an integrated multi-transducer capacitive barometric pressure sensor that is vacuum-sealed at wafer level is presented. But the interface circuitry is integrated directly within the sealed reference cavity, making the device immune to parasitic environmental effects.
Abstract: This paper presents an integrated multi-transducer capacitive barometric pressure sensor that is vacuum-sealed at wafer level. The interface circuitry is integrated directly within the sealed reference cavity, making the device immune to parasitic environmental effects. The overall device process merges CMOS circuitry with a dissolved-wafer transducer process and is compatible with bulk- and surface-micromachined transducers. The process employs chemical-mechanical polishing (CMP), anodic bonding, and hermetic lead transfers. The sensor achieves 25 mtorr resolution and is suitable for low-cost packaging. It is composed of a programmable switched-capacitor (SC) readout circuit, five segmented-range pressure transducers, and a reference capacitor, all integrated on a 6.5/spl times/7.5 mm/sup 2/ die using 3 /spl mu/m features.