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Showing papers in "IEEE Transactions on Electron Devices in 2003"


Journal ArticleDOI
TL;DR: In this paper, numerical simulations are used to guide the development of a simple analytical theory for ballistic field-effect transistors, and the model reduces to Natori's theory of the ballistic MOSFET.
Abstract: Numerical simulations are used to guide the development of a simple analytical theory for ballistic field-effect transistors. When two-dimensional (2-D) electrostatic effects are small (and when the insulator capacitance is much less than the semiconductor (quantum) capacitance), the model reduces to Natori's theory of the ballistic MOSFET. The model also treats 2-D electrostatics and the quantum capacitance limit where the semiconductor quantum capacitance is much less than the insulator capacitance. This new model provides insights into the performance of MOSFETs near the scaling limit and a unified framework for assessing and comparing a variety of novel transistors.

740 citations


Journal ArticleDOI
TL;DR: In this paper, the impact of the gate line edge roughness (LER) on the intrinsic parameters fluctuations in deep decananometer (sub 50 nm) gate MOSFETs was investigated.
Abstract: In this paper, we use statistical three-dimensional (3-D) simulations to study the impact of the gate line edge roughness (LER) on the intrinsic parameters fluctuations in deep decananometer (sub 50 nm) gate MOSFETs. The line edge roughness is introduced using a Fourier synthesis technique based on the power spectrum of a Gaussian autocorrelation function. In carefully designed simulation experiments, we investigate the impact of the rms amplitude /spl Delta/ and the correlation length /spl Lambda/ on the intrinsic parameter fluctuations in well scaled, but simple devices with fixed geometry as well as the channel length and width dependence of the fluctuations at fixed LER parameters. For the first time, we superimpose in the simulations LER and random discrete dopants and investigate their relative contribution to the intrinsic parameter fluctuations in the investigated devices. For particular MOSFET geometries, we were able to identify the regions where each of these two sources of intrinsic parameter fluctuations dominates.

612 citations


Journal ArticleDOI
TL;DR: In this paper, a review of the analytical and numerical simulation techniques used to study and predict intrinsic parameters fluctuations is presented, and the future challenges that have to be addressed in order to improve the accuracy and the predictive power of the intrinsic fluctuation simulations are also discussed.
Abstract: Intrinsic parameter fluctuations introduced by discreteness of charge and matter will play an increasingly important role when semiconductor devices are scaled to decananometer and nanometer dimensions in next-generation integrated circuits and systems. In this paper, we review the analytical and the numerical simulation techniques used to study and predict such intrinsic parameters fluctuations. We consider random discrete dopants, trapped charges, atomic-scale interface roughness, and line edge roughness as sources of intrinsic parameter fluctuations. The presented theoretical approach based on Green's functions is restricted to the case of random discrete charges. The numerical simulation approaches based on the drift diffusion approximation with density gradient quantum corrections covers all of the listed sources of fluctuations. The results show that the intrinsic fluctuations in conventional MOSFETs, and later in double gate architectures, will reach levels that will affect the yield and the functionality of the next generation analog and digital circuits unless appropriate changes to the design are made. The future challenges that have to be addressed in order to improve the accuracy and the predictive power of the intrinsic fluctuation simulations are also discussed.

579 citations


Journal ArticleDOI
TL;DR: AlGaN-GaN power high-electron mobility transistors (HEMTs) with 600-V breakdown voltage are fabricated and demonstrated as switching power devices for motor drive and power supply applications.
Abstract: AlGaN-GaN power high-electron mobility transistors (HEMTs) with 600-V breakdown voltage are fabricated and demonstrated as switching power devices for motor drive and power supply applications. The fabricated power HEMT realized the high breakdown voltage by optimized field plate technique and the low on-state resistance of 3.3 m/spl Omega/cm/sup 2/, which is 20 times lower than that or silicon MOSFETs, thanks to the high critical field of GaN material and the high mobility in 2DEG channel. The fabricated devices also demonstrated the high current density switching of 850 A/cm/sup 2/ turn-off. These results show that AlGaN-GaN power-HEMTs are one of the most promising candidates for future switching power device for power electronics applications.

409 citations


Journal ArticleDOI
TL;DR: In this paper, a nonquasi-static channel segmentation model was proposed to predict both drain and gate current noise in 0.18-/spl mu/m CMOS technology.
Abstract: The RF noise in 0.18-/spl mu/m CMOS technology has been measured and modeled. In contrast to some other groups, we find only a moderate enhancement of the drain current noise for short-channel MOSFETs. The gate current noise on the other hand is more significantly enhanced, which is explained by the effects of the gate resistance. The experimental results are modeled with a nonquasi-static RF model, based on channel segmentation, which is capable of predicting both drain and gate current noise accurately. Experimental evidence is shown for two additional noise mechanisms: 1) avalanche noise associated with the avalanche current from drain to bulk and 2) shot noise in the direct-tunneling gate leakage current. Additionally, we show low-frequency noise measurements, which strongly point toward an explanation of the 1/f noise based on carrier trapping, not only in n-channel MOSFETs, but also in p-channel MOSFETs.

375 citations


Journal ArticleDOI
TL;DR: In this paper, the authors investigated the noise introduced by the electron multiplication within the EMCCD and showed that the noise performance matches that of the ideal staircase avalanche photodiode, and a Monte Carlo method for simulating the low-light level images was demonstrated.
Abstract: Electron multiplying charge-coupled devices (EMCCDs) enable imaging with subelectron noise up to video frame rates and beyond, providing the multiplication gain is sufficiently high. The ultra-low noise, high resolution, high-quantum efficiency, and robustness to over exposure make these sensors ideally suited to applications traditionally served by image intensifiers. One important performance parameter of such low-light imaging systems is the noise introduced by the gain process. This work investigates the noise introduced by the electron multiplication within the EMCCD. The theory and measurements of the excess noise factor are presented. The measurement technique for determining the excess noise factor is described in detail. The results show that the noise performance matches that of the ideal staircase avalanche photodiode. A Monte Carlo method for simulating the low-light level images is demonstrated and the results compared with practical experience.

366 citations


Journal ArticleDOI
TL;DR: In this article, a review of design principles for implementation of a spiral inductor in a silicon integrated circuit fabrication process summarizes prior art in this field, and a fast and physics-based inductor model is exploited to put the results contributed by many different groups in various technologies and achieved over the past eight years into perspective.
Abstract: This review of design principles for implementation of a spiral inductor in a silicon integrated circuit fabrication process summarizes prior art in this field. In addition, a fast and physics-based inductor model is exploited to put the results contributed by many different groups in various technologies and achieved over the past eight years into perspective. Inductors are compared not only by their maximum quality factors (Q/sub max/), but also by taking the frequency at Q/sub max/, the inductance value (L), the self-resonance frequency (f/sub SR/), and the coil area into account. It is further explained that the spiral coil structure on a lossy silicon substrate can operate in three different modes, depending at first order on the silicon doping concentration. Ranging from high to low substrate resistivity, inductor-mode, resonator-mode, and eddy-current regimes are defined by characteristic changes of Q/sub max/, L, and f/sub SR/. The advantages and disadvantages of patterned or blanket resistive ground shields between the inductor coil and substrate and the effect of a substrate contact on the inductor are also addressed in this paper. Exploring optimum inductor designs under various constraints leverages the speed of the model. Finally, in view of the continuously increasing operating frequencies in advancing to new generations of RF systems, the range of feasible inductance values for given quality factors are predicted on the basis of optimum technological features.

320 citations


Journal ArticleDOI
Joe W. McPherson1, Jinyoung Kim1, A. Shanware1, Homi C. Mogul1, J. Rodriguez1 
TL;DR: In this paper, a thermochemical description of the ultimate breakdown strength of high-k dielectrics suggests that E/sub bd/ should reduce approximately as (k)/sup -1/2/ over a wide range of dielectric materials while the field-acceleration parameter /spl gamma/ should increase in similar but inverse manner.
Abstract: The ultimate breakdown strength E/sub bd/ of a dielectric material is found to decrease as the dielectric-constant k increases. A thermochemical description of the ultimate breakdown strength of high-k dielectrics suggests that E/sub bd/ should reduce approximately as (k)/sup -1/2/ over a wide range of dielectric materials while the field-acceleration parameter /spl gamma/ should increase in similar but inverse manner. New time-dependent dielectric breakdown (TDDB) data are presented over a wide range of dielectric materials and E/sub bd/ was found to decrease as (k)/sup -0.65/ while /spl gamma/ increases as (k)/sup 0.66/. The good agreement between thermochemical theory and high-k TDDB observations suggests that the very high local electric field (Lorentz-relation/Mossotti-field) in high-k dielectrics tends to distort/weaken the polar molecular bonds making them more susceptible to bond breakage by standard Boltzmann processes and/or by hole-capture and thus lowers the breakdown strength.

307 citations


Journal ArticleDOI
TL;DR: In this article, double gate devices based upon the FinFET architecture are fabricated, with gate lengths as small as 30 nm, with particular attention given to minimizing the parasitic series resistance.
Abstract: Double gate devices based upon the FinFET architecture are fabricated, with gate lengths as small as 30 nm. Particular attention is given to minimizing the parasitic series resistance. Angled extension implants and selective silicon epitaxy are investigated as methods for minimizing parasitic resistance in FinFETs. Using these two techniques high performance devices are fabricated with on-currents comparable to fully optimized bulk silicon technologies. The influence of fin thickness on device resistance and short channel effects is discussed in detail. Devices are fabricated with fins oriented in the and directions showing different transport properties.

285 citations


Journal ArticleDOI
TL;DR: In this paper, a program to numerically simulate quantum transport in double gate metal oxide semiconductor field effect transistors (MOSFETs) is described, using a Green's function approach and a simple treatment of scattering based on the idea of so-called Buttiker probes.
Abstract: A program to numerically simulate quantum transport in double gate metal oxide semiconductor field effect transistors (MOSFETs) is described. The program uses a Green's function approach and a simple treatment of scattering based on the idea of so-called Buttiker probes. The double gate device geometry permits an efficient mode space approach that dramatically lowers the computational burden and permits use as a design tool. Also implemented for comparison are a ballistic solution of the Boltzmann transport equation and the drift-diffusion approaches. The program is described and some examples of the use of nanoMOS for 10 nm double gate MOSFETs are presented.

283 citations


Journal ArticleDOI
TL;DR: In this paper, the authors present an ab initio analysis of a simple molecular system, which acts as a clocked molecular QCA cell, and show how clocked control of the molecular cellular automata can be accomplished with a local electric field.
Abstract: Quantum-dot cellular automata (QCA) is an approach to computing that eliminates the need for current switches by representing binary information as the configuration of charge among quantum dots. For molecular QCA, redox sites of molecules serve as the quantum dots. The Coulomb interaction between neighboring molecules provides device-device coupling. By introducing clocked control of the QCA cell, power gain, reduced power dissipation, and computational pipelining can be achieved. We present an ab initio analysis of a simple molecular system, which acts as a clocked molecular QCA cell. The intrinsic bistability of the molecular charge configuration results in dipole or quadrupole fields that couple strongly to the state of neighboring molecules. We show how clocked control of the molecular QCA can be accomplished with a local electric field.

Journal ArticleDOI
TL;DR: In this article, a charge-coupled device (CCD) was fabricated on high resistivity, n-type silicon, which allows for depletion depths of several hundred micrometers.
Abstract: Charge-coupled devices (CCDs) have been fabricated on high-resistivity, n-type silicon. The resistivity, on the order of 10 000 /spl Omega//spl middot/cm, allows for depletion depths of several hundred micrometers. Fully depleted, back-illuminated operation is achieved by the application of a bias voltage to an ohmic contact on the wafer back side consisting of a thin in situ doped polycrystalline silicon layer capped by indium tin oxide and silicon dioxide. This thin contact allows for a good short-wavelength response, while the relatively large depleted thickness results in a good near-infrared response.

Journal ArticleDOI
TL;DR: In this article, the amplitudes of random telegraph signals associated with the trapping of a single electron in defect states at the Si/SiO/sub 2/ interface of sub-100-nm (decananometer) MOSFETs employing three-dimensional (3-D) "atomistic" simulations are considered in the simulations.
Abstract: In this paper we study the amplitudes of random telegraph signals (RTS) associated with the trapping of a single electron in defect states at the Si/SiO/sub 2/ interface of sub-100-nm (decananometer) MOSFETs employing three-dimensional (3-D) "atomistic" simulations. Both continuous doping charge and random discrete dopants in the active region of the MOSFETs are considered in the simulations. The dependence of the RTS amplitudes on the position of the trapped charge in the channel and on device design parameters such as dimensions, oxide thickness and channel doping concentration is studied in detail. The 3-D simulations offer a natural explanation for the large variation in the RTS amplitudes measured experimentally in otherwise identical MOSFETs. The random discrete dopant simulations result in RTS amplitudes several times higher compared to continuous charge simulations. They also produce closer to the experimentally observed distributions of the RTS amplitudes. The results highlight the significant impact of single charge trapping in the next generation decananometer MOSFETs.

Journal ArticleDOI
TL;DR: In this article, the operation of 1-3 nm thick SOI MOSFETs, in double-gate (DG) mode and single-gate mode (for either front or back channel), is systematically analyzed.
Abstract: The operation of 1-3 nm thick SOI MOSFETs, in double-gate (DG) mode and single-gate (SG) mode (for either front or back channel), is systematically analyzed. Strong interface coupling and threshold voltage variation, a large influence of substrate depletion underneath the buried oxide, the absence of drain current transients, and degradation in electron mobility are typical effects in these ultra-thin MOSFETs. The comparison of SG and DG configurations demonstrates the superiority of DG-MOSFETs: ideal subthreshold swing and remarkably improved transconductance (consistently higher than twice the value in SG-MOSFETs). The experimental data and the difference between SG and DG modes is explained by combining classical models with quantum calculations. The key effect in ultimately thin DG-MOSFETs is volume inversion, which primarily leads to an improvement in mobility, whereas the total inversion charge is only marginally modified.

Journal ArticleDOI
TL;DR: In this article, a compact, physical, short-channel threshold voltage model for undoped symmetric double-gate MOSFETs is derived based on an analytical solution of the two-dimensional (2-D) Poisson equation with the mobile charge term included.
Abstract: A compact, physical, short-channel threshold voltage model for undoped symmetric double-gate MOSFETs has been derived based on an analytical solution of the two-dimensional (2-D) Poisson equation with the mobile charge term included. The new model is verified by published numerical simulations with close agreement. Applying the newly developed model, threshold voltage sensitivities to channel length, channel thickness, and gate oxide thickness have been comprehensively investigated. For practical device designs the channel length causes 30-50% more threshold voltage variation than does the channel thickness for the same process tolerance, while the gate oxide thickness causes the least, relatively insignificant threshold voltage variation. Model predictions indicate that individual DG MOSFETs with good turn-off behavior are feasible at 10 nm scale; however, practical exploitation of these devices toward gigascale integrated systems requires development of novel technologies for significant improvement in process control.

Journal ArticleDOI
TL;DR: In this article, the surface potential changes are caused by electrons which tunnel from the gate under high bias stress and get trapped at the surface states near the gate, which correlates with a large improvement in microwave power performance in these devices after passivation.
Abstract: Very slow drain current and surface potential transients have been observed in AlGaN/GaN heterostructure field effect transistors that are subjected to high bias stress. Simultaneous measurements of drain current and surface potential indicate that large change in surface potential after stress is responsible for the reduction in drain current in these devices. Measurements of surface potential profile from the gate edge toward the drain as a function of time indicate that surface potential changes occur mostly near the gate. It is proposed that the surface potential changes are caused by electrons which tunnel from the gate under high bias stress and get trapped at the surface states near the gate. Passivation of the surface with SiN/sub x/ reduces the transient magnitudes to a large extent. This correlates with a large improvement in microwave power performance in these devices after passivation. UV illumination of these devices totally eliminates the drain current and surface potential transients.

Journal ArticleDOI
TL;DR: In this paper, the authors investigated the manufacturability of 20-nm double-gate and FinFET devices in integrated circuits by projecting process tolerances and quantitatively considered two important factors affecting the sensitivity of device electrical parameters to physical variations.
Abstract: We investigate the manufacturability of 20-nm double-gate and FinFET devices in integrated circuits by projecting process tolerances. Two important factors affecting the sensitivity of device electrical parameters to physical variations were quantitatively considered. The quantum effect was computed using the density gradient method and the sensitivity of threshold voltage to random dopant fluctuation was studied by Monte Carlo simulation. Our results show the 3/spl sigma/ value of V/sub T/ variation caused by discrete impurity fluctuation can be greater than 100%. Thus, engineering the work function of gate materials and maintaining a nearly intrinsic channel is more desirable. Based on a design with an intrinsic channel and ideal gate work function, we analyzed the sensitivity of device electrical parameters to several important physical fluctuations such as the variations in gate length, body thickness, and gate dielectric thickness. We found that quantum effects have great impact on the performance of devices. As a result, the device electrical behavior is sensitive to small variations of body thickness. The effect dominates over the effects produced by other physical fluctuations. To achieve a relative variation of electrical parameters comparable to present practice in industry, we face a challenge of fin width control (less than /spl sim/1 nm 3/spl sigma/ value of variation) for the 20-nm FinFET devices. The constraint of the gate length variation is about 10/spl sim/15%. We estimate a tolerance of 1/spl sim/2 /spl Aring/ 3/spl sigma/ value of oxide thickness variation and up to 30% front-back oxide thickness mismatch.

Journal ArticleDOI
TL;DR: In this paper, the authors investigated the role of the surface states between the gate and drain electrodes in current collapse in AlGaN/GaN HEMTs and showed that the current collapse was caused by the Si/sub 3/N/sub 4/4/ film passivation.
Abstract: Drain current collapse in AlGaN/GaN HEMTs has been studied systematically by applying bias stress to the device. The collapse was suppressed by light illumination with energy smaller than the bandgap. The position dependence of the light illumination and the measurement of series source and drain resistances revealed that the collapse was caused by the surface states between the gate and drain electrodes, which captured electrons injected from the gate. The current collapse was eliminated by the passivation of the device surface with Si/sub 3/N/sub 4/ film.

Journal ArticleDOI
TL;DR: Using an accurate direct-tunneling gate-current model and specifications from the International Technology Roadmap for Semiconductors (ITRS), guidelines for the selection of gate dielectrics to satisfy the projected off-state leakage current requirements of future high-performance and low-power technologies are provided.
Abstract: In this paper, we explore the scaling limits of alternative gate dielectrics based on their direct-tunneling characteristics and gate-leakage requirements for future CMOS technology generations. Important material parameters such as the tunneling effective mass are extracted from the direct-tunneling characteristics of several promising high-/spl kappa/ gate dielectrics for the first time. We also introduce a figure-of-merit for comparing the relative advantages of various gate dielectrics based on the gate-leakage current. Using an accurate direct-tunneling gate-current model and specifications from the International Technology Roadmap for Semiconductors (ITRS), we provide guidelines for the selection of gate dielectrics to satisfy the projected off-state leakage current requirements of future high-performance and low-power technologies.

Journal ArticleDOI
TL;DR: In this paper, the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m.
Abstract: This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).

Journal ArticleDOI
TL;DR: In this article, the influence of scattering along the channel and extension regions of dual-gate nanotransistors was modeled and it was shown that scattering in the drain-end is less detrimental to the drive current than scattering near the source-end of the channel.
Abstract: We model the influence of scattering along the channel and extension regions of dual gate nanotransistors. It is found that the reduction in drain current due to scattering in the right half of the channel is comparable to the reduction in drain current due to scattering in the left half of the channel, when the channel length is comparable to the scattering length. This is in contrast to a popular belief that scattering in the source end of a nanotransistor is significantly more detrimental to the drive current than scattering elsewhere. As the channel length becomes much larger than the scattering length, scattering in the drain-end is less detrimental to the drive current than scattering near the source-end of the channel. Finally, we show that for nanotransistors, the classical picture of modeling the extension regions as simple series resistances is not valid.

Journal ArticleDOI
TL;DR: In this article, a current-mediated amorphous silicon active pixel readout circuit was proposed to reduce the effect of external readout noise sources associated with "off-chip" charge amplifiers.
Abstract: The most widely used architecture in large-area amorphous silicon (a-Si) flat panel imagers is a passive pixel sensor (PPS), which consists of a detector and a readout switch. While the PPS has the advantage of being compact and amenable toward high-resolution imaging, reading small PPS output signals requires external column charge amplifiers that produce additional noise and reduce the minimum readable sensor input signal. This work presents a current-mediated amorphous silicon active pixel readout circuit that performs on-pixel amplification of noise-vulnerable sensor input signals to minimize the effect of external readout noise sources associated with "off-chip" charge amplifiers. Results indicate excellent small-signal linearity along with a high, and programmable, charge gain. In addition, the active pixel circuit shows immunity to shift in threshold voltage that is characteristic of a-Si devices. Preliminary circuit noise results and analysis appear promising for its use in noise-sensitive, large-area, medical diagnostic imaging applications such as digital fluoroscopy.

Journal ArticleDOI
TL;DR: In this paper, the authors investigated the silicon thickness dependence of the low field electron mobility in ultrathin silicon-on-insulator (UT-SOI) MOSFETs operated both in single and in double-gate mode.
Abstract: In this paper, we have extensively investigated the silicon thickness dependence of the low field electron mobility in ultrathin silicon-on-insulator (UT-SOI) MOSFETs operated both in single- and in double-gate mode. A physically based model including all the scattering mechanisms that are known to be most relevant in bulk MOSFETs has been extended and applied to SOI structures. A systematic comparison with the measurements shows that the experimental mobility dependence on the silicon thickness (T/sub SI/) cannot be quantitatively explained within the transport picture that seems adequate for bulk transistors. In an attempt to improve the agreement with the experiments, we have critically rediscussed our model for the phonon scattering and developed a model for the scattering induced by the T/sub SI/ fluctuations. Our results suggest that the importance of the surface optical (SO) phonons could be significantly enhanced in UT-SOI MOSFETs with respect to bulk transistors. Furthermore, both the SO phonon and the T/sub SI/ fluctuation scattering are remarkably enhanced with reducing T/sub SI/, so that they could help explain the experimental mobility behavior.

Journal ArticleDOI
TL;DR: The operation of a QCA latch and a shift register is discussed and an analysis of the types and properties of errors encountered in their operation is presented.
Abstract: Quantum-dot cellular automata (QCA) is a digital logic architecture that uses single electrons in arrays of quantum dots to perform binary operations. A QCA latch is an elementary building block which can be used to build shift registers and logic devices for clocked QCA architectures. We discuss the operation of a QCA latch and a shift register and present an analysis of the types and properties of errors encountered in their operation.

Journal ArticleDOI
TL;DR: Some innovative technologies were introduced to achieve ultrahigh performance, including slanted linear CCD in situ storage, curving design procedure, and a CCD switch with fewer metal shunting wires.
Abstract: An image sensor for a video camera of 1000000 frames per second (fps) was developed. The specifications of the developed sensor are as follows: 1) frame rate: 1000000 fps; 2) pixel count: 81 120 (=312/spl times/260) pixels; 3) total number of successive frames: 103 frames; 4) gray levels: 10 b; and 5) open area of each pixel (fill factor): 580 square micrometers (13%). The overwriting function is installed for synchronization of image capturing with occurrence of the target event. Sensitivity is significantly high with the large photogate. Some innovative technologies were introduced to achieve ultrahigh performance, including slanted linear CCD in situ storage, curving design procedure, and a CCD switch with fewer metal shunting wires. They are applicable to the development of other new high-performance image sensors.

Journal ArticleDOI
TL;DR: In this article, the write/erase characteristics of Germanium nanocrystal memory device were modeled using single-charge tunneling theory with quantum confinement and Coulomb blockade effects, and a trap model was proposed to describe the retention characteristic of the memory.
Abstract: The write/erase characteristics of Germanium nanocrystal memory device are modeled using single-charge tunneling theory with quantum confinement and Coulomb blockade effects. A trap model is proposed to describe the retention characteristic of the nanocrystal memory. The impact of nanocrystal size, tunnel-oxide thickness, and high-k tunnel material is studied, and the suitability of the nanocrystal memory devices for nonvolatile memory and DRAM applications is discussed. Issues related to the scaling limit of the nanocrystal memory device are investigated.

Journal ArticleDOI
TL;DR: A new vision chip architecture for high-speed target tracking including multitarget tracking with collision and separation has successfully been achieved and a prototype chip has been developed.
Abstract: This paper describes a new vision chip architecture for high-speed target tracking. The processing speed and the number of pixels are improved by hardware implementation of a special algorithm which utilizes a property of high-speed vision and introduction of bit-serial and cumulative summation circuits. As a result, 18 objects in a 128 /spl times/ 128 image can be tracked in 1 ms. Based on the architecture, a prototype chip has been developed; 64 /spl times/ 64 pixels are integrated in 7 mm square chip and the power consumption for obtaining the centroid of an object per every 1 ms is 112 mW. Some experiments are performed on the evaluation board which is developed for evaluation under the condition of actual operation. High-speed target tracking including multitarget tracking with collision and separation has successfully been achieved.

Journal ArticleDOI
TL;DR: In this paper, a capacitorless, asymmetric double-gated DRAM (DG-DRAM) technology was presented, which reduces dopant fluctuation effects, off-state leakage, and disturb problems.
Abstract: A capacitorless, asymmetric double gate DRAM (DG-DRAM) technology is presented. Its double gate, thin body structure reduces dopant fluctuation effects, off-state leakage, and disturb problems. The cell's large body coefficient amplifies small gains of body potential into increased drain current. Experimental measurements of DG-DRAM were made using recessed channel SOI n-MOSFETs. No significant degradation in programming, retention, and read behavior was observed after 10/sup 11/ cycles. Cell geometry, operating voltages, and material quality should be considered for DG-DRAM in embedded and stand-alone applications. The feasibility of DG-DRAM in future high density CMOS memories depends on issues such as manufacturability, soft error reliability, and tail bit distribution.

Journal ArticleDOI
TL;DR: In this article, the authors investigated the optical and electrical crosstalk in a color CMOS image sensor with active pixel structure and determined the distribution of sensitivity inside a pixel.
Abstract: The paper describes results of crosstalk investigations and microlens (/spl mu/-lens) scan experiments in a color CMOS image sensor with active pixel structure . The investigation of optical and electrical crosstalk was made on 7.8- and 5.6-/spl mu/m pixels by using samples with continuous shift of color filter (CF ) and /spl mu/-lens across the array. As a result of this investigation, the distribution of sensitivity inside a pixel has been determined. By using minimum crosstalk criteria, the optimum parameters of the /spl mu/-lens manufacturing process and optimum position of the /spl mu/-lens was determined. The paper presents color maps of pixel sensitivity and crosstalk criteria as well as snapshots illustrating sensitivity distribution and collection area. The paper presents spectral characteristics measured at different relative apertures (f-number) as well. The quantitative analysis of spectral responses allowed us to determine the contribution of each component to the overall crosstalk.

Journal ArticleDOI
TL;DR: In this article, lateral scattering of retrograde well implants is shown to have an effect on the threshold voltage of nearby devices, and it is shown that threshold voltage decreases for narrow devices near the edge of the well.
Abstract: Lateral scattering of retrograde well implants is shown to have an effect on the threshold voltage of nearby devices. The threshold voltage of both NMOSFETs and PMOSFETs increases in magnitude for conventional retrograde wells, but for triple-well isolated NMOSFETs the threshold voltage decreases for narrow devices near the edge of the well. Electrical data, SIMS, and SUPREM4 simulations are shown that elucidate the phenomenon.