Showing papers in "IEEE Transactions on Electron Devices in 2004"
TL;DR: In this paper, a leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low/spl kappa/CDO for high-performance dense logic is presented.
Abstract: A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si/sub 1-x/Ge/sub x/ in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by >50%. A tensile silicon nitride-capping layer is used to introduce tensile strain into the n-type MOSFET and enhance electron mobility by 20%. Unlike all past strained-Si work, the hole mobility enhancement in this paper is present at large vertical electric fields in nanoscale transistors making this strain technique useful for advanced logic technologies. Furthermore, using piezoresistance coefficients it is shown that significantly less strain (/spl sim/5 /spl times/) is needed for a given PMOS mobility enhancement when applied via longitudinal uniaxial compression versus in-plane biaxial tension using the conventional Si/sub 1-x/Ge/sub x/ substrate approach.
728 citations
TL;DR: In this article, a detailed investigation of electronic switching in chalcogenide-based phase-change memory devices is presented, and a physical picture of the switching mechanism is proposed.
Abstract: A detailed investigation of electronic switching in chalcogenide-based phase-change memory devices is presented. An original bandgap model consistent with the microscopic structure of both crystalline and amorphous chalcogenide is described, and a physical picture of the switching mechanism is proposed. Numerical simulations provide, for the first time, a quantitative description of the peculiar current-voltage curve of a Ge/sub 2/Sb/sub 2/Te/sub 5/ resistor, in good agreement with measurements performed on test devices.
586 citations
TL;DR: In this paper, a detailed investigation of the time evolution for the low-field resistance R/sub off/ and the threshold voltage V/sub th/ in chalcogenide-based phase-change memory devices is presented.
Abstract: A detailed investigation of the time evolution for the low-field resistance R/sub off/ and the threshold voltage V/sub th/ in chalcogenide-based phase-change memory devices is presented. It is observed that both R/sub off/ and V/sub th/ increase and become stable with time and temperature, thus improving the cell readout window. Relying on a microscopic model, the drift of R/sub off/ and V/sub th/ is linked to the dynamic of the intrinsic traps typical of amorphous chalcogenides, thus providing for the first time a unified framework for the comprehension of chalcogenide materials transient behavior.
370 citations
TL;DR: In this paper, the authors investigated drain current dispersion effects in AlGaN-GaN HEMTs by means of pulsed, transient, and small-signal measurements.
Abstract: Drain current dispersion effects are investigated in AlGaN-GaN HEMTs by means of pulsed, transient, and small-signal measurements. Gate- and drain-lag effects characterized by time constants in the order of 10/sup -5/-10/sup -4/ s cause dispersion between dc and pulsed output characteristics when the gate or the drain voltage are pulsed. An activation energy of 0.3 eV is extracted from temperature-dependent gate-lag measurements. We show that two-dimensional numerical device simulations accounting only for polarization charges and donor-like traps at the ungated AlGaN surface can quantitatively reproduce all dispersion effects observed experimentally in the different pulsing modes, provided that the measured activation energy is adopted as the energetic distance of surface traps from the valence-band edge. Within this hypothesis, simulations show that surface traps behave as hole traps during transients, interacting with holes attracted at the AlGaN surface by the negative polarization charge.
316 citations
TL;DR: In this paper, the authors performed a comprehensive scaling study of Schottky-barrier (SB) carbon nanotube transistors using self-consistent, atomistic scale simulations.
Abstract: We performed a comprehensive scaling study of Schottky-barrier (SB) carbon nanotube transistors using self-consistent, atomistic scale simulations. We restrict our attention to SB carbon nanotube field-effect transistors (FETs) whose metal source-drain is attached to an intrinsic carbon nanotube channel. Ambipolar conduction is found to be an important factor that must be carefully considered in device design, especially when the gate oxide is thin. The channel length scaling limit imposed by source-drain tunneling is found to be between 5 nm and 10 nm, depending on the off-current specification. Using a large diameter tube increases the on-current, but it also increases the leakage current. Our study of gate dielectric scaling shows that the charge on the nanotube can play an important role above threshold.
306 citations
TL;DR: In this paper, a vertical field effect transistor (FET) with a vertical gate controlling the band-to-band tunneling width is presented, and the operation of the device is shown by means of both experimental results as well as two-dimensional computer simulations.
Abstract: The realization of a novel vertically grown tunnel field-effect transistor (FET) with several interesting properties is presented. The operation of the device is shown by means of both experimental results as well as two-dimensional computer simulations. This device consists of a MBE-grown, vertical p-i-n structure. A vertical gate controls the band-to-band tunneling width, and hence the tunneling current. Both n-channel and p-channel current behavior is observed. A perfect saturation in drain current-voltage (I/sub D/--V/sub DS/) characteristics in the reverse-biased condition for n-channel, an exponential and nearly temperature independent drain current-gate voltage (I/sub D/--V/sub GS/) relation for both subthreshold, as well as on-region, and source-drain off-currents several orders of magnitude lower then the conventional MOSFET are achieved. In the forward-biased condition, the device shows normal p-i-n diode characteristics.
270 citations
TL;DR: In this paper, a 2D analytical solution of electrostatic potential is derived for undoped (or lightly doped) double-gate (DG) MOSFETs in the sub-threshold region by solving Poissons equation in a 2-D boundary value problem.
Abstract: A two-dimensional (2-D) analytical solution of electrostatic potential is derived for undoped (or lightly doped) double-gate (DG) MOSFETs in the subthreshold region by solving Poissons equation in a 2-D boundary value problem. It is shown that the subthreshold current, short-channel threshold voltage rolloff and subthreshold slope predicted by the analytical solution are in close agreement with 2-D numerical simulation results for both symmetric and asymmetric DG MOSFETs without the need of any fitting parameters. The analytical model not only provides useful physics insight into short-channel effects, but also serves as basis for compact modeling of DG MOSFETs.
251 citations
TL;DR: In this article, a 2D analytical model for the surface potential variation along the channel in fully depleted dual-material gate silicon-on-insulator MOSFETs is developed to investigate the short-channel effects (SCEs).
Abstract: A two-dimensional (2-D) analytical model for the surface potential variation along the channel in fully depleted dual-material gate silicon-on-insulator MOSFETs is developed to investigate the short-channel effects (SCEs). Our model includes the effects of the source/drain and body doping concentrations, the lengths of the gate metals and their work functions, applied drain and substrate biases, the thickness of the gate and buried oxide and also the silicon thin film. We demonstrate that the surface potential in the channel region exhibits a step function that ensures the screening of the drain potential variation by the gate near the drain resulting in suppressed SCEs like the hot-carrier effect and drain-induced barrier-lowering (DIBL). The model is extended to find an expression for the threshold voltage in the submicrometer regime, which predicts a desirable "rollup" in the threshold voltage with decreasing channel lengths. The accuracy of the results obtained using our analytical model is verified using 2-D numerical simulations.
247 citations
TL;DR: In this article, the electrical performance of organic polymer thin-film transistors under steady-state white-light illumination, as well as the performance of these devices as photodetectors, was studied.
Abstract: We have studied the electrical performance of organic polymer thin-film transistors (OP-TFTs) under steady-state white-light illumination, as well as the performance of these devices as photodetectors. The off-state drain current of the OP-TFT is significantly increased due to the illumination, while a smaller relative effect is observed on the drain current in the strong-accumulation regime. The illumination effectively decreases the threshold voltage of the device and increases the apparent subthreshold swing, while the field-effect mobility of the charge carriers in the polymer channel is unchanged. We have observed full recovery of our devices after the illumination is removed at room temperature. These observations are explained in terms of the photogeneration of excitons due to the absorbed photons. The photogenerated excitons subsequently diffuse and dissociate into free charge carriers, thereby enhancing the carrier density in the channel of the device. We have found broadband responsivities of approximately 0.7 mA/W for devices biased in the strong-accumulation regime and gate-to-source voltage-independent photosensitivities of approximately 10/sup 3/ for devices in the off-state. We also determine, for the first time, the flatband voltage of these devices to be about -2.3 V.
243 citations
TL;DR: In this paper, the degradation of channel mobility due to Coulomb scattering arising from interface trapped charges, and remote soft optical phonon scattering are discussed, as well as channel resistance, gate leakage current, and contact resistance for a MOSFET with ultrathin high-k dielectric.
Abstract: Accurate measurements and degradation mechanisms of the channel mobility for MOSFETs with HfO/sub 2/ as the gate dielectric have been systematically studied in this paper. The error in mobility extraction caused by a high density of interface traps for a MOSFET with high-k gate dielectric has been analyzed, and a new method to correct this error has been proposed. Other sources of error in mobility extraction, including channel resistance, gate leakage current, and contact resistance for a MOSFET with ultrathin high-k dielectric have also been investigated and reported in this paper. Based on the accurately measured channel mobility, we have analyzed the degradation mechanisms of channel mobility for a MOSFET with HfO/sub 2/ as the gate dielectric. The mobility degradation due to Coulomb scattering arising from interface trapped charges, and that due to remote soft optical phonon scattering are discussed.
223 citations
TL;DR: An all ink-jet-deposited process capable of creating high-quality passive devices suitable for an RFID front-end is described in this paper, where gold nanocrystals are printed to create conductive lines with sheet resistance as low as 23 m/spl Omega/ per square.
Abstract: An all ink-jet-deposited process capable of creating high-quality passive devices suitable for an RFID front-end is described. Gold nanocrystals are printed to create conductive lines with sheet resistance as low as 23 m/spl Omega/ per square. Optimal printing conditions are found for polyimide dielectric layers and films as thin as 340 nm are produced. These results are used to create spiral inductors, interconnect, and parallel plate capacitors.
TL;DR: In this article, the relative contributions of interface- and bulk-trap generation to this device degradation mode are analyzed for a wide range of stress bias and stress temperature, as well as those of inversion layer holes, impact ionized hot holes, and hot electrons on interface and bulk trap generation, are identified.
Abstract: Negative bias temperature instability is studied in thick and thin gate oxide p-MOSFETs. The relative contributions of interface- and bulk-trap generation to this device degradation mode are analyzed for a wide range of stress bias and stress temperature. The effects of gate voltage and oxide field, as well as those of inversion layer holes, impact ionized hot holes, and hot electrons on interface- and bulk-trap generation, are identified. The bulk-trap generation process is interpreted within the modified anode-hole injection model and the mechanism of interface-trap generation is modeled within the framework of the classical reaction-diffusion theory. The diffusion species for interface-trap generation is unambiguously identified. Moreover, a high-temperature, diffusion-triggered, enhanced interface-trap generation mechanism is discussed for thin gate oxide p-MOSFETs. Finally, a novel scaling methodology is proposed for interface-trap generation that helps in obtaining a simple, analytical model useful for reliability projection.
TL;DR: In this article, it was shown that Fermi-pinning at the polysilicon/metal-oxide interface causes high threshold voltages in MOSFET devices.
Abstract: We report here that Fermi pinning at the polysilicon/metal-oxide interface causes high threshold voltages in MOSFET devices. In Part I, we investigated the different gatestack regions and determined that the polysilicon/metal oxide interface plays a key role on the threshold voltages. Now in Part II, the effects of the interfacial bonding are examined by experiments with submonolayer atomic-layer deposition (ALD) metal oxides and atomistic simulation. Results indicate that pinning occurs due to the interfacial Si-Hf and Si-O-Al bonds for HfO/sub 2/ and Al/sub 2/O/sub 3/, respectively. Oxygen vacancies at polysilicon/HfO/sub 2/ interfaces also lead to Fermi pinning. This fundamental characteristic affects the observed polysilicon depletion.
TL;DR: In this paper, the authors have fabricated pentacene-based thin film transistors and analyzed their electrical properties with the help of two-dimensional drift-diffusion simulations which favorably compare with the experimental results.
Abstract: We have fabricated pentacene-based thin film transistors and analyzed their electrical properties with the help of two-dimensional drift-diffusion simulations which favorably compare with the experimental results. We have set up a model considering the polycrystalline nature of pentacene and the presence of grains and grain boundaries. We show how this model can be applied to different devices with different grain sizes and we analyze the relationship between mobility, grain size and applied gate voltage. On the basis of the simulation results, we can introduce an effective carrier mobility, which accounts for grain-related effects. The comparison between experimental results and simulations allows us to clearly understand the differences in the mobility derived by the analysis of current-voltage curve (as done experimentally by using standard MOSFET theory) and the intrinsic mobility of the organic layer. The effect of the pentacene/oxide interface traps and fixed surface charges has also been considered. The dependence of the threshold voltage on the density and energy level of the trap states has been outlined.
TL;DR: In this paper, a novel ultrathin polysilicon film transistor provides the basis for dense and low-power embedded random access memory (RAM), which is made possible by the 2-nm-thick channel, which realizes a quantum-confinement effect that produces a low leakage current value of only 10/sup -19/A at room temperature.
Abstract: This work presents a gain-cell solution in which a novel ultrathin polysilicon film transistor provides the basis for dense and low-power embedded random-access memory (RAM). This is made possible by the new transistor's 2-nm-thick channel, which realizes a quantum-confinement effect that produces a low leakage current value of only 10/sup -19/ A at room temperature. The memory has the potential to solve the power and stability problems that static RAM (SRAM) is going to face in the very near future.
TL;DR: In this paper, an InGaAs monolithic interconnected module (MIM) using reflective spectral control has been fabricated and measured in a thermophotovoltaic radiator/module system (radiator, optical cavity, and thermophotonic module).
Abstract: An InGaAs monolithic interconnected module (MIM) using reflective spectral control has been fabricated and measured in a thermophotovoltaic radiator/module system (radiator, optical cavity, and thermophotovoltaic module). Results showed that at a radiator and module temperature of 1039/spl deg/C and 25/spl deg/C, respectively, 23.6% thermophotovoltaic radiator/module system radiant heat conversion efficiency and 0.79W/cm/sup 2/ maximum thermophotovoltaic radiator/module system power density were obtained. The use of reflective spectral control increased the spectral efficiency and thus the thermophotovoltaic radiator/module system radiant heat conversion efficiency by /spl sim/16% (relative). However, the amount of useful radiation reaching the MIM decreased by /spl sim/7% (relative) compared to using transmissive spectral control. Also, the thermophotovoltaic system radiant heat conversion efficiency and maximum power density using either transmissive or reflective spectral control decreased as the MIM temperature increased. The MIM using reflective spectral control was found to be more sensitive to changes in the MIM temperature than the MIM using transmissive spectral control.
IBM1
TL;DR: In this article, a 15% improvement in gate delay can be expected by optimizing the surface orientation of a high/spl kappa/interface, depending upon the type of logic gate, the off-state leakage specification, and technology scaling trends.
Abstract: With the advent of novel device structures that can be easily fabricated outside of the traditional (100) plane, it may be advantageous to change the crystal orientation to optimize CMOS circuit performance. The use of alternative surface orientations such as [110] and (111) enhances hole mobility while degrading electron mobility, thus allowing for adjustment of the ratio between nMOS and pMOS transistor drive currents. By optimizing the surface orientation, up to a 15% improvement in gate delay can be expected. This value depends upon the type of logic gate, the off-state leakage specification, and technology scaling trends. The introduction of high-/spl kappa/ dielectrics may provide an added incentive for the use of non-(100) orientations as this method of circuit performance enhancement may be used to compensate for mobility degradation from the high-/spl kappa/ interface. Additional concerns including layout area and device reliability are discussed.
TL;DR: In this paper, the authors derived the theoretical limit of delay and energy consumption in MOSFET sub-threshold circuit, and showed that devices that have an ideal sub-reshold slope are optimal for subthreshold operations due to smaller gate capacitance, as well as the higher current.
Abstract: In this paper, we propose MOSFETs that are suitable for subthreshold digital circuit operations. The MOSFET subthreshold circuit would use subthreshold leakage current as the operating current to achieve ultralow power consumption when speed is not of utmost importance. We derive the theoretical limit of delay and energy consumption in MOSFET subthreshold circuit, and show that devices that have an ideal subthreshold slope are optimal for subthreshold operations due to the smaller gate capacitance, as well as the higher current. The analysis suggests that a double gate (DG)-MOSFET is promising for subthreshold operations due to its near-ideal subthreshold slope. The results of our investigation into the optimal device characteristics for DG-MOSFET subthreshold operation show that devices with longer channel length (compared to minimum gate length) can be used for robust subthreshold operation without any loss of performance. In addition, it is shown that the source and drain structure of DG-MOSFET can be simplified for subthreshold operations since source and drain need not be raised to reduce the parasitic resistance.
TL;DR: In this paper, a physically based analytical single electron transistor (SET) model is proposed for hybrid CMOS-SET analog circuit simulation, and the model parameters are physical device parameters and an associated parameter extraction procedure is reported.
Abstract: A physically based compact analytical single electron transistor (SET) model is proposed for hybrid CMOS-SET analog circuit simulation. The modeling approach is based on the "orthodox theory" of single electron tunneling, and valid for single or multi gate, symmetric or asymmetric devices and can also explain the background charge effect. The model parameters are physical device parameters and an associated parameter extraction procedure is reported. The device characteristics produced by the proposed model are verified with Monte Carlo simulation for large range of drain to source voltages (|V/sub DS/|/spl les/3e/C/sub /spl Sigma//) and temperatures [T/spl les/e/sup 2//(10k/sub B/C/sub /spl Sigma//)] and good agreements are observed. The proposed model is implemented in a commercial circuit simulator in order to develop a computer-aided design framework for CMOS-SET hybrid IC designs. A series of SPICE simulations are successfully carried out for different CMOS-SET hybrid circuits in order to reproduce their experimental/Monte Carlo simulated characteristics.
TL;DR: The Ge-NC embedded in HfAlO is a promising candidate for further scaling of FG Flash memory devices and can achieve a low programming voltage of 6-7 V for fast programming, a long charge retention time of ten years maintaining a 0.7-V memory window.
Abstract: We fabricated a nonvolatile Flash memory device using Ge nanocrystals (NCs) floating-gate (FG)-embedded in HfAlO high-/spl kappa/ tunneling/control oxides. Process compatibility and memory operation of the device were investigated. Results show that Ge-NC have good thermal stability in the HfAlO matrix as indicated by the negative Gibbs free energy changes for both reactions of GeO/sub 2/+Hf/spl rarr/HfO/sub 2/+Ge and 3GeO/sub 2/+4Al/spl rarr/2Al/sub 2/O/sub 3/+3Ge. This stability implies that the fabricated structure can be compatible with the standard CMOS process with the ability to sustain source-drain activation anneal temperatures. Compared with Si-NC embedded in HfO/sub 2/, Ge-NC embedded in HfAlO can provide more electron traps, thereby enlarging the memory window. It is also shown that this structure can achieve a low programming voltage of 6-7 V for fast programming, a long charge retention time of ten years maintaining a 0.7-V memory window, and good endurance characteristics of up to 10/sup 6/ rewrite cycles. This paper shows that the Ge-NC embedded in HfAlO is a promising candidate for further scaling of FG Flash memory devices.
TL;DR: In this paper, the temporal read noise on the signal path of a complementary metal-oxide semiconductor image sensor is analyzed to investigate the effectiveness of high-gain column amplifiers in enhancing sensor sensitivity.
Abstract: The temporal read noise on the signal path of a complementary metal-oxide semiconductor image sensor is analyzed to investigate the effectiveness of high-gain column amplifiers in enhancing sensor sensitivity. The signal path examined includes a pixel source follower, a switched-capacitor, noise-cancelling, high-gain amplifier, and a sample-and-hold circuit in each column. It is revealed that the total random readout noise consists of a component due to noise charge sampled and held at the charge summation node of the amplifier and transferred to the output, and a direct noise component sampled at the sample-and-hold stage at the output of the column amplifier. The analysis suggests that the direct noise components can be greatly reduced by increasing the column amplifier gain, indicating that an extremely low-noise readout circuit may be achievable through the development of a double-stage noise-cancelling architecture.
TL;DR: In this paper, the hot-carrier degradation behavior of both a lateral and a vertical integrated DMOS transistor is investigated by the analysis of the electrical data, charge pumping measurements and two-dimensional device simulations.
Abstract: The hot-carrier degradation behavior of both a lateral and a vertical integrated DMOS transistor is investigated in detail by the analysis of the electrical data, charge pumping measurements and two-dimensional device simulations. Upon hot-carrier stress, two different, and competing degradation mechanisms are present: channel electron mobility reduction due to interface trap formation, and injection and trapping of hot holes in the accumulation region of the transistor. It will be shown that the latter mechanism is absent in the vertical DMOS.
TL;DR: In this article, a model based on the eigenfunction derivatives at the Si-oxide interface can be naturally extended to SOI MOSFETs and, furthermore, a formulation based on appropriate integrals of the Eigenfunctions in the silicon film, which must replace the expected value of the field used in bulk MOS FETs, is derived.
Abstract: In this paper, we discuss in detail the modeling of surface roughness (SR) scattering in single- and double-gate silicon-on-insulator (SOI) MOSFETs, where the conventional formulation based on the expected value of the electric field cannot be used. By reconsidering the Ando's original approach, we show that a model based on the eigenfunction derivatives at the Si-oxide interface can be naturally extended to SOI MOSFETs, and, furthermore, we also derive a formulation based on appropriate integrals of the eigenfunctions in the silicon film, which must replace the expected value of the field used in bulk MOSFETs. All the analytical identities used in the derivation of the model have been verified by using numerically calculated eigenvalues and wavefunctions. Our results indicate that, in ultrathin-film SOI MOSFETs, the effective field is no longer a good metric for the SR scattering and, furthermore, SR scattering affects the total mobility even at lower inversion densities than it does in bulk transistors.
TL;DR: In this paper, the authors compared the performance of FD dual-material gate (DMG) SOI MOSFETs with their single material gate counterparts and provided an incentive for further experimental exploration.
Abstract: The novel features of a fully depleted (FD) dual-material gate (DMG) silicon-on-insulator (SOI) MOSFET are explored theoretically and compared with those of a compatible SOI MOSFET. The two-dimensional numerical simulation studies demonstrate the novel features as threshold voltage roll-up and simultaneous transconductance enhancement and suppression of short-channel effects offered by the FD DMG SOI MOSFET. Moreover, these unique features can be controlled by engineering the workfunction and length of the gate material. This work illustrates the benefits of high-performance FD DMG SOI MOS devices over their single material gate counterparts and provides an incentive for further experimental exploration.
TL;DR: In this paper, the effects of the overlap between the three absorption coefficients involved in the operation of the intermediate band solar cell on the performance of this novel photovoltaic converter were studied.
Abstract: This paper studies the effects of the overlap between the three absorption coefficients involved in the operation of the intermediate band solar cell on the performance of this novel photovoltaic converter. Although an arbitrary overlap, in general, reduces the limiting efficiency of the intermediate band solar cell (for example from 57.29% to 32.56% under 1000 suns), its impact can be minimized and almost suppressed when the absorption coefficients increase with energy, and light confinement is used. Another important consequence derived from the overlap between the absorption coefficients is that the thickness of the intermediate band solar cell, even using detailed balance arguments and in contrast to the detailed balance model of the conventional single-gap solar cell, now becomes a parameter to be optimized.
TL;DR: In this article, a detailed study of cleaning conditions for the Ge wafer, dielectric deposition condition, and anneal conditions and their effect on the electrical properties of metal-gated dielectrics-Ge capacitors was carried out.
Abstract: We have studied ultrathin Al/sub 2/O/sub 3/ and HfO/sub 2/ gate dielectrics on Ge grown by ultrahigh vacuum-reactive atomic-beam deposition and ultraviolet ozone oxidation. Al/sub 2/O/sub 3/-Ge gate stack had a t/sub eq//spl sim/23 /spl Aring/, and three orders of magnitude lower leakage current compared to SiO/sub 2/. HfO/sub 2/-Ge allowed even greater scaling, achieving t/sub eq//spl sim/11 /spl Aring/ and six orders of magnitude lower leakage current compared to SiO/sub 2/. We have carried out a detailed study of cleaning conditions for the Ge wafer, dielectric deposition condition, and anneal conditions and their effect on the electrical properties of metal-gated dielectric-Ge capacitors. We show that surface nitridation is important in reducing hysteresis, interfacial layer formation and leakage current. However, surface nitridation also introduces positive trapped charges and/or dipoles at the interface, resulting in significant flatband voltage shifts, which are mitigated by post-deposition anneals.
TL;DR: In this paper, the authors investigated the characteristics of dark signals in the CMOS active pixel sensor (APS) with test structures fabricated using the deep-submicron CMOS technology and found that the periphery of the photodiode (PD) is the dominant source of dark currents in our test structure, and this factor is sensitive to the distance between the sidewall of the shallow trench isolation and the n-type region of the PD.
Abstract: The characteristics of dark signals have been investigated in the CMOS active pixel sensor (APS) with test structures fabricated using the deep-submicron CMOS technology. It is found that the periphery of the photodiode (PD) is the dominant source of dark currents in our test structure, and this factor is very sensitive to the distance between the sidewall of the shallow trench isolation and the n-type region of the PD. The dark currents from the transfer gate can be effectively reduced by the tail of p/sup +/ region on the surface of the transfer gate, and those from the floating diffusion (FD) node were estimated to be negligible in the normal operational mode. However, because of the enhanced thermal generation velocity caused by the severe process-induced damages, the FD node was considered as the main source of increased dark currents in the single frame capture mode. The characteristics of quantized dark currents causing the white pixels in the CMOS APS were examined using the dark current spectroscopy method. Three distinct deep-level bulk traps have been identified with the location in the silicon bandgap at |E/sub t/-E/sub i/|/spl sim/0.020 (eV), |E/sub t/-E/sub i/|/spl sim/0.082 (eV), and |E/sub t/-E/sub i/|/spl sim/0.058 (eV), and capture cross sections of 7.80/spl times/10/sup -15/ cm/sup 2/, 1.83/spl times/10/sup -13/ cm/sup 2/, and 1.46/spl times/10/sup -13/ cm/sup 2/ respectively.
TL;DR: In this article, the over-erase phenomenon in the polysiliconoxide-silicon nitride-oxide silicon (SONOS) memory structure is minimized by using hafnium oxide or ha fnium aluminum oxide to replace silicon nitride as the charge storage layer (the resulting structures are termed SOHOS devices, where the "H" denotes the high dielectric constant material instead of silicon Nitride).
Abstract: The over-erase phenomenon in the polysilicon-oxide-silicon nitride-oxide-silicon (SONOS) memory structure is minimized by using hafnium oxide or hafnium aluminum oxide to replace silicon nitride as the charge storage layer (the resulting structures are termed SOHOS devices, where the "H" denotes the high dielectric constant material instead of silicon nitride). Unlike SONOS devices, SOHOS structures show a reduced over-erase phenomenon and self-limiting charge storage behavior under both erase and program operations. These are attributed to the differences in band offset and the crystallinity of the charge storage layer.
TL;DR: In this article, the authors address the critical problem of global wire optimization for nanometer scale very large scale integration technologies, and elucidates the impact of such optimization on power dissipation, bandwidth, and performance.
Abstract: This paper addresses the critical problem of global wire optimization for nanometer scale very large scale integration technologies, and elucidates the impact of such optimization on power dissipation, bandwidth, and performance. Specifically, this paper introduces a novel methodology for optimizing global interconnect width, which maximizes a novel figure of merit (FOM) that is a user-defined function of bandwidth per unit width of chip edge and latency. This methodology is used to develop analytical expressions for optimum interconnect widths for typical FOMs for two extreme scenarios regarding line spacing: 1) spacing kept constant at its minimum value and 2) spacing kept the same as line width. These expressions have been used to compute the optimal global interconnect width and quantify the effect of increasing the line width on various performance metrics such as delay per unit length, total repeater area and power dissipation, and bandwidth for various International Technology Roadmap for Semiconductors technology nodes.
TL;DR: In this article, a physics-based MOSFET drain thermal noise current model valid for deep submicron channel lengths was derived and verified with experiments, and the derived model was verified by experimental noise for devices with channel lengths down to 0.18 /spl mu/Q/sub inv//L/sup 2/m.
Abstract: In this paper, a physics-based MOSFET drain thermal noise current model valid for deep submicron channel lengths was derived and verified with experiments. It is found that the well-known /spl mu/Q/sub inv//L/sup 2/ formula, previously derived for long channels, remains valid for short channels. Carrier heating in the gradual channel region was taken into account implicitly with the form of diffusion noise source and then impedance field method taking velocity saturation effect was used to calculate the external drain thermal noise current. The derived model was verified by experimental noise for devices with channel lengths down to 0.18 /spl mu/m. Excellent agreement between measured and modeled drain thermal noise was obtained for the entire V/sub GS/ and V/sub DS/ bias regions.