Showing papers in "IEEE Transactions on Electron Devices in 2008"
TL;DR: In this paper, the authors review advances in chemically synthesized semiconductor nanowires as nanoelectronic devices and discuss 3-D heterogeneous integration that is uniquely enabled by multifunctional nanowire within a bottom-up approach.
Abstract: Semiconductor nanowires represent unique materials for exploring phenomena at the nanoscale. Developments in nanowire growth have led to the demonstration of a wide range of nanowire materials with precise control of composition, morphology, and electrical properties, and it is believed that this excellent control together with small channel size could yield device performance exceeding that obtained using top-down techniques. Here, we review advances in chemically synthesized semiconductor nanowires as nanoelectronic devices. We first introduce basic nanowire field-effect transistor structures and review results obtained from both p- and n-channel homogeneous composition nanowires. Second, we describe nanowire heterostructures, show that by using nanowire heterostructures, several limiting factors in homogeneous nanowire devices can be mitigated, and demonstrate that nanowire transistor performance can reach the ballistic limit and exceed state-of-the-art planar devices. Third, we discuss basic methods for organization of nanowires necessary for fabricating arrays of device and circuits. Fourth, we introduce the concept of crossbar nanowire circuits, discuss results for both transistor and nonvolatile switch devices, and describe unique approaches for multiplexing/demultiplexing enabled by synthetically coded nanowire. Fifth, we discuss the unique application of thin-film nanowire transistor arrays on low-cost substrates and illustrate this with results for relatively high-frequency ring oscillators and completely transparent device arrays. Finally, we describe 3-D heterogeneous integration that is uniquely enabled by multifunctional nanowires within a bottom-up approach.
TL;DR: In this paper, the authors show that blindly applying these techniques on alternative substrates can lead to incorrect conclusions, and that it is possible to both under- and overestimate the interface trap density by more than an order of magnitude.
Abstract: ldquoConventionalrdquo techniques and related capacitance-voltage characteristic interpretation were established to evaluate interface trap density on Si substrates. We show that blindly applying these techniques on alternative substrates can lead to incorrect conclusions. It is possible to both under- and overestimate the interface trap density by more than an order of magnitude. Pitfalls jeopardizing capacitance-and conductance-voltage characteristic interpretation for alternative semiconductor MOS are elaborated. We show how the conductance method, the most reliable and widely used interface trap density extraction method for Si, can be adapted and made reliable for alternative semiconductors while maintaining its simplicity.
TL;DR: In this article, the electronic transport properties of nanowire field effect transistors (NW-FETs) are discussed in detail, and four different device concepts are studied in detail.
Abstract: This paper discusses the electronic transport properties of nanowire field-effect transistors (NW-FETs). Four different device concepts are studied in detail: Schottky-barrier NW-FETs with metallic source and drain contacts, conventional-type NW-FETs with doped NW segments as source and drain electrodes, and, finally, two new concepts that enable steep turn-on characteristics, namely, NW impact ionization FETs and tunnel NW-FETs. As it turns out, NW-FETs are, to a large extent, determined by the device geometry, the dimensionality of the electronic transport, and the way of making contacts to the NW. Analytical as well as simulation results are compared with experimental data to explain the various factors impacting the electronic transport in NW-FETs.
TL;DR: In this paper, a detailed investigation of MWCNT-based interconnect performance is presented, for the first time, and a compact equivalent circuit model is presented for evaluating and compared with traditional Cu interconnects, as well as Single-Walled CNT (SWCNT) based interconnect, at different interconnect levels.
Abstract: Metallic carbon nanotubes (CNTs) have received much attention for their unique characteristics as a possible alternative to Cu interconnects in future ICs. Until this date, while almost all fabrication efforts have been directed toward multiwalled CNT (MWCNT) interconnects, there is a lack of MWCNT modeling work. This paper presents, for the first time, a detailed investigation of MWCNT-based interconnect performance. A compact equivalent circuit model of MWCNTs is presented for the first time, and the performance of MWCNT interconnects is evaluated and compared against traditional Cu interconnects, as well as Single-Walled CNT (SWCNT)-based interconnects, at different interconnect levels (local, intermediate, and global) for future technology nodes. It is shown that at the intermediate and global levels, MWCNT interconnects can achieve smaller signal delay than that of Cu interconnects, and the improvements become more significant with technology scaling and increasing wire lengths. At 1000- global or 500- intermediate level interconnects, the delay of MWCNT interconnects can reach as low as 15% of Cu interconnect delay. It is also shown that in order for SWCNT bundles to outperform MWCNT interconnects, dense and high metallic-fraction SWCNT bundles are necessary. On the other hand, since MWCNTs are easier to fabricate with less concern about the chirality and density control, they can be attractive for immediate use as horizontal wires in VLSI, including local, intermediate, and global level interconnects.
TL;DR: In this article, the authors reviewed the recent approaches in realizing carrier-transport-enhanced CMOS, and the critical issues, fabrication techniques, and device performance of MOSFETs using three types of channel materials, Si (SiGe) with uniaxial strain, Ge-on-insulator (GOI), and III-V semiconductors, are presented.
Abstract: An effective way to reduce supply voltage and resulting power consumption without losing the circuit performance of CMOS is to use CMOS structures using high carrier mobility/velocity. In this paper, our recent approaches in realizing these carrier-transport-enhanced CMOS will be reviewed. First, the basic concept on the choice of channels for increasing on current of MOSFETs, the effective-mass engineering, is introduced from the viewpoint of both carrier velocity and surface carrier concentration under a given gate voltage. Based on this understanding, critical issues, fabrication techniques, and the device performance of MOSFETs using three types of channel materials, Si (SiGe) with uniaxial strain, Ge-on-insulator (GOI), and III-V semiconductors, are presented. As for the strained devices, the importance of uniaxial strain, as well as the combination with multigate structures, is addressed. A novel subband engineering for electrons on (110) surfaces is also introduced. As for GOI MOSFETs, the versatility of the Ge condensation technique for fabricating a variety of Ge-based devices is emphasized. In addition, as for III-V semiconductor MOSFETs, advantages and disadvantages on low effective mass are examined through simple theoretical calculations.
TL;DR: In this article, a 20-kHz 370-W dc/dc boost converter based on a 10-kV 4H-SiC DMOSFET and diodes is designed and experimentally demonstrated.
Abstract: Ten-kilovolt SiC MOSFETs are currently under development by a number of organizations in the United States, with the aim of enabling their applications in high-voltage high-frequency power conversions. The aim of this paper is to obtain the key device characteristics of SiC MOSFETs so that their realistic application prospect can be provided. In particular, the emphasis is on obtaining their losses in various operation conditions from the extensive characterization study and a proposed behavioral SPICE model. Using the validated MOSFET SPICE model, a 20-kHz 370-W dc/dc boost converter based on a 10-kV 4H-SiC DMOSFET and diodes is designed and experimentally demonstrated. In the steady state of the boost converter, the total power loss in the 15.45-mm2 SiC MOSFET is 23.6 W for the input power of 428 W. The characterization study of the experimental SiC MOSFET and the experiment of the SiC MOSFET-based boost converter indicate that the turn-on losses of SiC MOSFETs are the dominant factors in determining their maximum operation frequency in hard-switched circuits with conventional thermal management. Replacing a 10-kV SiC PiN diode with a 10-kV SiC JBS diode as a boost diode and using a small external gate resistor, the turn-on loss of the SiC MOSFET can be reduced, and the 10-kV 5-A SiC MOSFET-based boost converter is predicted to be capable of a 20-kHz operation with a 5-kV dc output voltage and a 1.25-kW output power by the PSpice simulation with the MOSFET model. The low losses and fast switching speed of 10-kV SiC MOSFETs shown in the characterization study and the preliminary demonstration of the boost converter make them attractive in high-frequency high-voltage power-conversion applications.
TL;DR: In this article, the authors proposed a novel tunnel source (PNPN) n-MOSFET based on the principle of band-to-band tunneling, which has the potential of steep subthreshold swing and improved Ion in addition to immunities against SCEs.
Abstract: As MOSFET is scaled below 90 nm, many daunting challenges arise. Short-channel effects (SCEs; drain-induced barrier lowering and VTHmiddotrolloff), off-state leakage, parasitic capacitance, and resistance severely limit the performance of these transistors. New device innovations are essential to overcome these difficulties. In this paper, we propose the concept of a novel tunnel source (PNPN) n-MOSFET based on the principle of band-to- band tunneling. It is found that the PNPN n-MOSFET has the potential of steep subthreshold swing and improved Ion in addition to immunities against SCEs. Therefore, such a PNPN n-MOSFET can overcome the ever-degrading on-off characteristics of the deeply scaled conventional MOSFET. The design of the PNPN n-MOSFET was extensively examined using simulations. Devices with source-side tunneling junctions were fabricated on bulk substrates using spike anneal, and the experimental data is presented.
TL;DR: In this article, the authors observed significant instability in the threshold voltage of 4H-SiC metal-oxide-semiconductor field effect transistors due to gate-bias stressing.
Abstract: We have observed significant instability in the threshold voltage of 4H-SiC metal-oxide-semiconductor field-effect transistors due to gate-bias stressing. This effect has a strong measurement time dependence. For example, a 20-mus-long gate ramp used to measure the I-V characteristic and extract a threshold voltage was found to result in a instability three to four times greater than that measured with a 1-s-long gate ramp. The VT instability was three times greater in devices that did not receive a NO postoxidation anneal compared with those that did. This instability effect is consistent with electrons directly tunneling in and out of near-interfacial oxide traps, which in irradiated Si MOS was attributed to border traps.
TL;DR: In this article, a bottom-gate thin-film transistors (TFTs) with transparent zinc oxide (ZnO) channels have been developed for liquid-crystal display (LCD) with the required pattern accuracy.
Abstract: In this paper, high-performance bottom-gate thin-film transistors (TFTs) with transparent zinc oxide (ZnO) channels have been developed. The ZnO film for active channels was deposited by RF magnetron sputtering. The crystallinity of the ZnO film drastically improved when it was deposited on a doublelayer SiOx/SiNx gate insulator. In order to achieve a ZnO TFT back-plane for liquid-crystal display (LCD) with the required pattern accuracy, dry etching of the ZnO film in an Ar and CH4 chemistry has been developed. The etching rate and tapered profile of the ZnO film could be controlled by the Ar content in the etching gases of Ar and CH4. The saturation mobility (musat) of the ZnO TFT strongly depended on a gate voltage. A musat of 5.2 & cm2 .(V .s)-1 at VGS = 40 V and VDS = 10 V, and an on/off-current ratio of 2.7 x 107 were obtained. A drain-current uniformity of plusmn7% was achieved within a radius of 20 mm from the substrate center. A 1.46 -in diagonal LCD with 61 600 pixels has been driven by the ZnO-TFT back-plane. A moving picture image was available on fabricated LCD driven by the ZnO TFTs.
TL;DR: In this article, a detailed analysis and potential solutions for prolonging CMOS as the leading information technology are presented, along with the state of the art, requirements, and solutions at the level of materials, transistor, and technology.
Abstract: The paradigm and the usage of CMOS are changing, and so are the requirements at all levels, from transistor to an entire CMOS system. The traditional drivers, such as speed and density of integration, are subject to other prerogatives related to variability, manufacturability, power consumption/dissipation (mobile products!), mix of varied digital and analog/RF functions (system-on-chip integration), etc. Controllability of variations and static leakage will add to, and in certain products prevail, over speed and density. Implications at all levels are multiple and are more diverse than just speed and smallness. The goal of the authors has been to see the problem globally from the product level and to place its components in their true proportions. Therefore, we will start with drawing the product-level picture and placing it in a historical perspective. Next, we will review the state of the art, the requirements, and solutions at the level of materials, transistor, and technology. Detailed analysis and potential solutions for prolonging CMOS as the leading information technology are presented in this paper.
TL;DR: In this paper, the Kirton and Uren model has been used to analyze the power density of the mobility noise in submicrometer MOSTs and the results of their computer simulations have been shown to be ldquosubstantially different from the usual 1/ tau distribution.
Abstract: 1/f noise is a fluctuation in the conductance of semiconductors and metals. This noise could be a fluctuation in the number of free electrons or in their mobility. Many experimental studies have proved that the 1/f noise in homogeneous samples is a fluctuation in the mobility. There is a reliable empirical relation for the power density of the mobility noise. Theoretical models for mobility noise have not had much influence in the discussions. The theoretical position for number fluctuations is quite the opposite. The generally accepted McWhorter model is simple; however, very few experimental studies definitely prove number fluctuations and exclude uncorrelated mobility fluctuations. There is an extensive literature on noise in MOSTs. Submicrometer MOSTs are notorious for their high low-frequency noise. Almost all studies start from the McWhorter generation-recombination (GR) model. The discussion is confused by the many complications of the MOSTs, such as mobility degradation, surface and contacts effects, size of the samples, etc. An additional problem is that the real 1/f noise is often mixed up with other types of low-frequency noise, such as burst and GR noises. A critical discussion is given for the Kirton and Uren model. Analytical expressions are presented for the results of their computer simulations. This explains their surprising discovery that the density of McWhorter states may be ldquosubstantiallyrdquo different from the usual 1/ tau distribution.
TL;DR: In this article, a 10-band sp3d5s* semi-empirical atomistic tight-binding model coupled to a self-consistent Poisson solver is used for the dispersion calculation.
Abstract: Bandstructure effects in the electronic transport of strongly quantized silicon nanowire field-effect-transistors (FET) in various transport orientations are examined. A 10-band sp3d5s* semiempirical atomistic tight-binding model coupled to a self-consistent Poisson solver is used for the dispersion calculation. A semi-classical, ballistic FET model is used to evaluate the current-voltage characteristics. It is found that the total gate capacitance is degraded from the oxide capacitance value by 30% for wires in all the considered transport orientations (, , ). Different wire directions primarily influence the carrier velocities, which mainly determine the relative performance differences, while the total charge difference is weakly affected. The velocities depend on the effective mass and degeneracy of the dispersions. The  and secondly the  oriented 3 nm thick nanowires examined, indicate the best ON-current performance compared to  wires. The dispersion features are strong functions of quantization. Effects such as valley splitting can lift the degeneracies particularly for wires with cross section sides below 3 nm. The effective masses also change significantly with quantization, and change differently for different transport orientations. For the cases of  and  wires the masses increase with quantization, however, in the  case, the mass decreases. The mass variations can be explained from the non-parabolicities and anisotropies that reside in the first Brillouin zone of silicon.
TL;DR: In this article, the authors investigated different materials to replace ITO in inverted-staggered TFTs based on gallium-indium-zinc oxide (GIZO) semiconductor.
Abstract: During the last years, oxide semiconductors have shown that they will have a key role in the future of electronics. In fact, several research groups have already presented working devices with remarkable electrical and optical properties based on these materials, mainly thin-film transistors (TFTs). Most of these TFTs use indium-tin oxide (ITO) as the material for source/drain electrodes. This paper focuses on the investigation of different materials to replace ITO in inverted-staggered TFTs based on gallium-indium-zinc oxide (GIZO) semiconductor. The analyzed electrode materials were indium-zinc oxide, Ti, Al, Mo, and Ti/Au, with each of these materials used in two different kinds of devices: one was annealed after GIZO channel deposition but prior to source/drain deposition, and the other was annealed at the end of device production. The results show an improvement on the electrical properties when the annealing is performed at the end (for instance, with Ti/Au electrodes, mobility rises from 19 to 25 cm2/V ldr s, and turn-on voltage drops from 4 to 2 V). Using time-of-flight secondary ion mass spectrometry (TOF-SIMS), we could confirm that some diffusion exists in the source/drain electrodes/semiconductor interface, which is in close agreement with the obtained electrical properties. In addition to TOF-SIMS results for relevant elements, electrical characterization is presented for each kind of device, including the extraction of source/drain series resistances and TFT intrinsic parameters, such as (intrinsic mobility) and VTi (intrinsic threshold voltage).
TL;DR: In this article, the issues specific to both general logic and dense static random access memories are analyzed, and solutions that address their distinct design metrics are presented to manage their severe degradation.
Abstract: Minimum energy operation for digital circuits typically requires scaling the power supply below the device threshold voltage. Advanced technologies offer improved integration, performance, and active-energy efficiency for minimum energy sub-Vt circuits, but are plagued by increased variation and reduced ION/IOFF ratios, which degrade the fundamental device characteristics critical to circuit operation by several orders of magnitude. This paper investigates those characteristics and presents design methodologies and circuit topologies to manage their severe degradation. The issues specific to both general logic and dense static random access memories are analyzed, and solutions that address their distinct design metrics are presented.
TL;DR: Avalanche photodiodes (APDs) operating in Geiger mode can detect weak optical signals at high speed The implementation of APD systems in a CMOS technology makes it possible to integrate the photodetector and its peripheral circuits on the same chip as mentioned in this paper.
Abstract: Avalanche photodiodes (APDs) operating in Geiger mode can detect weak optical signals at high speed The implementation of APD systems in a CMOS technology makes it possible to integrate the photodetector and its peripheral circuits on the same chip In this paper, we have fabricated APDs of different sizes and their driving circuits in a commercial 018-mum CMOS technology The APDs are theoretically analyzed, measured, and the results are interpreted Excellent breakdown performance is measured for the 10 and 20 m APDs at 102 V The APD system is compared to the previous implementations in standard CMOS Our APD has a 55% peak probability of detection of a photon at an excess bias of 2 V, and a 30 ns dead time, which is better than the previously reported results
TL;DR: In this article, the Schottky barrier height (SBH) of the contact systems of NiSi and PtSi was compared with two different schemes used to incorporate a high concentration of dopants at the silicide/silicon interface.
Abstract: An experimental study is presented to compare two different schemes used to incorporate a high concentration of dopants at the silicide/silicon interface for NiSi and PtSi, i.e., dopant segregation, with the purpose of lowering the Schottky barrier height (SBH) of the contact systems. Specifically, the interfacial dopant is introduced either through silicidation-induced dopant segregation (SIDS) or by silicide as diffusion source (SADS). For the latter, a postimplantation drive-in anneal is needed. For both silicide systems, the dopant segregation gives rise to a predominant effect, leading to an effective SBH that is independent of the original SBHs of PtSi and NiSi, which differs by 0.2 eV. Scheme SIDS is relatively simple in processing, but the silicidation process is dopant-dependent, leading to local variations of silicide formation. Scheme SADS addresses the adverse effect of dopant on silicidation by separating silicidation from dopant incorporation.
TL;DR: The current technology status for realizing the GAA NW device structures and their applications in logic circuit and nonvolatile memories are reviewed and the challenges and opportunities are outlined.
Abstract: Nanowire (NW) devices, particularly the gate-all-around (GAA) CMOS architecture, have emerged as the front-runner for pushing CMOS scaling beyond the roadmap. These devices offer unique advantages over their planar counterparts which make them feasible as an option for 22 -nm and beyond technology nodes. This paper reviews the current technology status for realizing the GAA NW device structures and their applications in logic circuit and nonvolatile memories. We also take a glimpse into applications of NWs in the ldquomore-than-Moorerdquo regime and briefly discuss the application of NWs as biochemical sensors. Finally, we summarize the status and outline the challenges and opportunities of the NW technology.
TL;DR: In this paper, the performances of carbon nanotube (CNT) interconnects, both single and multiwall (SWNT and MWNT), are benchmarked against their copper counterparts at a realistic operating temperature (100degC).
Abstract: Using physics-based circuit models, the performances of carbon nanotube (CNT) interconnects, both single- and multiwall (SWNT and MWNT), are benchmarked against their copper counterparts at a realistic operating temperature (100degC). The models used capture various electron phonon scattering mechanisms and the dependence of quantum conductance on temperature and diameter. It is demonstrated that any performance comparison between CNT and copper wires needs to be done at realistic temperatures because changes in temperature affect copper and CNT interconnects quite differently. The results of this paper demonstrate that a hybrid system of copper/SWNT/MWNT offers the highest performance enhancement for interconnects.
TL;DR: In this article, a comprehensive physical model for the analysis, characterization, and design of 4H-silicon carbide (SiC) MOSFETs has been developed.
Abstract: A comprehensive physical model for the analysis, characterization, and design of 4H-silicon carbide (SiC) MOSFETs has been developed. The model has been verified for an extensive range of bias conditions and temperatures. It incorporates details of interface trap densities, Coulombic interface trap scattering, surface roughness scattering, phonon scattering, velocity saturation, and their dependences on bias and temperature. The physics-based models were implemented into our device simulator that is tailored for 4H-SiC MOSFET analysis. By using a methodology of numerical modeling, simulation, and close correlation with experimental data, values for various physical parameters governing the operation of 4H-SiC MOSFETs, including the temperature-dependent interface trap density of states, the root-mean-square height and correlation length of the surface roughness, and the electron saturation velocity in the channel and its dependence on temperature, have been extracted. Coulomb scattering and surface roughness scattering limit surface mobility for a wide range of temperatures in the subthreshold and linear regions of device operation, whereas the saturation velocity and the high-field mobility limit current in the saturation region.
TL;DR: In this article, an atomistic 3D simulation study of the performance of graphene-nanoribbon (GNR) Schottky-barrier field effect transistors and transistors with doped reservoirs (MOSFETs) was presented.
Abstract: We present an atomistic 3-D simulation study of the performance of graphene-nanoribbon (GNR) Schottky-barrier field-effect transistors (SBFETs) and transistors with doped reservoirs (MOSFETs) by means of the self-consistent solution of the Poisson and Schrodinger equations within the nonequilibrium Green's function (NEGF) formalism Ideal MOSFETs show slightly better electrical performance for both digital and terahertz applications The impact of nonidealities on device performance has been investigated, taking into account the presence of single vacancy, edge roughness, and ionized impurities along the channel In general, MOSFETs show more robust characteristics than SBFETs Edge roughness and single-vacancy defect largely affect the performance of both device types
TL;DR: The ability of semiconducting nanowire (NW) field effect transistors (FETs) to serve as highly sensitive label-free sensors for biochemicals, including small molecules, proteins, and nucleic acids, was demonstrated in this article.
Abstract: Recent studies have demonstrated the ability of semiconducting nanowire (NW) field-effect transistors (FETs) to serve as highly sensitive label-free sensors for biochemicals, including small molecules, proteins, and nucleic acids. The nanoscale confinement of the channel current in concert with the large-surface area-to-volume ratio enables charged molecules bound to the surface to effectively gate the device. Functionalization of the NW surface with specific receptors therefore enables direct electronic detection of particular molecules of interest. The original work in the field relied on NWs grown by the chemical vapor deposition method, which require hybrid bottom-up fabrication processes for device realization. The lack of reproducibility with these techniques and the associated inability to leverage the central advantage of complementary MOSFETs, namely, very large scale integration, have recently led a number of groups to create NW sensors using only traditional top-down fabrication techniques. In this paper, we focus primarily on these most recent studies and discuss necessary future studies as dictated by experimental and theoretical considerations.
TL;DR: In this article, an approach for matching the transconductance characteristics of CMOS ISFET arrays by removing trapped charge has been presented, which can be applied directly to a prototype single-chip 2 2 array of IsFETs.
Abstract: This paper presents an approach for matching the transconductance characteristics of CMOS ISFET arrays by removing trapped charge. We describe how to design arrays of floating-gate ISFETs so that ultraviolet (UV) radiation and bulk-substrate biasing can be used to remove the random amount of trapped charge that accumulates on the gates during fabrication. The approach is applied directly to a prototype single-chip 2 2 array of ISFETs, which is designed and fabricated in a standard 0.35- CMOS process. By considering the transconductance characteristics of the 2 2 array before and after UV exposure, it is shown that the response can be matched after 10 h and that the ISFET threshold voltages converge to an equilibrium value of approximately 1 V. After matching, it is found that the ISFET array has a measured sensitivity of 46 mV/pH and can successfully image a change in the pH of a homogeneous electrolyte solution.
TL;DR: In this paper, an enhancement of punchthrough voltage in AlGaN/GaN high-electron-mobility transistors was presented by increasing the electron confinement in the transistor channel using an AlGAN buffer-layer structure.
Abstract: In this paper, we present an enhancement of punchthrough voltage in AlGaN/GaN high-electron-mobility-transistor devices by increasing the electron confinement in the transistor channel using an AlGaN buffer-layer structure. An optimized electron confinement results in a scaling of punchthrough voltage with device geometry and a significantly reduced subthreshold drain leakage current. These beneficial properties are pronounced even further if gate-recess technology is applied for device fabrication. Physical-based device simulations give insight in the respective electronic mechanisms.
TL;DR: In this article, the scaling of nanowire transistors to 10-nm gate lengths and below is considered and compared with the published experimental data of nan-wire transistors, and the performance limit of a nan-ire transistor is assessed by applying a ballistic current model.
Abstract: This paper considers the scaling of nanowire transistors to 10-nm gate lengths and below. The 2-D scale length theory for a cylindrical surrounding-gate MOSFET is reviewed first, yielding a general guideline between the gate length and the nanowire size for acceptable short-channel effects. Quantum confinement of electrons in the nanowire is discussed next. It gives rise to a ground-state energy and, therefore, a threshold voltage dependent on the radius of the nanowire. The scaling limit of nanowire transistors hinges on how precise the nanowire size can be controlled. The performance limit of a nanowire transistor is then assessed by applying a ballistic current model. Key issues such as the density of states of the nanowire material are discussed. Comparisons are made between the model results and the published experimental data of nanowire devices.
TL;DR: In this paper, high-electric-field degradation phenomena are investigated in GaN-capped AlGaN/GaN HEMTs by comparing experimental data with numerical device simulations.
Abstract: High-electric-field degradation phenomena are investigated in GaN-capped AlGaN/GaN HEMTs by comparing experimental data with numerical device simulations. Under power- and OFF-state conditions, 150-h DC stresses were carried out. Degradation effects characterizing both stress experiments were as follows: a drop in the dc drain current, the amplification of gate-lag effects, and a decrease in the reverse gate leakage current. Numerical simulations indicate that the simultaneous generation of surface (and/or barrier) and buffer traps can account for all of the aforementioned degradation modes. Experiments also showed that the power-state stress induced a drop in the transconductance at high gate-source voltages only, whereas the OFF-state stress led to a uniform transconductance drop over the entire gate-source-voltage range. This behavior can be reproduced by simulations provided that, under the power-state stress, traps are assumed to accumulate over a wide region extending laterally from the gate edge toward the drain contact, whereas, under the OFF-state stress, trap generation is supposed to take place in a narrower portion of the drain-access region close to the gate edge and to be accompanied by a significant degradation of the channel transport parameters.
TL;DR: A general procedure to find the optimum-cell geometry is proposed and applied to a prototype vertical cell, and the evolution of program and read performances through technology nodes is analyzed by numerical simulations with the aid of an analytical model.
Abstract: One of the major concerns for the feasibility of phase-change memories is the reduction of the programming current. To this aim, several efforts have been dedicated both on cell geometry and on material engineering. This paper addresses programming-current minimization by the optimization of the cell geometry and materials, programming-current scaling, and the tradeoff between programming and readout performances of the cell. A general procedure to find the optimum-cell geometry is proposed and applied to a prototype vertical cell. Then, the evolution of program and read performances through technology nodes is analyzed by numerical simulations with the aid of an analytical model, for both the isotropic- and nonisotropic-scaling approaches. The two scaling approaches are discussed and compared in terms of program and read cell performances. Finally, material optimization is considered for further program-read improvement.
TL;DR: In this article, a probabilistic superposition of elementary Markov processes describing the trapping/detrapping events taking place in the cell tunnel oxide was proposed to explain the main features of the random telegraph noise threshold-voltage instability.
Abstract: This paper presents a new physics-based statistical model for random telegraph noise in Flash memories. From the probabilistic superposition of elementary Markov processes describing the trapping/detrapping events taking place in the cell tunnel oxide, the model can explain the main features of the random telegraph noise threshold-voltage instability. The results on the statistical distribution of the threshold-voltage difference between two subsequent read accesses show good agreement between measurements and model predictions, even considering the time drift of the distribution tails. Moreover, the model gives a detailed spectroscopic analysis of the oxide defects responsible for the random telegraph noise, allowing a spatial and energetic localization of the traps involved in the threshold-voltage instability process.
TL;DR: In this article, a 2-D drift-diffusion electrothermal simulation, using an electron transport model calibrated against Monte Carlo simulations at various temperatures, is employed to analyze the impact of thermal effects on the operation of nanoscale SOI n-MOSFETs.
Abstract: This paper discusses self-heating (SHE) effects in silicon-on-insulator (SOI) CMOS technology and applies device simulation to analyze the impact of thermal effects on the operation of nanoscale SOI n-MOSFETs A 2-D drift-diffusion electrothermal simulation, using an electron transport model calibrated against Monte Carlo simulations at various temperatures, is employed in the analysis We report the effects of device-structure parameters, such as SOI layer thickness, buried-oxide (BOX) thickness, source/drain (S/D) extension length, and thickness of the elevated S/D region, on the SHE of nanoscale MOSFETs The SHE effects become significant due to the adoption of thin silicon layers and to the low thermal conductivity of the BOX, leading to the rise of large temperature under nominal operation conditions for high-performance digital circuits The ac performance of SOI MOSFETs is influenced as well, and in particular, a severe degradation of the cutoff frequency of very short MOSFETs is predicted by numerical electrothermal device simulations Although the effects of SHE on device performance are found to be somewhat modest and might be mitigated through device design, they may result in a degradation of the long-term reliability
TL;DR: In this article, the authors investigated the impact of device scaling to 45 nm and beyond on noise margins, delay, and energy in sub-Vth circuits and proposed an alternative scaling strategy.
Abstract: Subthreshold circuit design is promising for future ultralow-energy sensor applications as well as highly parallel high-performance processing. Device scaling has the potential to increase speed in addition to decreasing both energy and cost in subthreshold circuits. However, no study has yet considered whether device scaling to 45 nm and beyond will be beneficial for subthreshold logic. We investigate the implications of device scaling on subthreshold logic and SRAM and And that the slow scaling of gate-oxide thickness leads to a 60% reduction in Ion/Ioff between the 90- and 32-nm device generations. We highlight the effects of this device degradation on noise margins, delay, and energy. We subsequently propose an alternative scaling strategy and demonstrate significant improvements in noise margins, delay, and energy in sub-Vth circuits. Using both optimized and unoptimized subthreshold device models, we explore the robustness of scaled subthreshold SRAM. We use a simple variability model and find that even small memories become unstable at advanced technology nodes. However, the simple device optimizations suggested in this paper can be used to improve nominal read noise margins by 64% at the 32-nm node.
TL;DR: In this paper, the authors develop comprehensive modeling and design techniques for carbon nanotube (CNT)-based interconnects, which they utilize to examine the performance, reliability, and fabrication requirements for future CNT-based solutions.
Abstract: In this paper, we develop comprehensive modeling and design techniques for carbon nanotube (CNT)-based interconnects, which we utilize to examine the performance, reliability, and fabrication requirements for future nanotube-based interconnect solutions. We create a generalized model for CNT-based interconnect systems that achieves a high degree of accuracy compared to experimental CNT measurements. Leveraging the model, we develop the first closed-form formulation for the optimal nanotube diameter and bundle height for multi-walled CNT (MWCNT) and single-walled CNT (SWCNT) bundle interconnects for a general set of geometric and process parameters. The results indicate that the proposed design method decreases delay by 21% and 29% on average compared to nonoptimized MWCNT and SWCNT bundles. We also find that future CNT bundle fabrication processes must achieve a nanotube area coverage of at least 30% for optimized CNT bundles and 40% for nonoptimized CNT bundles to obtain competitive performance results compared to copper interconnects. In terms of reliability, we find that large diameter MWCNT bundles are significantly more susceptible to process variations than SWCNT bundles, which will have important implications for their utilization in future nanoscale integrated circuits.