Showing papers in "IEEE Transactions on Electron Devices in 2009"

Self-Accelerated Thermal Dissolution Model for Reset Programming in Unipolar Resistive-Switching Memory (RRAM) Devices

Abstract: This paper addresses the numerical modeling of reset programming in NiO-based resistive-switching memory. In our model, we simulate electrical conduction and heating in the conductive filament (CF), which controls the resistance of the low resistive (or set) state, accounting for CF thermal-activated dissolution. Employing CF electrical and thermal parameters, which were previously characterized on our NiO-based samples, our calculations are shown to match experimental reset and retention characteristics. Simulations show that reset transition is self-accelerated as a consequence of a positive feedback between the thermal dissolution of the CF and local Joule heating in the CF bottleneck, which can account for the abrupt resistance transition in experimental data. Finally, the model is used to investigate the reduction of the reset current, which is needed for device application.

Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status, and Prospects

Abstract: This paper reviews the current state of research in carbon-based nanomaterials, particularly the one-dimensional (1-D) forms, carbon nanotubes (CNTs) and graphene nanoribbons (GNRs), whose promising electrical, thermal, and mechanical properties make them attractive candidates for next-generation integrated circuit (IC) applications. After summarizing the basic physics of these materials, the state of the art of their interconnect-related fabrication and modeling efforts is reviewed. Both electrical and thermal modeling and performance analysis for various CNT- and GNR-based interconnects are presented and compared with conventional interconnect materials to provide guidelines for their prospective applications. It is shown that single-walled, double-walled, and multiwalled CNTs can provide better performance than that of Cu. However, in order to make GNR interconnects comparable with Cu or CNT interconnects, both intercalation doping and high edge-specularity must be achieved. Thermal analysis of CNTs shows significant advantages in tall vias, indicating their promising application as through-silicon vias in 3-D ICs. In addition to on-chip interconnects, various applications exploiting the low-dimensional properties of these nanomaterials are discussed. These include chip-to-packaging interconnects as well as passive devices for future generations of IC technology. Specifically, the small form factor of CNTs and reduced skin effect in CNT interconnects have significant implications for the design of on-chip capacitors and inductors, respectively.

Performance Comparison Between p-i-n Tunneling Transistors and Conventional MOSFETs

Abstract: In this paper, we present a detailed performance comparison between conventional n-i-n MOSFET transistors and tunneling field-effect transistors (TFETs) based on the p-i-n geometry, using semiconducting carbon nanotubes as the model channel material. Quantum-transport simulations are performed using the nonequilibrium Green's function formalism considering realistic phonon-scattering and band-to-band tunneling mechanisms. Simulations show that TFETs have a smaller quantum capacitance at most gate biases. Despite lower on-current, they can switch faster in a range of on/off-current ratios. Switching energy for TFETs is observed to be fundamentally smaller than that for MOSFETs, leading to lower dynamic power dissipation. Furthermore, the beneficial features of TFETs are retained with different bandgap materials. These reasons suggest that the p-i-n TFET is well suited for low-power applications.

Modeling, Analysis, and Design of Graphene Nano-Ribbon Interconnects

Abstract: Graphene nanoribbons (GNRs) are considered as a prospective interconnect material. A comprehensive conductance and delay analysis of GNR interconnects is presented in this paper. Using a simple tight-binding model and the linear response Landauer formula, the conductance model of GNR is derived. Several GNR structures are examined, and the conductance among them and other interconnect materials [e.g., copper (Cu), tungsten (W), and carbon nanotubes (CNTs)] is compared. The impact of different model parameters (i.e., bandgap, mean free path, Fermi level, and edge specularity) on the conductance is discussed. Both global and local GNR interconnect delays are analyzed using an RLC equivalent circuit model. Intercalation doping for multilayer GNRs is proposed, and it is shown that in order to match (or better) the performance of Cu or CNT bundles at either the global or local level, multiple zigzag-edged GNR layers along with proper intercalation doping must be used and near-specular nanoribbon edge should be achieved. However, intercalation-doped multilayer zigzag GNRs can have better performance than that of W, implying possible application as local interconnects in some cases. Thus, this paper identifies the on-chip interconnect domains where GNRs can be employed and provides valuable insights into the process technology development for GNR interconnects.

Filament Conduction and Reset Mechanism in NiO-Based Resistive-Switching Memory (RRAM) Devices

Abstract: The physical understanding of the programming and reliability mechanisms in resistive-switching memory devices requires a detailed characterization of the electrical and thermal conduction properties in the low-resistance state of the memory cell. The aim of this paper is the characterization of the conductive filament (CF), which controls the localized current flow in the low resistive state of the cell. Based on a new technique for evaluating the CF temperature during operation, we perform a statistical characterization of the critical filament temperature for the reset operation, i.e., the transition to the high-resistance state by the thermal dissolution of the CF. The thermal resistance of the CF and the activation energy for the dissolution mechanism are then evaluated, allowing for a physics-based numerical modeling of the reset operation based on CF thermal breakup.

Study of Multilevel Programming in Programmable Metallization Cell (PMC) Memory

Abstract: Programmable metallization cell (PMC) memory, also known as conductive bridging RAM (CBRAM), is a resistive-switching memory based on non-volatile formation and dissolution of a conductive filament (CF) in a solid electrolyte. Although ease of fabrication, promising performance and multilevel (ML) capability make the PMC a possible candidate for post-flash non-volatile memories, further physical understanding is required to better assess its true potential. In this work, we investigate the kinetics involved in the programming operation (i.e., transition from the high resistance to the low resistance state), which occurs by voltage-driven ion migration and electrochemical deposition, and results in CF formation and growth. The main kinetic parameters controlling the programming operation are extracted from our electrical data. Also, CF growth and corresponding resistance decrease is shown to be controllable with reasonable accuracy in pulse mode by employing a variable load resistance which can dynamically control the programming kinetics. A semi-analytical physical model is shown to account for experimental data and allows for the engineering of fast and reliable ML programming in one transistor-one resistor (1T-1R) devices.

Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits

Abstract: In this paper, novel n- and p-type tunnel field-effect transistors (T-FETs) based on heterostructure Si/intrinsic-SiGe channel layer are proposed, which exhibit very small subthreshold swings, as well as low threshold voltages. The design parameters for improvement of the characteristics of the devices are studied and optimized based on the theoretical principles and simulation results. The proposed devices are designed to have extremely low off currents on the order of 1 fA/mum and engineered to exhibit substantially higher on currents compared with previously reported T-FET devices. Subthreshold swings as low as 15 mV/dec and threshold voltages as low as 0.13 V are achieved in these devices. Moreover, the T-FETs are designed to exhibit input and output characteristics compatible with CMOS-type digital-circuit applications. Using the proposed n- and p-type devices, the implementation of an inverter circuit based on T-FETs is reported. The performance of the T-FET-based inverter is compared with the 65-nm low-power CMOS-based inverter, and a gain of ~104 is achieved in static power consumption for the T-FET-based inverter with smaller gate delay.

Compact Physics-Based Circuit Models for Graphene Nanoribbon Interconnects

Abstract: Physics-based equivalent circuit models are presented for armchair and zigzag graphene nanoribbons (GNRs), and their conductances have been benchmarked against those of carbon nanotubes and copper wires. Atomically thick GNRs with smooth edges can potentially have smaller resistances compared with copper wires with unity aspect ratios for widths below 8 nm and stacks of noninteracting GNRs can have substantially smaller resistivities compared to Cu wires. It is shown that rough edges can increase the resistance of narrow GNRs by an order of magnitude. This fact highlights the need for patterning methods that can produce relatively smooth edges to fabricate low resistance GNR interconnects.

Organic Thin-Film Transistors: Part I—Compact DC Modeling

Abstract: A generic analytical model for the current-voltage characteristics of organic thin-film transistors (OTFTs) is derived. Based on this generic model, a TFT compact dc model that meets the requirements for compact modeling, including for computer circuit simulators, is proposed. The models are fully symmetrical, and the TFT compact dc model covers all regimes of TFT operation-linear and saturation above threshold, subthreshold, and reverse biasing. The empirical fitting parameters are mostly eliminated from the characteristic equations. The developed models are also in close correspondence to several physical, parametric, and limiting models for current-voltage and mobility characteristics. An essential practical feature of the TFT compact dc model is that the model is both upgradable and reducible, allowing for easier implementation and modifications and also simultaneously allowing for separation of characterization techniques. This allows for systematic fitting of experimental data with large scattering in the values, but at the same time, preserving consistently the OTFT behavior in the model.

A Simple Semiempirical Short-Channel MOSFET Current–Voltage Model Continuous Across All Regions of Operation and Employing Only Physical Parameters

Abstract: A simple semiempirical model ID(VGS, VDS) for short-channel MOSFETs applicable in all regions of device operation is presented. The model is based on the so-called ldquotop-of-the-barrier-transportrdquo model, and we refer to it as the ldquovirtual sourcerdquo (VS) model. The simplicity of the model comes from the fact that only ten parameters are used. Of these parameters, six are directly obtainable from standard device measurements: 1) gate capacitance in strong inversion conditions (typically at maximum voltage VGS = Vdd); 2) subthreshold swing; 3) drain-induced barrier lowering (DIBL) coefficient; 4) current in weak inversion (typically Ioff at VGS = 0 V) and at high VDS; 5) total resistance at VDS = 0 V and VGS = Vdd and 6), effective channel length. Three fitted physical parameters are as follows: 1) carrier low-field effective mobility; 2) parasitic source/drain resistance, 3) the saturation region carrier velocity at the so-called virtual source. Lastly, a constrained saturation-transition-region empirical parameter is also fitted. The modeled current versus voltage characteristics and their derivatives are continuous from weak to strong inversion and from the linear to saturation regimes of operation. Remarkable agreement with published state-of-the-art planar short-channel strained devices is demonstrated using physically meaningful values of the fitted physical parameters. Moreover, the model allows for good physical insight in device performance properties, such as extraction of the VSV, which is a parameter of critical technological importance that allows for continued MOSFET performance scaling. The simplicity of the model and the fact that it only uses physically meaningful parameters provides an easy way for technology benchmarking and performance projection.

Comprehensive Analysis of Random Telegraph Noise Instability and Its Scaling in Deca–Nanometer Flash Memories

Abstract: This paper presents a comprehensive investigation of random telegraph noise (RTN) in deca-nanometer Flash memories, considering both the nor and the nand architecture. The statistical distribution of the threshold voltage instability is analyzed in detail, evidencing that the slope of its exponential tails is the critical parameter determining the scaling trend for RTN. By means of 3-D TCAD simulations, the slope is shown to be the result of cell geometry, atomistic substrate doping, and random placement of traps over the cell active area. Finally, the slope dependence on cell geometry (width, length, and oxide thickness), doping, and bias conditions is summarized in a powerful formula that is able to predict the RTN instabilities in deca-nanometer Flash memories.

Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance

Abstract: Closed-form expressions of the resistance, capacitance, and inductance for interplane 3-D vias are presented in this paper. The closed-form expressions account for the 3-D via length, diameter, dielectric thickness, and spacing to ground. A 3-D numerical simulation is used to extract electromagnetic solutions of the resistance, capacitance, and inductance for comparison with the closed-form expressions, revealing good agreement between simulation and the physical models. The maximum error for the resistance, capacitance, and inductance is less than 8%.

Effective Capacitance and Drive Current for Tunnel FET (TFET) CV/I Estimation

Abstract: Through mixed-mode device and circuit simulation, this paper provides an estimate of the effective output capacitance (C EFF) and drive current (I EFF) for delay (tauf = 0.69 R sw C EFF, where R sw = V DD/2 I EFF) estimation of unloaded tunnel field-effect transistor (TFET) inverters. It is shown that unlike MOSFET inverters, where C EFF is approximately equal to the gate capacitance (C gg) , in TFET inverters, the output capacitance can be as high as 2.6 times the gate capacitance. A three-point model is proposed to extract the effective drive current from the real-time switching current trajectory in a TFET inverter.

Reliability Impact of Chalcogenide-Structure Relaxation in Phase-Change Memory (PCM) Cells—Part I: Experimental Study

Abstract: The phase-change memory (PCM) relies on the electrical properties of the chalcogenide materials to represent the stored bit of information. As a result, data stability depends on structural relaxation (SR) in the amorphous chalcogenide phase, which results in a temperature-accelerated time evolution of the electrical properties of the active material. Here, we address the time, temperature, and bias dependence of SR effects on the amorphous Ge2Sb2Te5 (GST) material used in PCM cells. Electrical measurements for increasing annealing time and temperature indicate that SR can be described by a defect annihilation process in the amorphous chalcogenide material. Finally, the stability of chalcogenide resistance as a function of the read conditions is discussed, for the purpose of reducing the impact of SR on the reliability of PCM devices.

Constant-Voltage-Bias Stress Testing of a-IGZO Thin-Film Transistors

Abstract: Constant-voltage-bias (VDS = VGS = 30 V) stress measurements are performed for a period of 105 s on thin-film transistors (TFTs) with amorphous indium-gallium-zinc-oxide (IGZO) channel layers fabricated via RF sputtering using a postdeposition annealing temperature of 200degC, 250degC, or 300degC. Thermal silicon dioxide is employed as a TFT bottom-gate insulator. All SiO2/IGZO TFTs tested exhibit the following: 1) a positive rigid log(ID)- VGS transfer curve shift; 2) a continuous drain-current decrease over the entire stress duration; and 3) recovery of the log(ID)-VGS transfer curve toward the prestressed state when the stressed TFT is left unbiased in the dark at room temperature for an extended period of time. The SiO2/IGZO TFTs subjected to a higher postdeposition annealing temperature are more stable. A small (and typically negligible) amount of clockwise hysteresis is present in the log(ID) -VGS transfer curves of IGZO TFTs. These instability and hysteresis observations are consistent with a SiO2/ IGZO TFT instability mechanism involving electron trapping within the IGZO channel layer.

Resistive Switching Characteristics of Sol–Gel Zinc Oxide Films for Flexible Memory Applications

Abstract: Unipolar resistive switching devices are investigated for nonvolatile memory applications in a metal-insulator-metal structure in which the insulator layer is based on sol-gel-derived zinc oxide (ZnO) films prepared by a simple spin-coating process followed by thermal annealing. Fast programming ( les 50 ns) and a high off-to-on resistance ratio ( ges 104) is demonstrated. The influences on the switching behaviors according to the crystallinity of the ZnO films are studied as a function of the annealing temperature. In addition, the devices are fabricated on a flexible plastic substrate and exhibit excellent durability upon repeated bending tests, demonstrating their potential for flexible low-cost memory devices.

High-Frequency Analysis of Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design

Abstract: This paper presents a rigorous investigation of high-frequency effects in carbon nanotube (CNT) interconnects and their implications for the design and performance analysis of high-quality on-chip inductors. A frequency-dependent impedance extraction method is developed for both single-walled CNT (SWCNT) and multiwalled CNT (MWCNT) bundle interconnects. The method is subsequently verified by comparing the results with those derived directly from the Maxwell's equations. Our analysis reveals for the first time that skin effect in CNT (particularly MWCNT) bundles is significantly reduced compared to that in conventional metal conductors, which makes them very attractive and promising material for high-frequency applications, including high-quality (Q) factor on-chip inductor design in high-performance RF/mixed-signal circuits. It is shown that such unique high-frequency properties of CNTs essentially arise due to their large momentum relaxation time (leading to their large kinetic inductance), which causes the skin depths to saturate with frequency and thereby limits resistance increase at high frequencies in a bundle structure. It is subsequently shown that CNT-based planar spiral inductors can achieve more than three times higher Q factor than their Cu-based counterparts without using any magnetic materials or Q factor enhancement techniques.

Density of States of a-InGaZnO From Temperature-Dependent Field-Effect Studies

Abstract: Temperature-dependent field-effect measurements were performed on radio-frequency sputtered amorphous In-Ga-Zn-O thin film transistors (TFTs). We studied the effect of temperature on the TFT electrical properties. We observed that the field-effect mobility (mu) increases and the threshold voltage (V T) shifts negatively with temperature, while the current on-off ratio and subthreshold slope (S) remain almost unchanged. We also observed that the TFT drain current (ID) is thermally activated, and the relation between the prefactor (ID0) and activation energy (E a) obeys the Meyer-Neldel rule. The density of localized gap states (DOS) was then calculated by using a self-consistent method based on the experimentally obtained E a. The result shows good agreement with the DOS distribution calculated from SPICE simulations.

100 W Operation of a Cold Cathode TWT

Abstract: Recent demonstration of low-voltage high-transconductance field emitter array operation holds promise for the successful development of reliable cold cathode vacuum electronics device technologies. This paper reports on the experimental studies of implementation of such field emitter arrays as the electron source for a moderate power traveling wave tube (TWT) operating in the C-band frequency regime. The cold cathode TWT has operated for over 150 h at duty factors up to 10%, beam currents up to 121 mA, and RF powers up to 100 W at 5 GHz. High cathode current densities of 15.4 A/cm2 were achieved concurrent with excellent beam control, resulting in 99.4% beam transmission under zero-RF-drive operating conditions and 97.3% transmission at maximum RF output power. The cathode is shown to operate with a 72% reduction in the operating voltage from the previous generation of emitters fabricated by SRI International, bringing the operating voltage for full current operation well below 100 V. Extensive device characterization and life testing has been performed, and interesting variation in cathode performance was observed during the high-duty high-current portion of the testing program. The results presented here represent the highest current, highest power, and highest duty factor ever reported for an RF vacuum device employing a field emission cold cathode electron source.

Conductance Asymmetry of Graphene p-n Junction

Abstract: We use the nonequilibrium Green function method in the ballistic limit to provide a quantitative description of the conductance of graphene p-n junctions - an important building block for graphene electronics devices. In this paper, recent experiments on graphene junctions are explained by a ballistic transport model, but only if the finite junction transition width D w is accounted for. In particular, the experimentally observed anomalous increase in the resistance asymmetry between n-n and n-p junctions under low source/drain charge density conditions is also quantitatively captured by our model. In light of the requirement for sharp junctions in applications such as electron focusing, we also examine the p-n junction conductance in the regime where D w is small and find that wave-function mismatch (so-called pseudospin) plays a major role in sharp p-n junctions.

Crosstalk Prediction of Single- and Double-Walled Carbon-Nanotube (SWCNT/DWCNT) Bundle Interconnects

Abstract: The crosstalk effects in single- and double-walled carbon-nanotube (SWCNT and DWCNT) bundle-interconnect architectures are investigated in this paper. Some modified equivalent-circuit models are proposed for both SWCNT and DWCNT bundles, where capacitive couplings between adjacent bundles are incorporated. These circuit models are further used to predict the performance of SWCNT and DWCNT bundle interconnects in comparison with the Cu wire counterpart at all interconnect levels for advanced future technology generations. It is found that, compared with the SWCNT bundle, the DWCNT bundle interconnect can lead to a reduction of crosstalk-induced time delay, which will be more significant with increasing bundle length, while the peak voltage of the crosstalk-induced glitch in SWCNT and DWCNT bundle interconnects is in the same order as that of Cu wires. Due to the improvement in time delay, it is numerically confirmed that the DWCNT bundle interconnect will be more suitable for the next generation of interconnect technology as compared with the SWCNT bundle counterpart.

Printed Nonvolatile Memory for a Sheet-Type Communication System

Abstract: By using state-of-the-art printing technologies and functional inks, we have demonstrated organic nonvolatile flexible random-access-memory matrices with a nondestructive read-out capability and a time-continuous current output; these functionalities have not been simultaneously achieved even by silicon-based conventional memory. A memory cell comprising three transistors becomes possible with inkjet printing and other solution-based processes, which can use ferroelectric copolymer ink comprising poly(vinylidenefluoride-co-trifluoroethylene) and insulating ink comprising polyimide precursors properly within the planer plastic substrate. A large ldquo1 : 0rdquo current ratio of 105 is observed in air when it is annealed at 135degC , which is sufficiently low to be compatible with many plastic substrates. When stored in air, the ldquo1 : 0rdquo ratio was still 104 after 15 days and 103 after 5 months, which is sufficient for practical applications. Furthermore, human-scale communication sheets were manufactured as the first demonstration utilizing large-area organic memories.

Wide-Dynamic-Range CMOS Image Sensors—Comparative Performance Analysis

Abstract: A large variety of solutions for widening the dynamic range (DR) of CMOS image sensors has been proposed throughout the years. We propose a set of criteria upon which an effective comparative analysis of the performance of wide-DR (WDR) sensors can be done. Sensors for WDR are divided into seven categories: 1) companding sensors; 2) multimode sensors; 3) clipping sensors; 4) frequency-based sensors; 5) time-to-saturation (time-to-first spike) sensors; 6) global-control-over-the-integration-time sensors; and 7) autonomous-control-over-the-integration-time sensors. The comparative analysis for each category is based upon the quantitative assessments of the following parameters: signal-to-noise ratio, DR extension, noise floor, minimal transistor count, and sensitivity. These parameters are assessed using consistent assumptions and definitions, which are common to all WDR sensor categories. The advantages and disadvantages of each category in the sense of power consumption and data rate are discussed qualitatively. The influence of technology advancements on the proposed set of criteria is discussed as well.

Measurement of Channel Temperature in GaN High-Electron Mobility Transistors

Abstract: In this paper, a simple and reliable method to estimate the channel temperature of GaN high-electron mobility transistors (HEMTs) is proposed. The technique is based on electrical measurements of performance-related figures of merit (I Dmax and R ON) with a synchronized pulsed I -V setup. As our technique involves only electrical measurement, no special design in device geometry is required, and packaged devices can be measured. We apply this technique to different device structures and validate its sensitivity and robustness.

Phase-Shifted Traveling-Wave-Tube Circuit for Ultrawideband High-Power Submillimeter-Wave Generation

Abstract: A novel slow-wave vacuum electron device circuit, consisting of a half-period-staggered double-vane array and a high-aspect ratio sheet electron beam, has been conceived for a high-power wideband submillimeter-wave generation. A particle-in-cell simulation, which is based on a finite-difference time-domain algorithm, has shown that this circuit has a very wide intrinsic bandwidth (in excess of 50 GHz around the operating frequency of 220 GHz) with a moderate gain of 13 dB/cm. Moreover, the saturated conversion efficiency is predicted to be 3%-5.5% over the operating band corresponding to an output power of 150-275 W, assuming a beam power of 5 kW. Of particular importance, this structure is based on the TE-fundamental mode interaction, thereby avoiding the complex over moding instabilities that usually cause spurious signal oscillation in conventional high-aspect-ratio structures. This planar circuit has simple 2-D geometry that is thermally and mechanically robust as well as being compatible with conventional microfabrication techniques. This concept is expected to open numerous opportunities in potential applications of versatile electronic devices in the low-millimeter- and submillimeter-wave regions.

High-Voltage GaAs Photovoltaic Laser Power Converters

Abstract: The main drawback of photovoltaic (PV) laser power converters based on GaAs material is the low output voltage, which is often insufficient to power electronic circuits directly. Aside from the use of a dc-dc converter in combination with a single PV converter, it is possible to boost the voltage by the monolithic serial interconnection of several converter segments on a single chip, often called multiple converters. Another novel approach introduced in this paper is a multijunction PV cell, where several subcells of the same material are stacked onto a substrate and interconnected by interband tunnel diodes. This paper explores a tandem GaAs-GaAs converter and compares the results with a 2-V multiple PV converter under monochromatic laser illumination. In addition, 4-V multiple PV converters with maximum monochromatic efficiencies (810 nm) of up to 50.1% at 51.6 W/cm2 and 6-V converters are investigated. Thereby, the fabrication technology of the devices is outlined and the influence of inhomogeneous illumination on the performance of these energy converters is discussed.

A High-Speed CMOS Image Sensor With Column-Parallel Two-Step Single-Slope ADCs

Abstract: This paper proposes a column-parallel two-step single-slope (SS) ADC for high-speed CMOS image sensors. Error correction scheme to improve the linearity is proposed as well. A prototype sensor of 320 times 240 pixels has been fabricated with a 0.35-mum CMOS process. Measurement results demonstrate that the proposed ADC can achieve the conversion time of 4 mus , which is ten times faster than the conventional SS ADC. The proposed error correction effectively removes the dead band problem and yields DNL of +0.53/ -0.78 LSB and INL of +1.42/ -1.61 LSB. The power consumption is 36 mW from a supply voltage of 2.8 V.

A High-Speed Low-Noise CMOS Image Sensor With 13-b Column-Parallel Single-Ended Cyclic ADCs

Abstract: A high-performance CMOS image sensor (CIS) with 13-b column-parallel single-ended cyclic ADCs is presented The simplified single-ended circuits for the cyclic ADC are squeezed into a 56-mum-pitch single-side column The proposed internal reference generation and return-to-zero digital signal feedback techniques enhance the ADC to have low read noise, a high resolution of 13 b, and a resulting dynamic range of 71 dB An ultralow vertical fixed pattern noise of 01 erms - is attained by a digital CDS technique, which performs A/D conversion twice in a horizontal scan period (6 mus) The implemented CIS with 018-mum technology operates at 390 frames/s and has 707-V/lx middots sensitivity, 61- muV/e- conversion gain, 49-erms - read noise, and less than 04 LSB differential nonlinearity

Fringing-Induced Drain Current Improvement in the Tunnel Field-Effect Transistor With High- $\kappa$ Gate Dielectrics

Abstract: The tunnel field-effect transistor (tunnel FET) is a promising candidate for future CMOS technology. Its device characteristics have been subject to a variety of experimental and theoretical studies. In this paper, we evaluate the influence of using a high-kappa gate dielectric in the tunnel FET compared to a standard silicon oxide with same equivalent oxide thickness, which exhibits a quite different behavior compared to a conventional MOSFET due to its totally different working principle. It turns out that the fringing field effect, while deteriorating conventional MOSFET characteristics, leads to a much higher on-current comparable with actual conventional MOSFETs, a subthreshold slope of the tunnel FET lower than the theoretical limit for conventional MOSFETs, and a massive improved inverter delay, underlining its prospect for future applications. This leads to the conclusion that high-kappa materials with permittivities > 30 can advantageously be used in CMOS technology, giving rise to further technological development.

Modeling of Set/Reset Operations in NiO-Based Resistive-Switching Memory Devices

Abstract: Resistive-switching memory (RRAM) devices are attracting a considerable interest in view of their back-end integration, fast programming, and high scalability. Prediction of the programming voltages and currents as a function of the operating conditions is an essential task for developing compact and numerical models able to handle a large number (106 - 109) of cells within an array. Based on recent experimental findings on the set and reset processes, we have developed physics-based analytical models for the set and reset operations in NiO-based RRAMs. Simulation results obtained by the analytical models were compared with experimental data for variable pulse conditions and were found consistent with data. The set transition is described by a threshold switching process at the broken conductive filament (CF), while the reset transition is viewed as a thermally driven dissolution and/or oxidation of the CF. Set and reset models are finally used for reliability predictions of failure times under constant-voltage stress (read disturb) and elevated-temperature bake (data retention).