Showing papers in "IEEE Transactions on Electron Devices in 2013"
TL;DR: In this article, a detailed study of the doping-less tunnel field effect transistor (TFET) on a thin intrinsic silicon film using charge plasma concept was performed using calibrated simulations.
Abstract: Using calibrated simulations, we report a detailed study of the doping-less tunnel field effect transistor (TFET) on a thin intrinsic silicon film using charge plasma concept. Without the need for any doping, the source and drain regions are formed using the charge plasma concept by choosing appropriate work functions for the source and drain metal electrodes. Our results show that the performance of the doping-less TFET is similar to that of a corresponding doped TFET. The doping-less TFET is expected to be free from problems associated with random dopant fluctuations. Furthermore, fabrication of doping-less TFET does not require a high-temperature doping/annealing processes and therefore cuts down the thermal budget, opening up possibilities for fabricating TFETs on single crystal silicon-on-glass substrates formed by wafer scale epitaxial transfer.
433 citations
TL;DR: In this article, the authors report state-of-the-art high frequency performance of GaN-based high electron mobility transistors (HEMTs) and Schottky diodes achieved through innovative device scaling technologies such as vertically scaled enhancement and depletion mode (E/D mode) AlN/GaN/AlGaN double-heterojunction HEMT epitaxial structures.
Abstract: In this paper, we report state-of-the-art high frequency performance of GaN-based high electron mobility transistors (HEMTs) and Schottky diodes achieved through innovative device scaling technologies such as vertically scaled enhancement and depletion mode (E/D mode) AlN/GaN/AlGaN double-heterojunction HEMT epitaxial structures, a low-resistance n+-GaN/2DEG ohmic contact regrown by MBE, a manufacturable 20-nm symmetric and asymmetric self-aligned-gate process, and a lateral metal/2DEG Schottky contact. As a result of proportional scaling of intrinsic and parasitic delays, an ultrahigh fT exceeding 450 GHz (with a simultaneous fmax of 440 GHz) and a fmax close to 600 GHz (with a simultaneous fT of 310 GHz) are obtained in deeply scaled GaN HEMTs while maintaining superior Johnson figure of merit. Because of their extremely low on-resistance and high gain at low drain voltages, the devices exhibited excellent noise performance at low power. 501-stage direct-coupled field-effect transistor logic ring oscillator circuits are successfully fabricated with high yield and high uniformity, demonstrating the feasibility of GaN-based E/D-mode integrated circuits with transistors. Furthermore, self-aligned GaN Schottky diodes with a lateral metal/2DEG Schottky contact and a 2DEG/ n+-GaN ohmic contact exhibited RC-limited cutoff frequencies of up to 2.0 THz.
384 citations
TL;DR: In this article, a gate injection transistor (GIT) is proposed to increase the drain current with low on-state resistance by conductivity modulation, which greatly helps in increasing the efficiency of power switching systems.
Abstract: This paper reviews the recent activities for normally-off GaN-based gate injection transistors (GITs) on Si substrates and their application to inverters. Epitaxial growth of the AlGaN/GaN heterostructures with good crystallinity over 200-mm Si substrates with eliminated bowing enables low-cost fabrication of GaN devices with high breakdown voltages. A novel normally-off GaN transistor called as GIT is proposed in which hole injection from the p-type AlGaN gate increases the drain current with low on-state resistance by conductivity modulation. The low on-state resistance in GaN-based devices greatly helps to increase the efficiency of power switching systems. A GaN-based three-phase inverter successfully drives a motor with high efficiency of 99.3% at a high output power of 1500 W. The presented GaN-based devices are expected to greatly help saving energy in the future as an indispensable power switching system.
329 citations
TL;DR: In this paper, the advantages and limitations of the current-transient methods used for the study of the deep levels in GaN-based high-electron mobility transistors (HEMTs), by evaluating how the procedures adopted for measurement and data analysis can influence the results of the investigation.
Abstract: This paper critically investigates the advantages and limitations of the current-transient methods used for the study of the deep levels in GaN-based high-electron mobility transistors (HEMTs), by evaluating how the procedures adopted for measurement and data analysis can influence the results of the investigation. The article is divided in two parts within Part I. 1) We analyze how the choice of the measurement and analysis parameters (such as the voltage levels used to induce the trapping phenomena and monitor the current transients, the duration of the filling pulses, and the method used for the extrapolation of the time constants of the capture/emission processes) can influence the results of the drain current transient investigation and can provide information on the location of the trap levels responsible for current collapse. 2) We present a database of defects described in more than 60 papers on GaN technology, which can be used to extract information on the nature and origin of the trap levels responsible for current collapse in AlGaN/GaN HEMTs. Within Part II, we investigate how self-heating can modify the results of drain current transient measurements on the basis of combined experimental activity and device simulation.
320 citations
TL;DR: In this article, different physics-based negative bias temperature instability (NBTI) models as proposed in the literature are reviewed, and the predictive capability of these models is benchmarked against experimental data.
Abstract: Different physics-based negative bias temperature instability (NBTI) models as proposed in the literature are reviewed, and the predictive capability of these models is benchmarked against experimental data. Models that focus exclusively on hole trapping in gate-insulator-process-related preexisting traps are found to be inconsistent with direct experimental evidence of interface trap generation. Models that focus exclusively on interface trap generation are incapable of predicting ultrafast measurement data. Models that assume strong correlation between interface trap generation and hole trapping in switching hole traps cannot simultaneously predict long-time dc stress, recovery, and ac stress and cannot estimate gate insulator process impact. Uncorrelated contributions from generation and recovery of interface traps, together with hole trapping and detrapping in preexisting and newly generated bulk insulator traps, are invoked to comprehensively predict dc stress and recovery, ac duty cycle and frequency, and gate insulator process impact of NBTI. The reaction-diffusion model can accurately predict generation and recovery of interface traps for different devices and experimental conditions. Hole trapping/detrapping is modeled using a two-level energy well model.
266 citations
TL;DR: An original methodology to use conductive-bridge RAM (CBRAM) devices as, easy to program and low-power, binary synapses with stochastic learning rules with deterministic learning rules is demonstrated.
Abstract: In this paper, we present an alternative approach to neuromorphic systems based on multilevel resistive memory synapses and deterministic learning rules. We demonstrate an original methodology to use conductive-bridge RAM (CBRAM) devices as, easy to program and low-power, binary synapses with stochastic learning rules. New circuit architecture, programming strategy, and probabilistic spike-timing dependent plasticity (STDP) learning rule for two different CBRAM configurations with-selector (1T-1R) and without-selector (1R) are proposed. We show two methods (intrinsic and extrinsic) for implementing probabilistic STDP rules. Fully unsupervised learning with binary synapses is illustrated through two example applications: 1) real-time auditory pattern extraction (inspired from a 64-channel silicon cochlea emulator); and 2) visual pattern extraction (inspired from the processing inside visual cortex). High accuracy (audio pattern sensitivity > 2, video detection rate > 95%) and low synaptic-power dissipation (audio 0.55 μW, video 74.2 μW) are shown. The robustness and impact of synaptic parameter variability on system performance are also analyzed.
238 citations
TL;DR: Quokka as discussed by the authors is a simulation tool for 3D solar cell simulation, which is based on the full set of charge carrier transport equations, i.e., quasi-neutrality and conductive boundaries.
Abstract: Details of Quokka, which is a freely available fast 3-D solar cell simulation tool, are presented. Simplifications to the full set of charge carrier transport equations, i.e., quasi-neutrality and conductive boundaries, result in a model that is computationally inexpensive without a loss of generality. Details on the freely available finite volume implementation in MATLAB are given, which shows computation times on the order of seconds to minutes for a full I-V curve sweep on a conventional personal computer. As an application example, the validity of popular analytical models of partial rear contact cells is verified under varying conditions. Consequently, it is observed that significant errors can occur if these analytical models are used to derive local recombination properties from effective lifetime measurements of test structures.
227 citations
TL;DR: In this article, vertical p-n diodes fabricated on pseudobulk gallium nitride (GaN) substrates are discussed, and the measured devices demonstrate breakdown voltages of 2600 V with a differential specific on-resistance of 2 mΩ cm2.
Abstract: In this paper, vertical p-n diodes fabricated on pseudobulk gallium nitride (GaN) substrates are discussed. The measured devices demonstrate breakdown voltages of 2600 V with a differential specific on-resistance of 2 mΩ cm2. This performance places these structures beyond the SiC theoretical limit on the power device figure of merit chart. Contrary to common belief, GaN devices do possess avalanche capability. The temperature coefficient of the breakdown voltage is positive, showing that the breakdown is indeed because of impact ionization and avalanche. This is an important property of the device for operation in inductive switching environments. Critical electric field and mobility parameters for epitaxial GaN layers grown on bulk GaN are extracted from electrical measurements. The reverse recovery time of the vertical GaN p-n diode is not discernible because it is limited by capacitance rather than minority carrier storage, and because of this its switching performance exceeds the highest speed silicon diode.
211 citations
TL;DR: In this paper, an endurance/retention performance tradeoff was identified on the 40 nm × 40 nm HfO2/Metal cap bipolar RRAM devices in a 1T1R configuration.
Abstract: The endurance/retention performance of HfO2/ Metal cap RRAM devices in a 1T1R configuration shows metal cap dependence. For Hf and Ti caps, owning strong thermodynamic ability of extracting oxygen from HfO2, long pulse endurance (>1010 cycles) could be achieved. For Ta cap, owning lower thermodynamic ability of extracting oxygen from HfO2, better retention can be achieved. Therefore, an endurance/retention performance tradeoff is identified on the 40 nm × 40 nm HfO2/Metal cap bipolar RRAM devices. The tradeoff of endurance/retention performance can be explained by a different filament constriction shape depending on metal cap layer as derived from fitting I-V curves in the quantum point contact model. This difference in filament constriction shape is attributed to the thermodynamics difference of metal cap: Hf and Ti have a stronger thermodynamical ability to extract oxygen from HfO2 than Ta. The possibility of tuning the intrinsic reliability performance by changing the cap materials paves a way for optimizing the operation of RRAM devices into the desired specifics.
203 citations
TL;DR: In this article, a predictive model for device behavior that can be used in simulations and to guide designs of memristors has been proposed for high density, low power, and high speed memory.
Abstract: A key requirement for using memristors in circuits is a predictive model for device behavior that can be used in simulations and to guide designs We analyze one of the most promising materials, tantalum oxide, for high density, low power, and high-speed memory We perform an ensemble of measurements, including time dynamics across nine decades, to deduce the underlying state equations describing the switching in Pt/TaOx/Ta memristors A predictive, compact model is found in good agreement with the measured data The resulting model, compatible with SPICE, is then used to understand trends in terms of switching times and energy consumption, which in turn are important for choosing device operating points and handling interactions with other circuit elements
194 citations
TL;DR: In this article, the gate leakage mechanisms in AlInN/GaN and AlGaN/GAN high electron mobility transistors (HEMTs) are compared using temperature-dependent gate currentvoltage (IG-VG) characteristics.
Abstract: The gate leakage mechanisms in AlInN/GaN and AlGaN/GaN high electron mobility transistors (HEMTs) are compared using temperature-dependent gate current-voltage (IG-VG) characteristics. The reverse bias gate current of AlInN/GaN HEMTs is decomposed into three distinct components, which are thermionic emission (TE), Poole-Frenkel (PF) emission, and Fowler-Nordheim (FN) tunneling. The electric field across the barrier in AlGaN/GaN HEMTs is not sufficient to support FN tunneling. Hence, only TE and PF emission is observed in AlGaN/GaN HEMTs. In both sets of devices, however, an additional trap-assisted tunneling component of current is observed at low reverse bias. A model to describe the experimental IG-VG characteristics is proposed and the procedure to extract the associated parameters is described. The model follows the experimental gate leakage current closely over a wide range of bias and temperature for both AlGaN/GaN and AlInN/GaN HEMTs.
TL;DR: In this article, an ultrathin equivalent oxide thickness (EOT) HfO2/Al2O3/Ge gate stack has been fabricated by combining the plasma postoxidation method with a 0.2-nm-thick Al 2O3 layer between Hf2 and Ge, resulting in a low interface-state-density (Dit) GeOx/Ge metal-oxide-semiconductor (MOS) interface.
Abstract: An ultrathin equivalent oxide thickness (EOT) HfO2/Al2O3/Ge gate stack has been fabricated by combining the plasma postoxidation method with a 0.2-nm-thick Al2O3 layer between HfO2 and Ge for suppressing HfO2-GeOx intermixing, resulting in a low-interface-state-density (Dit) GeOx/Ge metal-oxide-semiconductor (MOS) interface. The EOT of these gate stacks has been scaled down to 0.7-0.8 nm with maintaining the Dit in 1011 cm-2·eV-1 level. The p- and n-channel MOS field-effect transistors (MOSFETs) (p- and n-MOSFETs) using this gate stack have been fabricated on (100) Ge substrates and exhibit high hole and electron mobilities. It is found that the Ge p- and n-MOSFETs exhibit peak hole mobilities of 596 and 546 cm2/V·s and peak electron mobilities of 754 and 689 cm2/V·s at EOTs of 0.82 and 0.76 nm, respectively, which are the record-high reports so far for Ge MOSFETs in subnanometer EOT range because of the sufficiently passivated Ge MOS interfaces in present HfO2/Al2O3/GeOx/Ge gate stacks.
IBM1
TL;DR: It is shown that neuromorphic systems based on new nanoscale devices can potentially improve density and power consumption by at least a factor of 10, as compared with conventional CMOS implementations.
Abstract: The goal of neuromorphic engineering is to build electronic systems that mimic the ability of the brain to perform fuzzy, fault-tolerant, and stochastic computation, without sacrificing either its space or power efficiency. In this paper, we determine the operating characteristics of novel nanoscale devices that could be used to fabricate such systems. We also compare the performance metrics of a million neuron learning system based on these nanoscale devices with an equivalent implementation that is entirely based on end-of-scaling digital CMOS technology and determine the technology targets to be satisfied by these new devices. We show that neuromorphic systems based on new nanoscale devices can potentially improve density and power consumption by at least a factor of 10, as compared with conventional CMOS implementations.
TL;DR: In this article, a comprehensive crossbar array model that incorporates line resistance and nonlinear device characteristics is presented, which can be solved using matrix algebra and is suitable for statistical analysis, and can be used for accurate analysis of crossbar arrays and the evaluation of memory select devices.
Abstract: This paper presents a comprehensive crossbar array model that incorporates line resistance and nonlinear device characteristics. The model can be solved using matrix algebra and is suitable for statistical analysis. The nonlinear device solution enables the assessment of crossbar arrays with diode or nonlinear select devices. The calculation based on this model shows that voltage and current degradation due to line resistance are not negligible even for small crossbar arrays, which constrains feasible array size. Diode and nonlinear select devices significantly improve the sensing margin of reading operation and the voltage window of writing operation. This model provides a quantitative tool for accurate analysis of crossbar arrays and the evaluation of memory select devices.
TL;DR: In this article, a physics-based compact model of metal-oxide-based resistive-switching random access memory (RRAM) cell under dc and ac operation modes is presented.
Abstract: A physics-based compact model of metal-oxide-based resistive-switching random access memory (RRAM) cell under dc and ac operation modes is presented. In this model, the conductive filament evolution corresponding to the resistive switching process is modeled by considering the transport behaviors of oxygen vacancies and oxygen ions together with the temperature effect. Both the metallic-like and electron hopping conduction transports are considered to model the conduction of RRAM. The model can reproduce both the typical I-V characteristics of RRAM in high-/low-resistance state (LRS) and the nonlinear characteristics in LRS. Moreover, to accurately model ac operation mode, the effects of parasitic capacitance and resistance are included in our model. The developed compact model is verified and calibrated by measured data in different HfOx-based RRAM devices under dc and ac operation modes. The excellent agreement between the model predictions and experimental results shows a promising prospect of the future implementation of this compact model in large-scale circuit simulation to optimize the design of RRAM.
TL;DR: In this article, a simulation method is developed to investigate the critical issues correlated with the interaction between devices and the circuit, and an optimal design scheme for turn-on voltage and conductance of the selector is proposed based on the simulation.
Abstract: The resistive random access memory (RRAM) crossbar array has been extensively studied as one of the most promising candidates for future high-density nonvolatile memory technology. However, some problems caused by circuit and device interaction, such as sneak leakage paths, result in limited array size and large power consumption, which degrade the array performance significantly. Thus, the analysis on circuit and device interaction issue is imperative. In this paper, a simulation method is developed to investigate the critical issues correlated with the interaction between devices and the circuit. The simulations show that a large off/on ratio of resistance states of RRAM is beneficial for large readout margin (i.e., array size). The existence of the selector connected in series with an RRAM device can eliminate the need for high Ron resistance, which is critical for the array consisted of only RRAM cells. The readout margin is more sensitive to the variation of Ron and is determined by the nonlinearity of the I-V characteristics of RRAM, whereas the nonlinear characteristics of the selector device are beneficial for a larger readout margin. An optimal design scheme for turn-on voltage and conductance of the selector is proposed based on the simulation.
TL;DR: In this paper, the development, performance, and status of lateral and vertical GaN devices are discussed, and the current and voltage demand for high power conversion application makes the chip area in a lateral topology so large that it becomes more difficult to manufacture.
Abstract: Power conversion losses are endemic in all areas of electricity consumption, including motion control, lighting, air conditioning, and information technology. Si, the workhorse of the industry, has reached its material limits. Increasingly, the lateral AlGaN/GaN HEMT based on gallium nitride (GaN-on-Si) is becoming the device of choice for medium power electronics as it enables high-power conversion efficiency and reduced form factor at attractive pricing for wide market penetration. The reduced form factor enabled by high-efficiency operation at high frequency further enables significant system price reduction because of savings in bulky extensive passive elements and heat sink costs. The high-power market, however, still remains unaddressed by lateral GaN devices. The current and voltage demand for high power conversion application makes the chip area in a lateral topology so large that it becomes more difficult to manufacture. Vertical GaN devices would play a big role alongside of silicon carbide (SiC) to address the high power conversion needs. In this paper, the development, performance, and status of lateral and vertical GaN devices are discussed.
TL;DR: In this article, the authors present self-consistent electrothermal simulations of single-finger and multifinger GaN vertical metal-oxide-semiconductor field effect transistors (MOSFETs) and lateral AlGaN/GaN high-electron-mobility transistors and compare their thermal performance.
Abstract: In this paper, we present self-consistent electrothermal simulations of single-finger and multifinger GaN vertical metal-oxide-semiconductor field-effect transistors (MOSFETs) and lateral AlGaN/GaN high-electron-mobility transistors (HEMTs) and compare their thermal performance. The models are first validated by comparison with experimental dc characteristics, and then used to study the maximum achievable power density of the device without the peak temperature exceeding a safe operation limit of 150°C (P150°C). It is found that the vertical MOSFETs have the potential to achieve a higher P150°C than the lateral HEMTs, especially for higher breakdown voltages and higher scaling level designs.
TL;DR: In this paper, double-gate molybdenum disulfide (MoS2) field effect transistors (FETs) with a monolayer thin body were examined and compared with ultrathin-body Si FETs by self-consistent quantum transport simulation in the presence of phonon scattering.
Abstract: The ultimate scaling limit of double-gate molybdenum disulfide (MoS2) field-effect transistors (FETs) with a monolayer thin body is examined and compared with ultrathin-body Si FETs by self-consistent quantum transport simulation in the presence of phonon scattering. Modeling of phonon scattering, quantum mechanical effects, and self-consistent electrostatics allows us to accurately assess the performance potential of monolayer MoS2 FETs. The results revealed that monolayer MoS2 FETs show 52% smaller drain-induced barrier lowering (DIBL) and 13% smaller subthreshold swing (SS) than 3-nm-thick-body Si FETs at a channel length of 10 nm with the same gating. With a requirement of DIBL , the scaling limit of monolayer MoS2 FETs is assessed to be 8 nm, comparing with 10 nm of the ultrathin-body Si counterparts due to the monolayer thin body and higher effective mass, which reduces direct source-to-drain tunneling. By comparing with the international technology roadmap for semiconductor (ITRS) target for high performance logic devices of 2023; double-gate monolayer MoS2 FETs can fulfill the ITRS requirements.
TL;DR: In this article, the authors analyzed the behavior of the internal charge dynamics in high-voltage (HV) semiconductors, giving a clear base to perform overall converter optimizations and to understand the previously proposed zero-current-switching techniques for insulated-gate bipolar transistor (IGBT)-based resonant dual active bridges.
Abstract: Soft-switching techniques are very attractive and often mandatory requirements in medium-voltage and medium-frequency applications such as solid-state transformers. The effectiveness of these soft-switching techniques is tightly related to the dynamic behavior of the internal stored charge in the utilized semiconductor devices. For this reason, this paper analyzes the behavior of the internal charge dynamics in high-voltage (HV) semiconductors, giving a clear base to perform overall converter optimizations and to understand the previously proposed zero-current-switching techniques for insulated-gate bipolar-transistor (IGBT)-based resonant dual active bridges. From these previous approaches, the two main concepts that allow switching loss reduction in HV semiconductors are identified: 1) shaping of the conducted current in order to achieve a high recombination time in the previously conducting semiconductors; and 2) achieving zero-voltage-switching (ZVS) in the turning-on device. The means to implement these techniques in a triangular-current-mode dual-active-bridge converter, together with the benefits of the proposed approaches, are analyzed and experimentally verified with a 1.7-kV IGBT-based neutral-point-clamped (NPC) bridge. Additionally, the impact of the modified currents in the converter's performance is quantified in order to determine the benefits of the introduced concepts in the overall converter.
TL;DR: In this paper, a source pocket Si TFET is presented and successfully fabricated by laser annealing, which has enhanced lateral electric field across the source tunneling junction, resulting in a reduction of tunneling distance.
Abstract: To reduce the power consumption and improve the device performance in scaled CMOS integrated circuits, transistors with steep subthreshold swing (SS) is highly desirable. The tunnel field-effect transistor (TFET) based on the band-to-band tunneling has been suggested as a replacement to conventional MOSFETs. In order to improve the device performance of TFET, enhanced carrier transport across the tunneling junction is crucial. In this paper, source-pocket Si TFET is presented and successfully fabricated by laser annealing. This TFET has enhanced lateral electric field across the source tunneling junction, resulting in a reduction of tunneling distance. The experimental data of the proposed paper, for the first time, shows steep SS (46 mV/dec at 1 pA/μm), excellent ION/IOFF ratio ( <; 107), and improved output characteristics at T = 300 K due to the dramatic reduction of the tunneling resistance. Compared with other TFET works, the proposed method is efficient to improve the device performance on TFET.
TL;DR: In this article, a comprehensive review of AlGaN/GaN high electron mobility transistor failure physics and reliability is presented, focusing on mechanisms affecting the gate-drain edge, where maximum electric field and peak temperatures are reached.
Abstract: This paper presents a comprehensive review of AlGaN/GaN high electron mobility transistor failure physics and reliability, focusing on mechanisms affecting the gate-drain edge, where maximum electric field and peak temperatures are reached. Physical effects at the origin of device degradation (inverse piezoelectric effect, time-dependent trap formation and percolative conductive paths formation, and electrochemical AlGaN and GaN degradation) are discussed on the basis of literature data and unpublished results. Thermally activated mechanisms involving metal-metal and metal-semiconductor interdiffusion at the gate Schottky junction are also discussed.
TL;DR: In this article, the dynamic ON-resistance (RON) of high-voltage GaN field effect transistors was investigated over a time span of ten decades under a variety of conditions.
Abstract: We have developed a new methodology to investigate the dynamic ON-resistance (RON) of high-voltage GaN field-effect transistors. The new technique allows the study of RON transients after a switching event over an arbitrary length of time. Using this technique, we have investigated dynamic RON transients in AlGaN/GaN high-voltage, high electron-mobility transistors over a time span of ten decades under a variety of conditions. We find that right after an OFF-to-ON switching event, RON can be several times higher under dc conditions. The increase in RON is enhanced as the drain-source voltage in the OFF-state increases. The RON recovery process after an OFF-to-ON switching event is characterized by a fast release of trapped charge through a temperature-independent tunneling process followed by conventional thermally activated detrapping on a longer timescale. After a high-power-to-ON switching event, in contrast, detrapping only takes place through a temperature-independent process. We postulate that the fast temperature-independent detrapping originates from interface states at the AlGaN barrier/AlN spacer interface. The thermally activated detrapping can arise from traps at the surface of the device or inside the AlGaN barrier. These findings are relevant in the quest to engineer a reliable GaN power switch with minimum dynamic RON problems.
TL;DR: Ferroelectric Si:HfO2 has been investigated starting from metal-ferroelectric-metal (MFM) capacitors over metal ferroelectric insulator-semiconductor (MFIS) and finally ferro electric field effect transistor (FeFET) devices as mentioned in this paper.
Abstract: Ferroelectric Si:HfO2 has been investigated starting from metal-ferroelectric-metal (MFM) capacitors over metal-ferroelectric-insulator-semiconductor (MFIS) and finally ferroelectric field-effect-transistor (FeFET) devices. Endurance characteristics and field cycling effects recognized for the material itself are shown to also translate to highly scaled 30-nm FeFET devices. Positive-up negative-down as well as pulsed Id-Vg measurements illustrate how ferroelectric material characteristics of MFM capacitors can also be identified in more complex MFIS and FeFET structures. Antiferroelectric-like characteristics observed for relatively high Si dopant concentration reveal significant trapping superimposed onto the ferroelectric memory window limiting the general program/erase endurance of the devices to 104 cycles. In addition, worst case disturb scenarios for a VDD/2 and VDD/3 scheme are evaluated to prove the viability of one-transistor memory cell concepts. The ability to tailor the ferroelectric properties by appropriate dopant concentration reveals disturb resilience up to 106 disturb cycles while maintaining an ION to IOFF ratio of more than four orders of magnitude.
TL;DR: In this paper, a 2D semianalytical solution for the electrostatic potential valid for junctionless symmetric double-gate field-effect transistors in sub-threshold regime is proposed, which is based on the parabolic approximation for the potential and removes previous limitations.
Abstract: A 2-D semianalytical solution for the electrostatic potential valid for junctionless symmetric double-gate field-effect transistors in subthreshold regime is proposed, which is based on the parabolic approximation for the potential and removes previous limitations. Based on such a solution, a semi-analytical expression for the current is derived. The potential and current models are validated through comparisons with TCAD simulations and are used to evaluate relevant short-channel effect parameters, such as threshold roll-off, drain-induced barrier lowering, and inverse subthreshold slope. The implications of different possible definitions of threshold voltage, either based on the potential in the channel or on a fixed current level, are discussed. Finally, a fully analytical simplification for the current is suggested, which can be used in compact models for circuit simulations.
TL;DR: In this paper, a silicon nanowire with a gate-all-around (GAA) structure is implemented on a bulk wafer for a junctionless (JL) field effect transistor (FET).
Abstract: A silicon nanowire (Si-NW) with a gate-all-around (GAA) structure is implemented on a bulk wafer for a junctionless (JL) field-effect transistor (FET). A suspended Si-NW from the bulk-Si is realized using a deep reactive ion etching (RIE) process. The RIE process is iteratively applied to make multiply stacked Si-NWs, which can increase the on-state current when amplified with the number of iterations or enable integration of 3-D stacked Flash memory. The fabricated JL FETs exhibit excellent electrostatic control with the aid of the GAA and junction-free structure. The influence on device characteristics according to the channel dimensions and additional doping at the source and drain extension are studied for various geometric structures of the Si-NW.
TL;DR: In this paper, a novel high-electron mobility transistor (HEMT) structure employing wider bandgap AlGaN for a channel layer, which is called Al-GaN channel HEMT, and investigated it.
Abstract: Enhanced performance of RF power modules is required in a next-generation information society. To satisfy these requirements, we designed a novel high-electron mobility transistor (HEMT) structure employing wider bandgap AlGaN for a channel layer, which we called AlGaN channel HEMT, and investigated it. The wider bandgap is more effective for higher voltage operation of HEMTs and contributes to the increase of output power in RF power modules. As a result, fabricated AlGaN channel HEMTs had much higher breakdown voltages than those of conventional GaN channel HEMTs with good pinchoff operation and sufficiently high drain current density without noticeable current collapse. Furthermore, specific on-state resistances of fabricated AlGaN channel HEMTs were competitive with the best values of reported GaN- and SiC-based devices with similar breakdown voltages. These results indicate that the proposed AlGaN channel HEMTs are very promising not only for an information-communication society but also in the power electronics field.
TL;DR: In this article, two types of fin-shaped field effect transistors (FinFETs), one with AlGaN/GaN heterojunction and the other with heavily doped heter-junction-free GaN layer operating in junctionless mode, have been fabricated and characterized.
Abstract: Two types of fin-shaped field-effect transistors (FinFETs), one with AlGaN/GaN heterojunction and the other with heavily doped heterojunction-free GaN layer operating in junctionless mode, have been fabricated and characterized. The threshold voltages of both devices shift toward positive direction from large negative value as the fin width decreases. Both devices exhibit high ON-state performance. The heterojunction-free GaN FinFETs show superior OFF-state performance because the current flows through the volume of the GaN channel layer, which can be fully depleted. The proposed GaN nanochannel FinFETs are very promising candidates not only for high performance, but also for high power applications.
TL;DR: An overview of recently reported low-noise amplifiers (LNAs) designed, fabricated, and fabricated in GaN technology is provided, highlighting their noise performance together with high-linearity and high-robustness capabilities.
Abstract: In this paper, an overview of recently reported low-noise amplifiers (LNAs), designed, and fabricated in GaN technology is provided, highlighting their noise performance together with high-linearity and high-robustness capabilities. Several SELEX-ES GaN monolithic technologies are detailed, providing the results of the noise characterization and modeling on sample devices. An in-depth review of three LNAs based on the 0.25- μm GaN HEMT process, marginally described in previous publications, is then presented. In particular, two robust and broadband 2-18-GHz monolithic microwave integrated circuit (MMIC) LNAs are designed, fabricated, and tested, exhibiting robustness to over 40-dBm input power levels; an X-band MMIC LNA, suitable for synthetic aperture radar systems, is also designed and realized, for which measurement results show a noise figure ~ 2.2 dB with an associated gain and robustness up to 41-dBm input power level.
TL;DR: In this article, the retention model of a bipolar ReRAM considering the percolative paths in a conductive filament is proposed, and it is shown that the control of oxygen vacancy concentration in the filament is the key for ensuring data retention including tail bits.
Abstract: The retention model of a bipolar ReRAM considering the percolative paths in a conductive filament is proposed. We demonstrate, for the first time, that the control of oxygen vacancy concentration in a conductive filament is the key for ensuring data retention including tail bits. To improve the retention property under low-current operation, the size of the conductive filament must be scaled down while keeping the density of oxygen vacancy high enough. Based on this concept, we demonstrate both low-current operation and sufficient retention results exceeding 500 h at 150°C, which correspond to more than 10 years at 85°C.